TWI504155B - 60/24ghz dual-band signal generator system and method - Google Patents

Description

60 GHz and 24 GHz dual frequency signal source generator system and method

The present invention relates to the technical field of phase-locked loops, and more particularly to a 60 GHz and 24 GHz dual-frequency signal source generator system and method.

Recently, two important and unregistered frequency bands for millimeter-wave broadband communication or sensing system planning are the 24 GHz band and the 60 GHz band. In the 24 GHz band and the 60 GHz band, the local oscillator signal source needs to be connected by a separate phase-locked loop to provide a stable buck reference signal, so the component cost required for system integration will be twice. In view of the development of communication systems in the GHz, the demand for multi-band applications (such as LTE systems) can be found, so when considering the future development of the millimeter-wave communication band, the requirements of 60 GHz and 24 GHz coexistence systems will also be considered.

Most of the existing local oscillator signal source generators utilize the design of a phase-locked loop (PLL) and concentrate on the output of a single frequency. Therefore, the most straightforward approach to how to provide 60 GHz and 24 GHz band applications is to utilize two PLL circuits to provide the desired frequency output.

M Simon, P. Laaser, E. Riccio, U. Basaran, D. Friedrich, Y. Raman, H. Geltinger, A. Holm, published in Proc. of the 1 ^st European Wireless Technology Conf., 2008 EuMA , 2008 In the paper "A High Performance Dual Band/Dual Mode CMOS RF Transceiver for WiMAX and WLAN Systems", it is proposed that a PLL circuit contains a plurality of voltage controlled oscillators (VCOs) to generate signals of different frequencies. Its output frequency band is 2.5GHz and 3.5GHz.

And H.-K. Chen, T. Wang, and S.-S. Lu in IEEE Trans. on Microwave Theory and Tech. , vol . 59, no . 5, pp. 1327-1338, May 2011 The hardware architecture proposed in the Millimeter-Wave CMOS Triple-Band Phase-Locked Loop with A Multimode LC-Based ILFD paper also uses a PLL circuit with multiple voltage-controlled oscillators (VCOs) to generate multiple Signals of different frequencies. Its output frequency bands are at 40 GHz, 60 GHz and 80 GHz.

And W.-Z.Chen and D.-Y.Yu proposed in the paper "A Dual-Band Four-Mode △-Σ Frequency Synthesizer" proposed by IEEE Radio Frequency Integrated Circuits Symposium, (RFIC 2006) , 2006 The hardware architecture uses a PLL circuit with a VCO, and then the divider is used to achieve different frequency outputs. Its output frequency band is 5GHz and 2.4GHz.

J.-Y.Lee, H.Kim, H.-K.Yu in ^{Proc.of the 3 rd European Microwave Integrated Circuits} Conf., (EuMIC 2008), 2008 proposed "A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz The hardware architecture proposed in the WPAN Radio paper uses a PLL circuit with a VCO and a frequency multiplier to achieve different frequency outputs. The VCO output frequency band is output at 24-26 GHz and the 48-52 GHz signal is output for the down-conversion mixing of the front-end circuit receiver.

In the aforementioned paper, the use of multiple phase-locked loops (PLLs) increases the chip area and power consumption. Using multiple voltage controlled oscillators (VCOs) or using a VCO plus a frequency divider or frequency multiplier, due to the special nature of the two frequencies of 60 GHz and 24 GHz, it is not easy to simultaneously generate 60 GHz and 24GHz frequency output. Therefore, this patent proposes a new technology to complete the 60 GHz and 24 GHz dual frequency output.

The main object of the present invention is to provide a 60 GHz and 24 GHz dual-frequency signal source generating system and method, which can integrate a signal source generator circuit capable of simultaneously generating 60 GHz and 24 GHz to save circuit manufacturing cost. The circuit architecture of the present invention has its innovative design concept, the development advantages of the high divisor frequency division circuit, and a coexistence circuit architecture derived from the injection-locked oscillator circuit.

According to a feature of the present invention, the present invention provides a 60 GHz and 24 GHz dual-frequency signal source generating method, the method comprising the steps of: (A) providing a reference signal source; (B) using a phase-locked loop according to the reference signal source, Generating a first output signal having a frequency of 50 GHz to 70 GHz; (C) using a frequency dividing device to divide the frequency of the first output signal by 5 to generate a frequency dividing signal; (D) using a frequency dividing signal The frequency multiplying device multiplies the frequency division signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.

According to another feature of the present invention, the present invention provides a 60 GHz and 24 GHz dual frequency signal source generating system including a phase locked loop, a frequency dividing device, and a frequency doubling device. The phase locked loop is based on the frequency of a reference signal source to generate a first output signal having a frequency of 50 GHz to 70 GHz. The frequency dividing device is connected to the phase locked loop, and divides the frequency of the first output signal by a frequency dividing operation of 5 to generate a frequency dividing signal. The frequency multiplying device is connected to the frequency dividing device, and multiplies the frequency dividing signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.

1 is a schematic diagram of one embodiment of a 60 GHz and 24 GHz dual frequency signal source generation system 100 of the present invention. 2 is a block diagram of one embodiment of a 60 GHz and 24 GHz dual frequency signal source generation system 100 of the present invention. The 60 GHz and 24 GHz dual-frequency signal source generating system 100 includes a phase locked loop 110, a frequency dividing device 120, a frequency doubling device 130, and a switch 140.

The phase locked loop 110 is responsive to the frequency of a reference signal source (Vref) to generate a first output signal having a frequency of 60 GHz ISM application band (eg, 50 GHz to 70 GHz). The frequency of the first output signal is preferably 60 GHz.

The frequency dividing device 120 is connected to the phase locked loop, and divides the frequency of the first output signal by a frequency dividing operation of 5 to generate a frequency dividing signal. Wherein, the frequency of the frequency-divided signal is 12 GHz

The frequency multiplying device 130 is connected to the frequency dividing device 120, and multiplies the frequency dividing signal by a frequency multiplication operation to generate a second output signal having a frequency of 24 GHz ISM application frequency band (for example, 20 GHz to 28 GHz). The frequency of the second output signal is preferably 24 GHz. The frequency multiplying device 130 is an injection-locked oscillator.

The switch 140 is connected to the phase locked loop 110 and the frequency multiplying device 140 to select the first output signal or the second output signal as an output signal.

The phase locked loop 110 includes a detector 210, a charge pump 220, a phase locked loop filter 230, a controllable oscillator 240, and a programmable frequency dividing device 250.

The detector 210 generates a detection signal according to the difference between the frequency or phase of the logic signal of the reference signal source and a feedback signal.

The charge pump 220 is coupled to the detector 210 to generate a control signal according to the detection signal.

The phase locked loop filter 230 is coupled to the charge pump 220 to generate an adjustment signal according to the control signal. The phase locked loop filter 230 is a low pass filter.

The controllable oscillator 240 is coupled to the phase-locked loop filter 230 to generate the first output signal according to the adjustment signal. The first output signal is a differential output signal.

The programmable frequency dividing device 250 is coupled to the frequency dividing device 120 to generate the feedback signal according to the frequency dividing signal.

3 is a schematic diagram of the frequency dividing device 120 of the present invention. As can be seen from FIG. 3, the frequency division of the first output signal (V+, V-) is divided by 5 to generate the frequency-divided signal (Vo+, Vo-). The first output signal (V+, V-) is multiplied with a signal with a frequency of 4f ₀ to generate signals with frequencies f ₀ and 9f ₀ respectively (f ₀ = 5f _{0 -} 4f ₀ , 9f ₀ =5f ₀ +4f ₀ ). Then, by filtering the signal with the frequency of 9f ₀ through the bandpass filter BPF@f ₀ , the frequency-divided signal (Vout+, Vout-) having the frequency f ₀ can be generated. The signals with frequencies f ₀ and 9f ₀ pass through the non-linear amplifier and the bandpass filter BPF@2f ₀ to generate the signal with the frequency 4f ₀ .

4 is a circuit diagram of the frequency dividing device 120 of the present invention. The frequency dividing device 120 includes an inductor L2, an inductor L3, a capacitor C1, and an adjustable capacitor Cvar3, Cvar4, and transistors M5~M8. The transistors M5 to M8 are preferably NMOS transistors.

The source of the NMOS transistor M5 and the source of the NMOS transistor M6 are connected to the ground potential, the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6, an output terminal Out4, and the adjustable One end of the capacitor Cvar4, the drain of the NMOS transistor M8, and one end of the inductor L2. The drain of the NMOS transistor M5 is connected to the gate of the NMOS transistor M6, an output terminal Out3, one end of the adjustable capacitor Cvar3, the drain of the NMOS transistor M7, and the other end of the inductor L2. The middle of the inductor L2 is connected to the high potential, the other end of the adjustable capacitor Cvar3 is connected to the other end of the adjustable capacitor Cvar4, the source of the NMOS transistor M7 is connected to the source of the NMOS transistor M8, and One end of the capacitor C1, the NMOS transistor M7 and the gate of the NMOS transistor M8 are connected to the first output signal (V+, V-), and the other end of the capacitor C1 is connected to the inductor L3, the inductor L3 The other end is connected to the low potential.

FIG 3 the band pass filter BPF @ f ₀ by the inductor L2, the adjustable capacitor Cvar3, Cvar4 composed of band-pass filter BPF @ 2f ₀ of the inductor L3 and the capacitor C1 is composed. The non-linear portion of the NMOS transistors M7, M8 of Figure 4 is then modeled as the non-linear amplifier Amp of Figure 3. The operation of the circuit of Figure 4 can be seen from the schematic diagram of Figure 3.

The frequency multiplying device 130 is an injection-locked oscillator. Figure 5 is a circuit diagram of the frequency multiplying device 130 of the present invention. The injection-locked oscillator 130 includes an inductor L1, an adjustable capacitor Cvar1, Cvar2, transistors M1 to M4, and a first filter Filter1. The transistors M1 to M4 are preferably NMOS transistors.

As shown in FIG. 5, a first end of the first inductor L1 is connected to an output terminal Vout+, and the other end is connected to an output terminal Vout-, and the middle of the inductor L1 is connected to a high potential Vdd, the adjustable capacitor A first end of the Cvar1 is connected to the output terminal Vout+, and the other end is connected to a first end of the adjustable capacitor Cvar2, and the other end of the adjustable capacitor Cvar2 is connected to the output terminal Vout-, the NMOS transistor M1 The drain is connected to the output terminal Vout+ and the gate of the NMOS transistor M2, and the gate of the NMOS transistor M1 is connected to the output terminal Vout- and the drain of the NMOS transistor M2, the NMOS transistor M1 The source is connected to the source of the NMOS transistor M2, the drain of the NMOS transistor M3, the drain of the NMOS transistor M4, and the first filter Filter1, the source of the NMOS transistor M3, and the NMOS. The source of the transistor M4 is connected to a low potential gnd, and the gate of the NMOS transistor M3 and the gate of the NMOS transistor M4 are connected to the demultiplexed signal (Vo+, Vo-). The first filter Filter1 suppresses the 24 GHz and increases the 48 GHz.

The OFDM transistor is used in the frequency dividing device 120 and the frequency doubling device 130, and the analog circuit designer can easily convert to use a PMOS transistor. At the same time, whether using an NMOS transistor or a PMOS transistor, the N-type or P-type made by the semiconductor process can be used according to the semiconductor process design kit (PDK) provided by the fab. Transistor.

6 is a flow chart of a method for generating a 60 GHz and 24 GHz dual-frequency signal source according to the present invention, which is used to generate a 60 GHz signal and a 24 GHz signal. Please refer to the 60 GHz and 24 GHz dual-frequency signal source generation system 100 of the present invention. First, a reference signal source Vref is provided in step (A); and in step (B) A phase-locked loop is used according to the reference signal source to generate a first output signal having a frequency of 50 GHz to 70 GHz.

In step (C), a frequency dividing device is used, and the frequency of the first output signal is divided by 5 to generate a frequency dividing signal.

In step (D), a frequency doubling device is used to multiply the frequency division signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.

It can be seen from the foregoing description that the innovative spirit of the circuit architecture of the present invention grasps the relationship between the 60 GHz frequency and the 24 GHz frequency, and proposes a 60 GHz and 24 GHz dual-frequency co-existing phase-locked loop architecture to cope with the future in the millimeter wave ISM band 60-GHz and 24 The design of a local oscillator signal source (LO) generator required for a -GHz dual-band transceiver system.

The present invention differs from the conventional design concept in that the dual-frequency local oscillator source (LO) circuit of the present invention is not implemented by two phase-locked loops, nor does it utilize the concept of a conventional frequency multiplier to produce an output frequency of 24 GHz. Conventional techniques utilize two phase-locked loops that waste wafer area and power consumption, while conventional frequency multiplier circuits can degrade phase noise.

The invention has the advantage of integrating a signal source generator circuit capable of simultaneously generating 60 GHz and 24 GHz by a single phase-locked loop design concept to save circuit manufacturing costs (including the number of components or circuit size). The circuit architecture of the present invention is applicable to the fabrication of integrated circuits with less power and area losses. In addition, the circuit architecture of the present invention has its innovative design concept, that is, the development advantages of the high divisor frequency dividing circuit and A coexistence circuit architecture derived from an injection-locked oscillator circuit.

From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are distinguished from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

100‧‧‧60GHz and 24GHz dual-frequency signal source generator system

110‧‧‧ phase-locked loop

120‧‧‧Dividing device

130‧‧‧Multiplier

140‧‧‧Switcher

210‧‧‧Detector

220‧‧‧Charge pump

230‧‧‧ phase-locked loop filter

240‧‧‧Controllable Oscillator

250‧‧‧Programmable frequency divider

Step (A) ~ Step (D)

1 is a schematic diagram of one embodiment of a 60 GHz and 24 GHz dual frequency source generator system of the present invention.

2 is a block diagram of one embodiment of a 60 GHz and 24 GHz dual frequency source generator system of the present invention.

3 is a schematic diagram of the frequency dividing device of the present invention.

4 is a circuit diagram of the frequency dividing device of the present invention.

Figure 5 is a circuit diagram of the frequency multiplying device of the present invention.

6 is a flow chart of a method for generating a 60 GHz and 24 GHz dual-frequency signal source according to the present invention.

100‧‧‧60GHz and 24GHz dual-frequency signal source generator system

110‧‧‧ phase-locked loop

120‧‧‧Dividing device

130‧‧‧Multiplier

140‧‧‧Switcher

Claims (15)

A 60 GHz and 24 GHz dual-frequency signal source generating system includes: a phase-locked loop, based on a frequency of a reference signal source, to generate a first output signal having a frequency of 50 GHz to 70 GHz; and a frequency dividing device connected to the phase lock phase a loop dividing the frequency of the first output signal by 5 to generate a frequency-dividing signal; and a frequency multiplying device connected to the frequency-dividing device to multiply the frequency-divided signal by a frequency multiplying operation a second output signal having a frequency of 20 GHz to 28 GHz, the frequency doubling device is an injection locking oscillating device, wherein the injection locking oscillating device comprises a first inductor, first and second adjustable capacitors, first to first a fourth transistor, and a first filter; wherein the first filter suppresses the 24 GHz and boosts 48 GHz. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 1, wherein the frequency of the first output signal is 60 GHz, the frequency of the frequency-divided signal is 12 GHz, and the frequency of the second output signal is 24 GHz. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 2, wherein the first to fourth electro-crystalline system NMOS transistors. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 3, wherein a first end of the first inductor is connected to a first output end (Vout+), and the other end is connected to a second end. An output terminal (Vout-), the middle of the first inductor is connected to a high potential (Vdd), and a first end of the first adjustable capacitor is connected to the first output terminal (Vout+), and the other One end is connected to a first end of the second adjustable capacitor, the other end of the second adjustable capacitor is connected to the second output end (Vout-), and the drain of the first NMOS transistor is connected to the first end An output terminal (Vout+) and a gate of the second NMOS transistor, wherein a gate of the first NMOS transistor is connected to the second output terminal (Vout-) and a drain of the second NMOS transistor, the first a source of the NMOS transistor is coupled to a source of the second NMOS transistor, a drain of the third NMOS transistor, a drain of the fourth NMOS transistor, and the first filter, the third NMOS The source of the crystal and the source of the fourth NMOS transistor are connected to a low potential (gnd), and the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the demultiplexed signal. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 4, wherein the frequency dividing device comprises a second inductor, a third inductor, a first capacitor, a third capacitor, and a fourth adjustable capacitor. And the fifth to eighth transistors. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 5, wherein the fifth to eighth electro-crystalline system NMOS transistors. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 6, wherein the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected to the ground potential, the fifth The gate of the NMOS transistor is connected to the drain of the sixth NMOS transistor, a fourth output terminal, one end of the fourth adjustable capacitor, the drain of the eighth NMOS transistor, and one end of the second inductor The drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, a third output terminal, and the third adjustable One end of the entire capacitor, the drain of the seventh NMOS transistor, and the other end of the second inductor, the middle of the second inductor is connected to the high potential, and the other end of the third adjustable capacitor is connected to the fourth The other end of the capacitor can be adjusted, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, and the end of the first capacitor, the seventh NMOS transistor and the eighth NMOS transistor The gate is connected to the first output signal, the other end of the first capacitor is connected to the third inductor, and the other end of the third inductor is connected to the low potential. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 7 , further comprising: a switch connected to the phase locked loop and the frequency multiplying device to select the first output signal or the first The second output signal is used as the output signal. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 8 , wherein the phase locked loop comprises: a detector according to a logic signal frequency or phase of the reference signal source and a feedback signal a difference, which in turn generates a detection signal; a charge pump coupled to the detector to generate a control signal according to the detection signal; a phase-locked loop filter coupled to the charge pump to generate a control signal according to the control signal Adjusting a signal; a controllable oscillator coupled to the phase locked loop filter to generate the first output signal according to the adjustment signal; and a programmable frequency dividing device coupled to the frequency dividing device for The frequency signal generates the feedback signal. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 9 , wherein the phase locked loop filter is a low pass filter. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 10, wherein the first output signal is a differential output signal. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 2, wherein the first to fourth electro-crystalline system PMOS transistors. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 2, wherein the first to fourth electro-crystalline system semiconductor processes are fabricated by a transistor. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 5, wherein the fifth to eighth electro-crystalline system PMOS transistors. The 60 GHz and 24 GHz dual-frequency signal source generating system according to claim 5, wherein the fifth to eighth electro-crystalline system semiconductor processes are fabricated by a semiconductor.