TWI504155B - 60/24ghz dual-band signal generator system and method - Google Patents
60/24ghz dual-band signal generator system and method Download PDFInfo
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本發明係關於鎖相迴路之技術領域,尤指一種60GHz及24GHz雙頻訊號源產生器系統及方法。 The present invention relates to the technical field of phase-locked loops, and more particularly to a 60 GHz and 24 GHz dual-frequency signal source generator system and method.
近來,在毫米波寬頻的通訊或感測系統規劃上兩個重要且不需註冊的頻段就是24GHz頻段及60GHz頻段。在24GHz頻段及60GHz頻段兩系統中,局部振盪訊號源需由個別的鎖相迴路,以便提供穩定的升降頻參考訊號,因此系統整合上所需的元件成本將是兩倍。鑑於在數GHz的通訊系統發展中,可以發現多頻帶應用的需求性(如LTE系統),所以在考量未來發展到毫米波通訊頻帶時,也將必然要考量60GHz和24GHz共存系統的需求。 Recently, two important and unregistered frequency bands for millimeter-wave broadband communication or sensing system planning are the 24 GHz band and the 60 GHz band. In the 24 GHz band and the 60 GHz band, the local oscillator signal source needs to be connected by a separate phase-locked loop to provide a stable buck reference signal, so the component cost required for system integration will be twice. In view of the development of communication systems in the GHz, the demand for multi-band applications (such as LTE systems) can be found, so when considering the future development of the millimeter-wave communication band, the requirements of 60 GHz and 24 GHz coexistence systems will also be considered.
現有局部振盪訊號源產生器多是利用鎖相迴路(PLL)的設計並集中在單一頻率的輸出。因此,針對如何提供60GHz和24GHz頻帶應用的最直接的方法係利用兩個PLL電路來提供所需的頻率輸出。 Most of the existing local oscillator signal source generators utilize the design of a phase-locked loop (PLL) and concentrate on the output of a single frequency. Therefore, the most straightforward approach to how to provide 60 GHz and 24 GHz band applications is to utilize two PLL circuits to provide the desired frequency output.
於M Simon,P.Laaser,E.Riccio,U.Basaran,D.Friedrich,Y.Raman,H.Geltinger,A.Holm在Proc.of the 1 st European Wireless Technology Conf.,2008 EuMA,2008所發表的「A High Performance Dual Band/Dual Mode CMOS RF Transceiver for WiMAX and WLAN Systems」論文中,提出一個PLL電路內含多顆壓控振盪器(VCO)來產生多個不同頻率的訊號。其輸出頻段在2.5GHz和3.5GHz。 M Simon, P. Laaser, E. Riccio, U. Basaran, D. Friedrich, Y. Raman, H. Geltinger, A. Holm, published in Proc. of the 1 st European Wireless Technology Conf., 2008 EuMA , 2008 In the paper "A High Performance Dual Band/Dual Mode CMOS RF Transceiver for WiMAX and WLAN Systems", it is proposed that a PLL circuit contains a plurality of voltage controlled oscillators (VCOs) to generate signals of different frequencies. Its output frequency band is 2.5GHz and 3.5GHz.
而H.-K.Chen,T.Wang,andS.-S.Lu在IEEE Trans.on Microwave Theory and Tech.,vol.59,no.5,pp.1327-1338,May 2011所提出的「A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop with A Multimode LC-Based ILFD」論文中所提出的硬體架構,其亦使用一個PLL電路,其中內含多顆壓控振盪器(VCO)來產生多個不同頻率的訊號。其輸出頻段在40GHz、60GHz和80GHz。 And H.-K. Chen, T. Wang, and S.-S. Lu in IEEE Trans. on Microwave Theory and Tech. , vol . 59, no . 5, pp. 1327-1338, May 2011 The hardware architecture proposed in the Millimeter-Wave CMOS Triple-Band Phase-Locked Loop with A Multimode LC-Based ILFD paper also uses a PLL circuit with multiple voltage-controlled oscillators (VCOs) to generate multiple Signals of different frequencies. Its output frequency bands are at 40 GHz, 60 GHz and 80 GHz.
而W.-Z.Chen and D.-Y.Yu在IEEE Radio Frequency Integrated Circuits Symposium,(RFIC 2006),2006所提出的「A Dual-Band Four-Mode △-Σ Frequency Synthesizer」論文中所提出的硬體架構,其使用一個PLL電路內含一顆VCO,再應用除頻器達成不同的頻率輸出。其輸出頻段在5GHz和2.4GHz。 And W.-Z.Chen and D.-Y.Yu proposed in the paper "A Dual-Band Four-Mode △-Σ Frequency Synthesizer" proposed by IEEE Radio Frequency Integrated Circuits Symposium, (RFIC 2006) , 2006 The hardware architecture uses a PLL circuit with a VCO, and then the divider is used to achieve different frequency outputs. Its output frequency band is 5GHz and 2.4GHz.
J.-Y.Lee,H.Kim,H.-K.Yu在Proc.of the 3 rd European Microwave Integrated Circuits Conf.,(EuMIC 2008),2008所提出的「A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz WPAN Radio」論文中所提出的硬體架構,其使用一個PLL電路內含一顆VCO再應用倍頻器達成不同的頻率輸出。其VCO輸出頻段在24-26GHz並倍頻後輸出48-52GHz的訊號供前端電路接收機的降頻混頻用。 J.-Y.Lee, H.Kim, H.-K.Yu in Proc.of the 3 rd European Microwave Integrated Circuits Conf., (EuMIC 2008), 2008 proposed "A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz The hardware architecture proposed in the WPAN Radio paper uses a PLL circuit with a VCO and a frequency multiplier to achieve different frequency outputs. The VCO output frequency band is output at 24-26 GHz and the 48-52 GHz signal is output for the down-conversion mixing of the front-end circuit receiver.
前述論文中,使用多個鎖相迴路(PLLs),會增加晶片面積及功耗。使用多個壓控振盪器(VCO)或是使用一顆VCO加上一個除頻器或倍頻器等方式,由於受限於60GHz與24GHz頻率兩頻率的特殊性,無法容易地同時產生60GHz與24GHz頻率輸出。因此,本專利案提出一新的技術來完成60GHz與24GHz雙頻輸出。 In the aforementioned paper, the use of multiple phase-locked loops (PLLs) increases the chip area and power consumption. Using multiple voltage controlled oscillators (VCOs) or using a VCO plus a frequency divider or frequency multiplier, due to the special nature of the two frequencies of 60 GHz and 24 GHz, it is not easy to simultaneously generate 60 GHz and 24GHz frequency output. Therefore, this patent proposes a new technology to complete the 60 GHz and 24 GHz dual frequency output.
本發明之主要目的係在提供一種60GHz及24GHz雙頻訊號源產生系統及方法,可整合一個可以同時產生60GHz和24GHz的訊號源產生器電路,以節省電路製作成本。本發明的電路架構有其創新的設計概念,可在高除數除頻電路的開發優勢及結合注入鎖定振盪器電路所衍生出來的一個共存電路架構。 The main object of the present invention is to provide a 60 GHz and 24 GHz dual-frequency signal source generating system and method, which can integrate a signal source generator circuit capable of simultaneously generating 60 GHz and 24 GHz to save circuit manufacturing cost. The circuit architecture of the present invention has its innovative design concept, the development advantages of the high divisor frequency division circuit, and a coexistence circuit architecture derived from the injection-locked oscillator circuit.
依據本發明之一特色,本發明提出一種60GHz及24GHz雙頻訊號源產生方法,該方法包含步驟:(A)提供一參考訊號源;(B)使用一鎖相迴路依據該參考訊號源,以產生一頻率為50GHz至70GHz之第一輸出訊號;(C)使用一除頻裝置,對該第一輸出訊號的頻率進行除5之除頻操作,以產生一除頻訊號;(D)使用一倍頻裝置,對該除頻訊號進行乘2之倍頻操作,以產生一頻率為20GHz至28GHz之第二輸出訊號。 According to a feature of the present invention, the present invention provides a 60 GHz and 24 GHz dual-frequency signal source generating method, the method comprising the steps of: (A) providing a reference signal source; (B) using a phase-locked loop according to the reference signal source, Generating a first output signal having a frequency of 50 GHz to 70 GHz; (C) using a frequency dividing device to divide the frequency of the first output signal by 5 to generate a frequency dividing signal; (D) using a frequency dividing signal The frequency multiplying device multiplies the frequency division signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.
依據本發明之另一特色,本發明提出一種60GHz及24GHz雙頻訊號源產生系統,包括一鎖相迴路、一除頻裝置、及一倍頻裝置。該鎖相迴路依據一參考訊號源的頻率,以產生一頻率為50GHz至70GHz之第一輸出訊號。該除頻裝置連接至該鎖相迴路,對該第一輸出訊號的頻率進行除5之除頻操作,以產生一除頻訊號。該倍頻裝置連接至該除頻裝置,對該除頻訊號進行乘2之倍頻操作,以產生一頻率為20GHz至28GHz之第二輸出訊號。 According to another feature of the present invention, the present invention provides a 60 GHz and 24 GHz dual frequency signal source generating system including a phase locked loop, a frequency dividing device, and a frequency doubling device. The phase locked loop is based on the frequency of a reference signal source to generate a first output signal having a frequency of 50 GHz to 70 GHz. The frequency dividing device is connected to the phase locked loop, and divides the frequency of the first output signal by a frequency dividing operation of 5 to generate a frequency dividing signal. The frequency multiplying device is connected to the frequency dividing device, and multiplies the frequency dividing signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.
圖1係本發明之60GHz及24GHz雙頻訊號源產生系統100之一實施例的示意圖。圖2係本發明之60GHz及24GHz雙頻訊號源產生系統100之一實施例的方塊圖。該60GHz及24GHz雙頻訊號源產生系統100包括一鎖相迴路110、一除頻裝置120、一倍頻裝置130、及一切換器140。 1 is a schematic diagram of one embodiment of a 60 GHz and 24 GHz dual frequency signal source generation system 100 of the present invention. 2 is a block diagram of one embodiment of a 60 GHz and 24 GHz dual frequency signal source generation system 100 of the present invention. The 60 GHz and 24 GHz dual-frequency signal source generating system 100 includes a phase locked loop 110, a frequency dividing device 120, a frequency doubling device 130, and a switch 140.
該鎖相迴路110依據一參考訊號源(Vref)的頻率,以產生一頻率為60GHz ISM應用頻帶(例如:50GHz至70GHz)之第一輸出訊號。其中,該第一輸出訊號之頻率較佳為60GHz。 The phase locked loop 110 is responsive to the frequency of a reference signal source (Vref) to generate a first output signal having a frequency of 60 GHz ISM application band (eg, 50 GHz to 70 GHz). The frequency of the first output signal is preferably 60 GHz.
該除頻裝置120連接至該鎖相迴路,對該第一輸出訊號的頻率進行除5之除頻操作,以產生一除頻訊號。其中,該除頻訊號之頻率為12GHz The frequency dividing device 120 is connected to the phase locked loop, and divides the frequency of the first output signal by a frequency dividing operation of 5 to generate a frequency dividing signal. Wherein, the frequency of the frequency-divided signal is 12 GHz
該倍頻裝置130連接至該除頻裝置120,對該除頻訊號進行乘2之倍頻操作,以產生一頻率為24GHz ISM應用頻帶(例如:20GHz至28GHz)之第二輸出訊號。其中,該第二輸出訊號之頻率較佳為24GHz。該倍頻裝置130係一注入鎖定振盪裝置(injection-locked oscillator)。 The frequency multiplying device 130 is connected to the frequency dividing device 120, and multiplies the frequency dividing signal by a frequency multiplication operation to generate a second output signal having a frequency of 24 GHz ISM application frequency band (for example, 20 GHz to 28 GHz). The frequency of the second output signal is preferably 24 GHz. The frequency multiplying device 130 is an injection-locked oscillator.
該切換器140連接至該鎖相迴路110及該倍頻裝置140,以選擇該第一輸出訊號或該第二輸出訊號,作為輸出訊號。 The switch 140 is connected to the phase locked loop 110 and the frequency multiplying device 140 to select the first output signal or the second output signal as an output signal.
該鎖相迴路110包含一檢測器210、一電荷泵220、一鎖相迴路濾波器230、一可控式振盪器240、及一可程式除頻裝置250。 The phase locked loop 110 includes a detector 210, a charge pump 220, a phase locked loop filter 230, a controllable oscillator 240, and a programmable frequency dividing device 250.
該檢測器210係依據該參考訊號源與一反饋訊號之邏輯訊號頻率或相位的差異,進而產生一檢測訊號。 The detector 210 generates a detection signal according to the difference between the frequency or phase of the logic signal of the reference signal source and a feedback signal.
該電荷泵220耦合於該檢測器210,以依據該檢測訊號而產生一控制訊號。 The charge pump 220 is coupled to the detector 210 to generate a control signal according to the detection signal.
該鎖相迴路濾波器230耦合於該電荷泵220,以依據該控制訊號而產生一調整訊號。其中,該鎖相迴路濾波器230係為一低通濾波器。 The phase locked loop filter 230 is coupled to the charge pump 220 to generate an adjustment signal according to the control signal. The phase locked loop filter 230 is a low pass filter.
該可控式振盪器240耦合於該鎖相迴路濾波器230,以依據該調整訊號,進而產生該第一輸出訊號。其中,該第一輸出訊號係為差動輸出訊號。 The controllable oscillator 240 is coupled to the phase-locked loop filter 230 to generate the first output signal according to the adjustment signal. The first output signal is a differential output signal.
該可程式除頻裝置250耦合於該除頻裝置120,以依據該除頻訊號而產生該反饋訊號。 The programmable frequency dividing device 250 is coupled to the frequency dividing device 120 to generate the feedback signal according to the frequency dividing signal.
圖3係本發明該除頻裝置120之示意圖。由圖3可知,其係對該第一輸出訊號(V+,V-)的頻率進行除5之除頻操作,以產生該除頻訊號(Vo+,Vo-)。其係先對該第一輸出訊號(V+,V-)與一頻率為4f0的訊號進行乘法,以分別產生頻率為f0及9f0的訊號(f0=5f0-4f0,9f0=5f0+4f0)。再經由帶通濾波器BPF@f0濾除頻率為9f0的訊號,即可產生頻率為f0之該除頻訊號(Vout+,Vout-)。頻率為f0及9f0的訊號經由非線性放大器及帶通濾波器BPF@2f0,即可產生該頻率為4f0的訊號。 3 is a schematic diagram of the frequency dividing device 120 of the present invention. As can be seen from FIG. 3, the frequency division of the first output signal (V+, V-) is divided by 5 to generate the frequency-divided signal (Vo+, Vo-). The first output signal (V+, V-) is multiplied with a signal with a frequency of 4f 0 to generate signals with frequencies f 0 and 9f 0 respectively (f 0 = 5f 0 - 4f 0 , 9f 0 =5f 0 +4f 0 ). Then, by filtering the signal with the frequency of 9f 0 through the bandpass filter BPF@f 0 , the frequency-divided signal (Vout+, Vout-) having the frequency f 0 can be generated. The signals with frequencies f 0 and 9f 0 pass through the non-linear amplifier and the bandpass filter BPF@2f 0 to generate the signal with the frequency 4f 0 .
圖4係本發明該除頻裝置120之電路圖。該除頻裝置120包含含一電感L2、一電感L3、一電容C1、及可調整電容Cvar3,Cvar4、及電晶體M5~M8。該電晶體M5~M8係較佳為NMOS電晶體。 4 is a circuit diagram of the frequency dividing device 120 of the present invention. The frequency dividing device 120 includes an inductor L2, an inductor L3, a capacitor C1, and an adjustable capacitor Cvar3, Cvar4, and transistors M5~M8. The transistors M5 to M8 are preferably NMOS transistors.
該NMOS電晶體M5的源極及該NMOS電晶體M6的源極連接至該地電位,該NMOS電晶體M5的閘極連接至該NMOS電晶體M6的汲極、一輸出端Out4、該可調整電容Cvar4的一端、該NMOS電晶體M8的汲極、及該電感L2的一端。該NMOS電晶體M5的汲極連接至該NMOS電晶體M6的閘極、一輸出端Out3、該可調整電容Cvar3的一端、該NMOS電晶體M7的汲極、及該電感L2的另一端。該電感L2的中間連接至該高電位,該可調整電容Cvar3的另一端連接至該可調整電容Cvar4的另一端,該NMOS電晶體M7的源極連接至該NMOS電晶體M8的源極、及該電容C1的一端,該NMOS電晶體M7與該NMOS電晶體M8的閘極連接至該第一輸出訊號(V+,V-),該電容C1的另一端連接至該電感L3,該電感L3的另一端連接至該低電位。 The source of the NMOS transistor M5 and the source of the NMOS transistor M6 are connected to the ground potential, the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6, an output terminal Out4, and the adjustable One end of the capacitor Cvar4, the drain of the NMOS transistor M8, and one end of the inductor L2. The drain of the NMOS transistor M5 is connected to the gate of the NMOS transistor M6, an output terminal Out3, one end of the adjustable capacitor Cvar3, the drain of the NMOS transistor M7, and the other end of the inductor L2. The middle of the inductor L2 is connected to the high potential, the other end of the adjustable capacitor Cvar3 is connected to the other end of the adjustable capacitor Cvar4, the source of the NMOS transistor M7 is connected to the source of the NMOS transistor M8, and One end of the capacitor C1, the NMOS transistor M7 and the gate of the NMOS transistor M8 are connected to the first output signal (V+, V-), and the other end of the capacitor C1 is connected to the inductor L3, the inductor L3 The other end is connected to the low potential.
圖3中的帶通濾波器BPF@f0由電感L2、可調整電容Cvar3,Cvar4所組成,帶通濾波器BPF@2f0由電感L3和電容C1所組成。圖4中NMOS電晶體M7,M8的非線性部分則模擬成圖3中的非線性放大器Amp。由圖3的示意圖,即可瞭解圖4電路的運作。 FIG 3 the band pass filter BPF @ f 0 by the inductor L2, the adjustable capacitor Cvar3, Cvar4 composed of band-pass filter BPF @ 2f 0 of the inductor L3 and the capacitor C1 is composed. The non-linear portion of the NMOS transistors M7, M8 of Figure 4 is then modeled as the non-linear amplifier Amp of Figure 3. The operation of the circuit of Figure 4 can be seen from the schematic diagram of Figure 3.
該倍頻裝置130係一注入鎖定振盪裝置(injection-locked oscillator)。圖5係本發明該倍頻裝置130之電路圖。該注入鎖定振盪裝置(injection-locked oscillator)130包含一電感L1、可調整電容Cvar1,Cvar2、電晶體M1~M4,及一第一濾波器Filter1。其中,該電晶體M1~M4係較佳為NMOS電晶體。 The frequency multiplying device 130 is an injection-locked oscillator. Figure 5 is a circuit diagram of the frequency multiplying device 130 of the present invention. The injection-locked oscillator 130 includes an inductor L1, an adjustable capacitor Cvar1, Cvar2, transistors M1 to M4, and a first filter Filter1. The transistors M1 to M4 are preferably NMOS transistors.
如圖5所示,該第一電感L1的一第一端連接至一輸出端Vout+,其另一端連接至一輸出端Vout-,該電感L1的中間連接至一高電位Vdd,該可調整電容Cvar1的一第一端連接至該輸出端Vout+,其另一端連接至該可調整電容Cvar2的一第一端,該可調整電容Cvar2的另一端連接至該輸出端Vout-,該NMOS電晶體M1的汲極連接至該輸出端Vout+及該NMOS電晶體M2的閘極,該NMOS電晶體M1的閘極連接至該輸出端Vout-及該NMOS電晶體M2的汲極,該NMOS電晶體M1的源極連接至該NMOS電晶體M2的源極、該NMOS電晶體M3的汲極、該NMOS電晶體M4的汲極、及該第一濾波器Filter1,該NMOS電晶體M3的源極及該NMOS電晶體M4的源極連接至一低電位gnd,該NMOS電晶體M3的閘極及該NMOS電晶體M4的閘極連接至該除頻訊號(Vo+,Vo-)。其中,該第一濾波器Filter1係抑制該24GHz並提昇48GHz。 As shown in FIG. 5, a first end of the first inductor L1 is connected to an output terminal Vout+, and the other end is connected to an output terminal Vout-, and the middle of the inductor L1 is connected to a high potential Vdd, the adjustable capacitor A first end of the Cvar1 is connected to the output terminal Vout+, and the other end is connected to a first end of the adjustable capacitor Cvar2, and the other end of the adjustable capacitor Cvar2 is connected to the output terminal Vout-, the NMOS transistor M1 The drain is connected to the output terminal Vout+ and the gate of the NMOS transistor M2, and the gate of the NMOS transistor M1 is connected to the output terminal Vout- and the drain of the NMOS transistor M2, the NMOS transistor M1 The source is connected to the source of the NMOS transistor M2, the drain of the NMOS transistor M3, the drain of the NMOS transistor M4, and the first filter Filter1, the source of the NMOS transistor M3, and the NMOS. The source of the transistor M4 is connected to a low potential gnd, and the gate of the NMOS transistor M3 and the gate of the NMOS transistor M4 are connected to the demultiplexed signal (Vo+, Vo-). The first filter Filter1 suppresses the 24 GHz and increases the 48 GHz.
上述除頻裝置120及倍頻裝置130中係使用NMOS電晶體,熟於類比電路設計者可輕易轉換為使用PMOS電晶體。同時,不論使用NMOS電晶體或PMOS電晶體,在設計時只要依據晶圓廠所提供的半導體製程設計套件(Process Design Kit,PDK),亦可使用半導體製程所製作之N-type或P-type電晶體。 The OFDM transistor is used in the frequency dividing device 120 and the frequency doubling device 130, and the analog circuit designer can easily convert to use a PMOS transistor. At the same time, whether using an NMOS transistor or a PMOS transistor, the N-type or P-type made by the semiconductor process can be used according to the semiconductor process design kit (PDK) provided by the fab. Transistor.
圖6係本發明一種60GHz及24GHz雙頻訊號源產生方法之流程圖,其係用於產生一60GHz訊號及一24GHz訊號,請同時參照前述本發明之60GHz及24GHz雙頻訊號源產生系統100,首先,於步驟(A)中提供一參考訊號源Vref;再於步驟(B) 中使用一鎖相迴路依據該參考訊號源,以產生一頻率為50GHz至70GHz之第一輸出訊號。 6 is a flow chart of a method for generating a 60 GHz and 24 GHz dual-frequency signal source according to the present invention, which is used to generate a 60 GHz signal and a 24 GHz signal. Please refer to the 60 GHz and 24 GHz dual-frequency signal source generation system 100 of the present invention. First, a reference signal source Vref is provided in step (A); and in step (B) A phase-locked loop is used according to the reference signal source to generate a first output signal having a frequency of 50 GHz to 70 GHz.
於步驟(C)中使用一除頻裝置,對該第一輸出訊號的頻率進行除5之除頻操作,以產生一除頻訊號。 In step (C), a frequency dividing device is used, and the frequency of the first output signal is divided by 5 to generate a frequency dividing signal.
於步驟(D)中使用一倍頻裝置,對該除頻訊號進行乘2之倍頻操作,以產生一頻率為20GHz至28GHz之第二輸出訊號。 In step (D), a frequency doubling device is used to multiply the frequency division signal by a frequency multiplication operation to generate a second output signal having a frequency of 20 GHz to 28 GHz.
由前述說明可知,本發明電路架構的創新精神在掌握60GHz頻率與24GHz頻率存在的關係,提出一個60GHz和24GHz雙頻共存的鎖相迴路架構,以因應未來在毫米波ISM頻段60-GHz和24-GHz雙頻收發機系統所需之局部振盪訊號源(LO)產生器的設計。 It can be seen from the foregoing description that the innovative spirit of the circuit architecture of the present invention grasps the relationship between the 60 GHz frequency and the 24 GHz frequency, and proposes a 60 GHz and 24 GHz dual-frequency co-existing phase-locked loop architecture to cope with the future in the millimeter wave ISM band 60-GHz and 24 The design of a local oscillator signal source (LO) generator required for a -GHz dual-band transceiver system.
本發明與習知的設計理念不同,本發明的雙頻局部振盪源(LO)電路非由兩個鎖相迴路所完成,亦不利用習知倍頻器的概念而產生24GHz的輸出頻率。習知技術利用兩個鎖相迴路將浪費晶片面積及功率消耗,而利用習知倍頻器電路將劣化相位雜訊。 The present invention differs from the conventional design concept in that the dual-frequency local oscillator source (LO) circuit of the present invention is not implemented by two phase-locked loops, nor does it utilize the concept of a conventional frequency multiplier to produce an output frequency of 24 GHz. Conventional techniques utilize two phase-locked loops that waste wafer area and power consumption, while conventional frequency multiplier circuits can degrade phase noise.
本發明的優點在於藉由單一鎖相迴路設計的概念,整合一個可以同時產生60GHz和24GHz的訊號源產生器電路,以節省電路製作成本(包括使用元件個數或電路大小)。本發明的電路架構並適用在積體電路的製作上,具有較小的功率和面積損耗。此外,本發明的電路架構有其創新的設計概念,亦即,在高除數除頻電路的開發優勢及 結合注入鎖定振盪器電路所衍生出來的一個共存電路架構。 The invention has the advantage of integrating a signal source generator circuit capable of simultaneously generating 60 GHz and 24 GHz by a single phase-locked loop design concept to save circuit manufacturing costs (including the number of components or circuit size). The circuit architecture of the present invention is applicable to the fabrication of integrated circuits with less power and area losses. In addition, the circuit architecture of the present invention has its innovative design concept, that is, the development advantages of the high divisor frequency dividing circuit and A coexistence circuit architecture derived from an injection-locked oscillator circuit.
由上述可知,本發明無論就目的、手段及功效,在在均顯示其迴異於習知技術之特徵,極具實用價值。惟應注意的是,上述諸多實施例僅係為了便於說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。 From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are distinguished from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.
100‧‧‧60GHz及24GHz雙頻訊號源產生器系統 100‧‧‧60GHz and 24GHz dual-frequency signal source generator system
110‧‧‧鎖相迴路 110‧‧‧ phase-locked loop
120‧‧‧除頻裝置 120‧‧‧Dividing device
130‧‧‧倍頻裝置 130‧‧‧Multiplier
140‧‧‧切換器 140‧‧‧Switcher
210‧‧‧檢測器 210‧‧‧Detector
220‧‧‧電荷泵 220‧‧‧Charge pump
230‧‧‧鎖相迴路濾波器 230‧‧‧ phase-locked loop filter
240‧‧‧可控式振盪器 240‧‧‧Controllable Oscillator
250‧‧‧可程式除頻裝置 250‧‧‧Programmable frequency divider
步驟(A)~步驟(D) Step (A) ~ Step (D)
圖1係本發明之60GHz及24GHz雙頻訊號源產生器系統之一實施例的示意圖。 1 is a schematic diagram of one embodiment of a 60 GHz and 24 GHz dual frequency source generator system of the present invention.
圖2係本發明之60GHz及24GHz雙頻訊號源產生器系統之一實施例的方塊圖。 2 is a block diagram of one embodiment of a 60 GHz and 24 GHz dual frequency source generator system of the present invention.
圖3係本發明該除頻裝置之示意圖。 3 is a schematic diagram of the frequency dividing device of the present invention.
圖4係本發明該除頻裝置之電路圖。 4 is a circuit diagram of the frequency dividing device of the present invention.
圖5係本發明該倍頻裝置之電路圖。 Figure 5 is a circuit diagram of the frequency multiplying device of the present invention.
圖6係本發明一種60GHz及24GHz雙頻訊號源產生方法之流程圖。 6 is a flow chart of a method for generating a 60 GHz and 24 GHz dual-frequency signal source according to the present invention.
100‧‧‧60GHz及24GHz雙頻訊號源產生器系統 100‧‧‧60GHz and 24GHz dual-frequency signal source generator system
110‧‧‧鎖相迴路 110‧‧‧ phase-locked loop
120‧‧‧除頻裝置 120‧‧‧Dividing device
130‧‧‧倍頻裝置 130‧‧‧Multiplier
140‧‧‧切換器 140‧‧‧Switcher
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Citations (4)
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US6249192B1 (en) * | 1998-01-26 | 2001-06-19 | Agere Systems Guardian Corp. | Clock injection system |
US6417740B1 (en) * | 2001-02-22 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Wide-band/multi-band voltage controlled oscillator |
TW200943731A (en) * | 2008-04-03 | 2009-10-16 | Univ Nat Taiwan Science Tech | Injection-locked frequency divider |
US20120274367A1 (en) * | 2009-08-24 | 2012-11-01 | Kiat Seng Yeo | Front-End Transceiver |
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Publication number | Priority date | Publication date | Assignee | Title |
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US6249192B1 (en) * | 1998-01-26 | 2001-06-19 | Agere Systems Guardian Corp. | Clock injection system |
US6417740B1 (en) * | 2001-02-22 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Wide-band/multi-band voltage controlled oscillator |
TW200943731A (en) * | 2008-04-03 | 2009-10-16 | Univ Nat Taiwan Science Tech | Injection-locked frequency divider |
US20120274367A1 (en) * | 2009-08-24 | 2012-11-01 | Kiat Seng Yeo | Front-End Transceiver |
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