TWI503842B - Resistive memory apparatus and memory cell thereof - Google Patents

Description

Resistive memory device and its memory cell

The invention relates to a resistive memory and a memory cell thereof.

As the demand for information increases, it is an important trend to allocate large-capacity memory in electronic devices. In the current technical field, resistive memory has become a new favorite in the need to provide a long-lasting memory space with sufficient capacity.

The use of resistive memory as a non-volatile memory is a popular trend. The main reason is that the relatively high writing speed of the resistive memory, the relatively low operating power consumption, and the fabrication of the resistive memory are completely compatible with the manufacturing technology of today's integrated circuits.

However, in the current technical field, the resistive memory cell has a problem that the impedance value cannot be kept stable between the set and the reset. The main reason is that the control of the resistance value when the resistive memory cell is reset is relatively unstable. This phenomenon may cause errors in the reading of resistive memory cells, which affects the reliability of resistive memory.

The invention provides a resistive memory and a memory cell thereof, which can effectively improve the sensing margin and improve the reliability thereof.

The resistive memory cell of the present invention includes a first transistor, a second transistor, a first resistor, and a second resistor. The first transistor has a first end, a second end, and a control end. The first end and the second end of the first transistor are respectively coupled to the first bit line and the reference voltage, and the control end of the first transistor receives the word line signal. The second transistor has a first end, a second end, and a control end. The first end and the second end of the second transistor are respectively coupled to the second bit line and the reference voltage, and the control end of the second transistor receives the word. Meta-line signal. The first resistor is connected in series between the first end of the first transistor and the coupling path of the first bit line or in series between the second end of the first transistor and the coupling path of the reference voltage. The second resistor is connected in series between the coupling path of the first end and the second bit line of the second transistor or in series between the second end of the second transistor and the coupling path of the reference voltage.

The invention further provides a resistive memory device comprising a plurality of resistive memory cells, a plurality of bit line pairs, and a plurality of source lines. The resistive memory cells are arranged in a memory cell array, and the memory cell array has a plurality of memory cell rows and a plurality of memory cell columns. The word lines are respectively coupled to the memory cell columns and respectively transmit a plurality of word line signals. The bit line pairs are respectively coupled to the memory cell row. The source lines are respectively coupled to the resistive memory cells. Further, the resistive memory cell includes a first transistor, a second transistor, a first resistor, and a second resistor. The first transistor has a first end, a second end, and a control end. The first end and the second end of the first transistor are respectively coupled to the first bit line and the reference voltage, and the control end of the first transistor receives the word line signal. The second transistor has a first end, a The second end and the second end of the second transistor are respectively coupled to the second bit line and the reference voltage, and the control end of the second transistor receives the word line signal. The first resistor is connected in series between the first end of the first transistor and the coupling path of the first bit line or in series between the second end of the first transistor and the coupling path of the reference voltage. The second resistor is connected in series between the coupling path of the first end and the second bit line of the second transistor or in series between the second end of the second transistor and the coupling path of the reference voltage.

Based on the above, the present invention determines the stored data in the resistive memory cell through the impedance states of the first resistor and the second resistor respectively transmitted by the first bit line and the second bit line in the resistive memory cell. In this way, by the combination of the first resistor and the second resistor being set or reset, the stored data in the resistive memory cell can be more accurately known. Moreover, when the impedance value of the reset resistor cannot be effectively reset to the ideal value, the sensing boundary of the resistive memory cell can be controlled by changing the impedance value of the set resistor to maintain its performance.

The above described features and advantages of the invention will be apparent from the following description.

100,211~242‧‧‧Resistive memory cells

200, 300, 400‧‧‧Resistive memory device

M1, M2‧‧‧ transistor

R0_L, R0_R, R1, R2‧‧‧ resistance

VG_Sel1, VG_Sel2‧‧‧ character line signal

VS‧‧‧reference voltage

WL0~WL3‧‧‧ character line

SL0~SL1, SL0_U, SL0_D‧‧‧ source line

BL_L, BL_R, BL0_L~BL1_L, BL0_R~BL1_R, BL1_U~BL3_U, BL1_D~BL3_D‧‧‧ bit line

311_1, 311_2, 321_1, 321_2‧‧‧partial resistive memory cells

WL0_U~WL1_U, WL0_D~WL1_D‧‧‧ sub-word line

410‧‧‧ memory cell array

420‧‧‧Differential Amplifier

431, 432‧‧‧ preamplifier

SW1~SW4‧‧‧ switch

SEL1~SEL4‧‧‧Selection signal

ST‧‧‧ Sense end

RT‧‧‧ reference end

REF‧‧‧ reference signal line

FIG. 1A is a schematic diagram of a resistive memory cell according to an embodiment of the invention.

FIG. 1B is a schematic diagram of a resistive memory cell in accordance with an embodiment of the present invention.

2A is a schematic diagram of a resistive memory device in accordance with an embodiment of the present invention.

2B is a schematic diagram of a resistive memory device of another embodiment of the embodiment of FIG. 2A.

2C is a schematic diagram of a resistive memory device according to still another embodiment of the embodiment of FIG. 2A.

FIG. 3A is a schematic diagram of a resistive memory device according to another embodiment of the present invention.

FIG. 3B is a schematic diagram of another embodiment of the resistive memory device of the embodiment of FIG. 3A of the present invention. FIG.

4 is a schematic diagram of a resistive memory device according to still another embodiment of the present invention.

Please refer to FIG. 1A. FIG. 1A is a schematic diagram of a resistive memory cell according to an embodiment of the present invention. The resistive memory cell 110 includes transistors M1, M2 and resistors R0_L and R0_R. The transistor M1 has a first end, a second end, and a control end, and the transistor M1 may be a gold-oxygen semiconductor field effect transistor (MOSFET). The second end of the transistor M1 (eg, its source) is coupled to the reference voltage VS, and the control terminal (eg, its gate) of the transistor M1 receives the word line signal VG_Sel1, the first end of the transistor M1 (eg, The pole is coupled to the resistor R0_L, and the reference voltage VS may be a source voltage. The transistor M2 has a first end, a second end, and a control end, and the transistor M2 may also be a gold-oxygen semiconductor field effect transistor (MOSFET). The second end of the transistor M2 (eg, its source) is coupled to the reference voltage VS, and the control terminal (eg, its gate) of the transistor M2 receives the word line signal VG_Sel2, the first end of the transistor M2 (eg, The pole is coupled to the resistor R0_R.

In the above embodiments, the transistors M1 and M2 may be N-type or P-type MOS field-effect transistors. Of course, in other embodiments of the present invention, the transistors M1 and M2 may also be any type of Bipolar Junction Transistor (BJT).

Please note that the word line signals VG_Sel1 and VG_Sel2 received by the control terminals of the transistors M1 and M2, respectively, may be the same signal transmitted from the same word line, or may be in a word line. The two sub-word lines transmit different signals.

The first end of the resistor R0_L is coupled to the first end of the transistor M1, and the second end of the resistor R0_L is coupled to the bit line BL0_L. In addition, the first end of the resistor R0_R is coupled to the first end of the transistor M2, and the second end of the resistor R0_R is coupled to the bit line BL0_R.

It should be noted that the resistive memory cell 110 of the present embodiment can provide a single bit of stored data or can also provide two bits of read data. For example, the resistive memory cell 110 provides a single bit of stored data. The user can obtain the impedance states provided by the resistors R0_L and R0_R through the bit line BL0_L and the bit line BL0_R. The stored data stored in the resistive memory cell 110 is known through the impedance state. For example, when the impedance provided by the resistor R0_L is high impedance and the impedance provided by the resistor R0_R is low impedance (below the impedance value provided by the resistor R0_L), the stored storage of the resistive memory cell 110 can be interpreted. The data is bit "0" (or bit "1"), and when the impedance provided by resistor R0_L is low impedance and the impedance provided by resistor R0_R is high impedance, then the power is read. The stored data stored by the resistive memory cell 110 is bit "0" (or bit "1").

Certainly, the embodiment of the present invention may also determine that the stored data stored in the resistive memory cell 110 is a bit “0” when the impedances provided by the resistors R0_L and R0_R are both high impedances (eg, greater than the first critical resistance value). (or bit "1"), and when the impedances provided by the resistors R0_L and R0_R are both low impedance (for example, less than the second critical resistance value), the stored data stored in the resistive memory cell 110 is interpreted as a bit. Yuan "0" (or bit "1"). The first and second threshold resistance values for determining that the impedances provided by the resistors R0_L and R0_R are both high impedance or low impedance may be the same or different. The first and second critical resistance values are predetermined values, and the first critical resistance value is greater than the second critical resistance value.

The above-mentioned high and low impedance determination operations provided by the resistors R0_L and R0_R can turn on the transistors M1 and M2 by the word lines VG_Sel0 and VG_Sel1, and pass the currents read by the bit line BL0_L and the bit line BL0_R (or The magnitude of the voltage) is compared to a predetermined threshold to determine. The preset threshold value can be adjusted according to the change of the process parameters of the resistive memory cell 110. As a result, the instability of the stored data reading of the resistive memory cell 110 can be effectively avoided.

It is to be noted that the resistive memory cell 110 of the embodiment of the present invention compares the impedance states provided by the resistors R0_L and R0_R with each other to obtain the stored data of the resistive memory cell 110. That is to say, the resistive memory cell 110 of the embodiment of the present invention does not need to set a reference memory cell for providing a reference value as a basis for impedance value comparison. In this way, the resistive memory cell using the embodiment of the present invention is utilized. The memory constructed by 110 can save the area required for the reference memory cell, and the power consumption required by the reference memory cell, effectively reduce the price and save power consumption, and effectively improve the data reading speed of the resistive memory cell 110.

On the other hand, the transistor M1, the resistor R0_L, and the transistor M2, and the resistor R0_R in the resistive memory cell 110 can be separated to store two bits of stored data. Specifically, the combination of the transistor M1 and the resistor R0_L can be used to store the stored data of one bit, and the combination of the transistor M2 and the resistor R0_R can be used to store the stored data of another bit. When the resistive memory cell 110 is to be read, the transistors M1 and M2 can be turned on by the word lines VG_Sel0 and VG_Sel1, respectively, and respectively interpreted according to the currents on the bit line BL0_L and the bit line BL0_R. The impedance values of the resistors R0_L and R0_R are respectively determined according to whether the impedance values of the resistors R0_L and R0_R are greater than a predetermined threshold value, or are less than another preset threshold value to read the stored data stored in the single resistive memory cell 110. Two bits.

Incidentally, in the portion for writing data to the resistive memory cell 110, the character signal can be transmitted through the word lines VG_Sel0 and VG_Sel1 to select the resistive memory cell 110, and the resistive memory cell 110 is In the selected state, the stored data is written by setting or resetting the resistance values of the resistors R0_L and R0_R, respectively. Of course, the impedance states of the resistors R0_L and R0_R can be determined according to the stored data to be written.

It is worth noting that when the resistance value provided by the resistor of the resistive memory cell 110 in the reset state is unstable, the power in the set state can be changed. The resistance value provided by the resistor is used to maintain the difference between the impedance values of the reset and the set resistor, and then the resistors R0_L and R0_R are reset and/or set in the resistive memory cell 110. Comparing the resistance values can effectively prevent the possibility of error in the judgment of the stored data reading.

Please refer to FIG. 1B. FIG. 1B is a schematic diagram of a resistive memory cell according to an embodiment of the present invention. The resistive memory cell 120 of FIG. 1B is different from the resistive memory cell 110 of FIG. 1A in that the resistor R0_L is coupled between the coupling path of the transistor M1 and the reference voltage VS, and the resistor R0_R is coupled. Between the coupling path of the transistor M2 and the reference voltage VS.

2A, FIG. 2A is a schematic diagram of a resistive memory device according to an embodiment of the invention. The resistive memory device 210 includes resistive memory cells 211 to 242, word lines WL0 to WL3, and source lines SL0 to SL1. The resistive memory cells 211 to 242 are arranged in an array to form a memory cell array. The 4×2 memory cell array illustrated in FIG. 2A is merely an example and is not intended to limit the invention.

The memory cell array of Figure 2A has a plurality of memory cell rows and memory cell columns. Wherein, the same word line is coupled to the same memory cell column. Specifically, the word line WL0 is coupled to the resistive memory cells 211 and 212 of the first memory cell column, and the word line WL1 is coupled to the resistive memory cells 221 and 222 of the second memory cell column. The line WL2 is coupled to the resistive memory cells 231 and 232 of the third memory cell, and the word line WL3 is coupled to the resistive memory cells 241 and 242 of the fourth memory cell.

In addition, in this embodiment, the same memory cell row of resistive memory cell coupling Connect to the same source line. In FIG. 2A, the memory cell formed by the resistive memory cells 211 and 212 is coupled to the source line SL0 and the resistive memory cells 231 and 232. The memory cell row and the memory cell formed by the resistive memory cells 241 and 242 are coupled to the source line SL1.

The bit line BL0_L and the bit line BL0_R in FIG. 2A form one bit line pair, and the bit line BL1_L and the bit line BL1_R form another bit line pair. The bit line pair formed by the bit line BL0_L and the bit line BL0_R is coupled to the memory cell row formed by the resistive memory cells 211, 221, 231, and 241, and the bit formed by the bit line BL1_L and the bit line BL1_R The pair of meta-lines are coupled to the memory cell formed by the resistive memory cells 212, 222, 232, and 242.

When the memory cell in the resistive memory device 210 is read, the resistive memory cell 211 is taken as an example, and the crystals M1 and M2 are turned on through the word line WL0 to select the resistive memory cell 211, and the measurement is performed. The currents transmitted on the bit lines BL0_L and BL_R are used to know the impedance states of the resistors R1 and R2. According to the description of the foregoing embodiment, it can be known that the stored data of one or more bits in the resistive memory cell 211 can be obtained by judging the impedance states of the resistors R1 and R2.

In this embodiment, two transistors in a single resistive memory cell share the same word line. If two bytes of stored data are stored in a single resistive memory cell, the stored data of the two bits will be simultaneously read during the data reading operation. In contrast, when storing a bit of stored data in a single resistive memory cell, the current on the corresponding bit line pair can be sensed at the same time, and the power is obtained. Storage data in resistive memory cells.

Please refer to FIG. 2B. FIG. 2B is a schematic diagram of a resistive memory device according to another embodiment of the embodiment of FIG. 2A. 2B illustrates a memory device 220 that is different from the resistive memory device 210 in that each memory cell is coupled to an independent source line, specifically, a memory formed by the resistive memory cells 211-212. The cell row is coupled to the source line SL0, the memory cell formed by the resistive memory cells 221-222 is coupled to the source line SL1, and the memory cell formed by the resistive memory cells 231-232 is coupled to the source line. The memory cell formed by the SL2 and the resistive memory cells 241-242 is coupled to the source line SL3.

Referring to FIG. 2C, FIG. 2C is a schematic diagram of a resistive memory device according to still another embodiment of the embodiment of FIG. 2A. In FIG. 2C, the source lines SL0 to SL3 are arranged in a direction non-parallel to the word line. Among them, the transistors arranged at the relative positions of the same memory row are connected to the same source line. Specifically, the resistive memory cells 211, 221, 231, and 241 arranged in the same memory row are exemplified, wherein the transistor M1 of the resistive memory cell 211, the transistor M3 of the resistive memory cell 221, and the resistive memory The transistor M7 of the cell 241 is coupled to the source line SL0, and the transistor M2 of the resistive memory cell 211, the transistor M4 of the resistive memory cell 221, and the transistor M6 of the resistive memory cell 241 are coupled to the source. Line SL1. In the configuration mode of FIG. 2C, the resistive memory cell 211 is taken as an example, wherein the resistor R1 and the resistor R2 can be selected to simultaneously access data, or the resistor R1 and the resistor R2 can be selected. Access to data at the time.

Referring to FIG. 3A, FIG. 3A illustrates a resistor according to another embodiment of the present invention. Schematic diagram of a memory device. The resistive memory device 310 includes a plurality of resistive memory cells, and each resistive memory cell is split into two portions to be disposed at different positions. In FIG. 3A, a portion of the resistive memory cell 311_1 and a portion of the resistive memory cell 311_2 are combined into a resistive memory cell, and a portion of the resistive memory cell 321_1 and a portion of the resistive memory cell 321_2 are combined into another resistive memory cell.

The partial resistive memory cell 311_1 and the partial resistive memory cell 311_2 are respectively coupled to the sub-word line WL0_U and the sub-word line WL0_D. The transistor M1 in the partial resistive memory cell 311_1 is controlled to be turned on or off by the sub-word line WL0_U, and the transistor M2 in the partial resistive memory cell 311_2 is controlled to be turned on or off by the sub-word line WL0_D. open. Similarly, the partial resistive memory cell 321_1 and the partial resistive memory cell 321_2 are coupled to the sub-word line WL1_U and the sub-word line WL1_D, respectively. The transistor in the partial resistive memory cell 321_1 is controlled to be turned on or off by the sub-word line WL1_U, and the transistor in the partial resistive memory cell 321_2 is controlled to be turned on or off by the sub-word line WL1_D. The configuration of the word lines of the remaining resistive memory cells is similar to the configuration of the word lines of the resistive memory cells described above, and will not be described one by one.

Incidentally, in this embodiment, the adjacent partial resistive memory cells 311_1 and 321_1 are coupled to the source line SL0_U, and the adjacent partial resistive memory cells 311_2 and 321_2 are coupled to the source line SL0_D, and The adjacent partial resistive memory cells 311_1 and 321_1 share the bit line BL0_U, and the adjacent partial resistive memory cells 311_2 and 321_2 share the bit line BL0_D. The remaining bit lines BL1_U~BL3_U and the bit lines BL1_D~BL3_D are respectively coupled to the remaining parts. Resistive memory cell. Of course, in other embodiments of the present invention, the adjacent partial resistive memory cells are also respectively coupled to different source lines, and the configuration thereof is similar to the embodiment of FIG. 2B, and details are not described herein.

It can be found from the circuit architecture of FIG. 3A that two resistive memory cells of a single resistive memory cell are respectively controlled by different sub-word lines, and therefore, two bits stored in a single resistive memory cell are stored. Meta-stored data can be read separately. Moreover, when performing a data writing operation on the resistive memory cell, a resistive memory cell composed of the partially resistive memory cells 311_1 and 311_2 is taken as an example, and one of the partial resistive memory cells 311_1 and 321_1 can be simultaneously performed. Reset or set, and set or reset for the other of the partial resistive memory cells 311_1 and 321_1. Effectively speed up data writing.

Of course, the setting or resetting actions of the partial resistive memory cells 311_1 and 321_1 can also be performed in a time-sharing manner without any limitation.

Please refer to FIG. 3B. FIG. 3B is a schematic diagram of another embodiment of the resistive memory device of the embodiment of FIG. 3A of the present invention. The source line of the resistive memory device 320 of FIG. 3B may be arranged not parallel to the direction of the word line. The partially resistive memory cells disposed in the same memory row can be coupled to the same source line.

2A, 2B, 2C, 3A, and 3B, the arrangement of the source lines of the resistive memory device of the embodiment of the present invention is not limited to one mode, and those skilled in the art have a general knowledge. The arrangement of the source lines of the known memory can be applied to the present invention, and will not be described one by one.

Please refer to FIG. 4, which illustrates a resistive type according to still another embodiment of the present invention. A schematic diagram of a memory device. The resistive memory device 400 includes a memory cell array 410, a differential amplifier 420, preamplifiers 431, 432, and switches SW1 SWSW4. The differential amplifier 420 is coupled to the bit lines BL_L and BL_R in the memory cell array 410 through the switches SW1 SW SW4. The switch SW1 is configured to select one of the bit lines BL_L and BL_R to be coupled to the sensing terminal ST on the differential amplifier 420 according to the selection signal SEL1 and the inverted signal SEL2 of the selection signal SEL1. The switches SW4 and SW3 respectively select the bit line BL_R or the preset reference signal line REF to be coupled to the reference terminal RT on the differential amplifier 420 according to the selection signal SEL4 and the inverted signal SEL3 of the selection signal SEL4, respectively. The preset reference signal line REF is used to transmit a preset reference signal.

In this embodiment, the selection signals SEL1 SEL SEL4 can be determined according to the number of data bits stored in a single resistive memory cell. When a single resistive memory cell stores a single data bit, the switches SW1 and SW4 can be turned on according to the selection signals SEL1 and SEL4, and the switches SW2 and SW3 can be turned off according to the selection signals SEL2 and SEL3. Thus, the differential amplifier 420 The currents on the bit lines BL_L and BL_R can be received for comparison, and the data bits stored by the resistive memory cells are known.

On the other hand, when a single resistive memory cell stores a plurality of data bits, the switch SW3 is turned on according to the selection signal SEL3, and the switch SW4 is turned off according to the selection signal SEL4. Moreover, the switches SW1 and SW2 can be sequentially turned on when the switch SW3 is turned on, so that the electrical characteristics on the bit line BL_L and the bit line BL_R are time-divisionally separated from the preset reference signal provided by the preset reference signal line REF. Compare and borrow to obtain two bit data bits.

Of course, the above-described turn-on sequence for the switches SW1 and SW2 can be changed, or when only one of the two bits of the stored data needs to be read, only one of the switches SW1 and SW2 needs to be turned on.

In summary, the present invention provides a resistive memory cell composed of two transistors and two resistors. In this way, the impedance values provided by the two resistors can be compared, and the stored data in the resistive memory cells can be read through the comparison result, thereby avoiding the possibility of reading errors in the stored data.

110‧‧‧Resistive memory cells

M1, M2‧‧‧ transistor

R0_L, R0_R‧‧‧ resistance

BL0_L, BL0_R‧‧‧ bit line

VG_Sel1, VG_Sel2‧‧‧ character line signal

VS‧‧‧reference voltage

Claims (9)

A resistive memory cell includes: a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor are respectively coupled to a first bit line and a reference voltage, the control end of the first transistor receives a word line signal; a second transistor has a first end, a second end, and a control end, the first end and the second end of the second transistor The first transistor is coupled to the second bit line and the reference voltage, and the control terminal of the second transistor receives the word line signal; a first resistor is serially connected to the first end of the first transistor and the first a coupling path of one of the wires is connected in series between the second end of the first transistor and the coupling path of the reference voltage; and a second resistor is serially connected to the first end of the second transistor And the coupling path of the second bit line is connected between the second end of the second transistor and the coupling path of the reference voltage, wherein the resistance of the first resistor is higher than the resistance of the second resistor When the resistance is changed, the first stored data stored by the resistive memory cell is a first logic level, and the resistance of the first resistor is When the resistance of the second resistor is lower than the resistance of the second resistor, the first storage data is a second logic level; or the resistance of the first resistor and the second resistor is greater than a first threshold resistance value, the first storage The data is a first logic level. When the resistances of the first resistor and the second resistor are both less than a second threshold resistance, the first stored data is a second logic level. The resistive memory cell of claim 1, wherein when the resistive memory cell is selected for reading, the first and second transistors are turned on according to the word line signal. The first bit line and the second bit line respectively transmit impedance states of the first resistor and the second resistor. The resistive memory cell of claim 2, wherein the impedance states of the first resistor and the second resistor respectively represent a plurality of second stored data stored by the resistive memory cell. A resistive memory device comprising: a plurality of resistive memory cells arranged in a memory cell array, the memory cell array having a plurality of memory cell rows and a plurality of memory cell columns; a plurality of word word lines respectively coupled to the memory cells The memory cells are respectively arranged to transmit a plurality of word line signals; the plurality of bit line pairs are respectively coupled to the memory cell lines; and the plurality of source lines are respectively coupled to the resistive memories Each of the resistive memory cells includes: a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor are respectively coupled to a first a bit line and a corresponding source line, the control end of the first transistor receives a word line signal; a second transistor has a first end, a second end, and a control end, the second transistor The first end and the second end are respectively coupled to a second bit line and a corresponding source line, and the control end of the second transistor receives the word line signal; a first resistor is serially connected to the first line The first end of the crystal and the first bit a coupling path between the first line of the first transistor and a corresponding path of the corresponding source line; and a second resistor connected in series with the first of the second transistor And a coupling path between the end and the second bit line or between the coupling paths of the second end of the second transistor and its corresponding source line; and a differential amplifier coupled to the bits a pair of potential amplifiers, the differential amplifier receiving a plurality of selection signals, wherein the differential amplifier performs signals for the first bit line and the second bit line of each of the bit line pairs according to the selection signals Comparing to obtain a first stored data, or the differential amplifier compares the signals on the first bit line and the second bit line with a predetermined reference signal according to the selection signals, and To obtain a majority of the second stored data. The resistive memory device of claim 4, wherein each of the word lines comprises a first sub-word line and a second sub-word line, wherein the first of each resistive memory cell a control end of the transistor is coupled to the first sub-word line of the corresponding word line, and a control end of the second transistor is coupled to the second sub-word line of the corresponding word line, each of the source The pole line includes a first sub-source line and a second sub-source line, wherein the second end of the first transistor of each of the resistive memory cells is coupled to the first sub-source of the corresponding source line The second end of the second transistor is coupled to the second sub-source line of the corresponding source line. The resistive memory device of claim 4, wherein the first resistance of each of the resistive memory cells and the impedance state of the second resistor represent a stored data stored by each of the resistive memory cells. The resistive memory device of claim 6, wherein when the resistance of the first resistor is higher than the resistance of the second resistor, the stored data is a first logic level, and the first resistor When the resistance is lower than the resistance of the second resistor, the stored data is at a second logic level. The resistive memory device of claim 6, wherein when the resistances of the first resistor and the second resistor are greater than a critical resistance value, the stored data is a first logic level, the first When the resistance of the resistor and the second resistor are both less than the critical resistance value, the stored data is at a second logic level. The resistive memory device of claim 4, wherein the first resistance of each of the resistive memory cells and the impedance state of the second resistor respectively represent a plurality of stores stored in each of the resistive memory cells. data.