TWI502777B - Semiconductor element and manufacturing method thereof - Google Patents

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a light emitting semiconductor device and a method of fabricating the same.

With the advancement of optoelectronic technology, the manufacture and application of semiconductor components have gradually matured, such as light-emitting diodes (LEDs) or laser components, which can be fabricated from semiconductor components. Taking the light-emitting diode as an example, it has been widely used in various fields of light source or illumination, such as traffic signs and outdoor, due to its advantages of low pollution, low power consumption, short response time, and long service life. Kanban and display backlights, etc. Light-emitting diodes have become one of the most eye-catching optoelectronic industries.

At present, the method of mixing white light of a light-emitting diode is mainly to use a blue light-emitting diode or an ultraviolet light-emitting diode (UV LED) to excite yellow phosphor powder to mix white light. However, the conversion efficiency of the long-wavelength light of the phosphor powder is not good, so that the white light of the mixed white light is cooled, and the color rendering of the light-emitting diode is poor. In addition, the phosphor absorbs energy, causing a loss of energy from the light emitted by the light-emitting diode. Therefore, how to reduce the loss of light energy and improve the conversion efficiency of long-wavelength light to improve the color rendering is one of the issues that current researchers are trying to solve.

The present invention provides a method of fabricating a semiconductor device which can produce a semiconductor device having good color rendering properties.

The present invention provides a semiconductor element which has good color rendering properties.

The present invention provides a method of fabricating a semiconductor device, comprising the following steps. A substrate is provided, the substrate having a base and a plurality of columns on the base. A protective layer is formed on the side walls of each of the columnar bodies and on the base between the columns. A first type doped semiconductor material is grown on the top surface of the column to form a plurality of first type doped semiconductor structures. Each of the first type doped semiconductor structures has a bottom surface and a plurality of side wall surfaces connected to the bottom surface, and each of the side wall surfaces is inclined with respect to the bottom surface. A plurality of light emitting layers are formed on sidewalls of the first type doped semiconductor structure, wherein each of the light emitting layers includes a metal element, and the metal element has a content of three or more of the light emitting layers. A second type doped semiconductor layer is formed on the uppermost light emitting layer.

In an embodiment of the invention, the method for fabricating the semiconductor device further includes forming a conductive layer on the second type doped semiconductor layer.

In an embodiment of the invention, the method for fabricating the aforementioned substrate comprises the following steps. An undoped semiconductor layer is formed on the substrate. A first type of doped semiconductor material is grown on the undoped semiconductor layer to form a first type of doped semiconductor material layer. The first type doped semiconductor material layer is patterned to form a columnar body and a base, wherein the base includes a region other than the columnar body of the first type doped semiconductor material layer, the substrate, and the undoped semiconductor layer.

The present invention provides a semiconductor device produced by the above-described production method.

In an embodiment of the invention, the protective layer is made of cerium oxide.

In an embodiment of the invention, the side of the uppermost layer of the luminescent layer The wall is at an angle to the bottom surface of the first doped semiconductor structure, the angle being no greater than 65 degrees.

In an embodiment of the invention, the shape of the first type doped semiconductor layer is a plate shape or a pyramid shape.

In an embodiment of the invention, the aforementioned metal element is indium.

In an embodiment of the invention, the luminescent layer has a chemical formula of In _x Ga _1-x N and x is between 0 and 0.4.

In an embodiment of the invention, one of the first type and the second type is a P type, and the other of the first type and the second type is an N type.

In an embodiment of the invention, the conductive layer is a transparent conductive layer.

Based on the above, the present invention can illuminate the light emitted by the multi-layer luminescent layer by modulating the content of the metal element disposed in the multi-layer luminescent layer disposed on the first type doped semiconductor structure without arranging the luminescent layer. The wavelength can cover the wavelength range of visible light. As a result, the problem of the absorption energy of the phosphor powder and the problem of poor conversion efficiency of the long-wavelength light of the phosphor powder can be reduced, and a semiconductor element having high power and good color rendering properties can be produced.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a flow chart showing the fabrication of a semiconductor device in accordance with an embodiment of the invention. Referring to FIG. 1, a method for fabricating a semiconductor device of the present embodiment includes: providing a substrate (step S100), the substrate having a base and a plurality of bases Columns. A protective layer is formed on the side walls of each of the columnar bodies (step S200). Growing a first type doped semiconductor material on a top surface of the column to form a plurality of first type doped semiconductor structures (step S300), wherein each of the first type doped semiconductor structures has a bottom surface and a plurality of bottom surfaces Side wall surface. A plurality of light emitting layers are formed on sidewall faces of the first type doped semiconductor structure (step S400). A second type doped semiconductor layer is formed on the uppermost light emitting layer (step S500). In the present embodiment, the manufacturing method of the semiconductor element is, for example, sequentially performing steps S100 to S500.

Hereinafter, a method of fabricating a semiconductor device will be described in detail with reference to FIGS. 2A to 2E and FIGS. 3A to 3G.

2A to 2E are schematic cross-sectional views showing a manufacturing process of the substrate in the step S100. In the present embodiment, the columnar body of the substrate is, for example, a nanoimprint lithography, and the nanoimprint mold having the concave-convex pattern is transferred to the substrate by pressing, and further A plurality of columnar bodies are formed. Specifically, referring to FIG. 2A, first, an undoped semiconductor layer 20 is formed on a substrate 10. The substrate 10 may be a sapphire substrate (alumina, Al 2 O 3 ), a tantalum carbide (SiC) substrate, a germanium (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a gallium nitride (GaN) substrate, Lithium aluminate (LiAlO2) substrate, lithium gallium hydride (LiGaO2) substrate or other substrate suitable for epitaxy. In the present embodiment, the substrate 10 is exemplified by a (0001) plane (ie, c plane) sapphire substrate, and the material of the undoped semiconductor layer 20 is exemplified by gallium nitride, but the invention is not limited thereto. .

Next, a first type doped semiconductor material is grown on the undoped semiconductor layer 20 to form a first type doped semiconductor material layer 30. In the present embodiment, the first type doped semiconductor material is exemplified by N-type gallium nitride, but the invention is not limited thereto. In addition, the method of forming the undoped semiconductor layer 20 and the first type doped semiconductor material layer 30 is, for example, a Metal-Organic Chemical Vapor Deposition (MOCVD) method, but the invention is not limited thereto. . In other embodiments, the method of forming the undoped semiconductor layer 20 and the first type doped semiconductor material layer 30 may also be Molecular Beam Epitaxy (MBE), sputtering, and evaporation ( Evaporation, Pulse Laser Deposition (PLD), Vapor Phase Epitaxy (VPE) or Liquid Phase Epitaxy (LPE). In addition, the thicknesses H ₂₀ and H _{30 of the} undoped semiconductor layer 20 and the first type doped semiconductor material layer 30 are, for example, 3 micrometers (μm), but the invention is not limited thereto.

Next, a dielectric layer 40 and a generation transfer layer 50 are successively formed on the first type doped semiconductor material layer 30. In the present embodiment, the material of the dielectric layer 40 may be an inorganic material, wherein the inorganic material is, for example, tantalum oxide, tantalum nitride, hafnium oxynitride, hafnium aluminum oxide or a stacked layer of at least two of the above materials. The material of the transfer layer 50 may be a polymer. In addition, the thicknesses H ₄₀ and H _{50 of the} dielectric layer 40 and the generation transfer layer 50 are, for example, 0.4 μm and 0.2 μm, respectively, but the invention is not limited thereto.

Referring to FIG. 2B, a patterned mold (not shown) is placed on the generation transfer layer 50, and the patterned mold is in direct contact with the generation transfer layer 50. Patterning the mold, the substrate 10, and the film layer thereon (including undoped semiconductors) The bulk layer 20, the first type doped semiconductor material layer 30, the dielectric layer 40, and the generation transfer layer 50) are subjected to a temperature rising process. Next, the patterned mold is subjected to a high pressure to transfer the pattern on the patterned mold to the transfer layer 50, and a plurality of columnar patterns P1 are formed. Next, the patterned mold, the substrate 10, and the film layer thereon are cooled to room temperature, and the patterned mold is separated from the substrate 10.

In this embodiment, the pitch P ₅₀ between the adjacent two columnar patterns P1 and the diameter D _{50 of} each of the columnar patterns P1 are both about 0.35 μm, in other words, the ratio of the pitch P ₅₀ to the diameter D ₅₀ is 1:1. However, the invention is not limited thereto. In other embodiments, the ratio of the pitch P ₅₀ to the diameter D ₅₀ may depend on actual needs.

Referring to FIG. 2C, the dielectric layer 40 is patterned by using the columnar pattern P1 as a mask to form a plurality of columnar patterns P2 having substantially the same contour as the columnar pattern P1. In the present embodiment, the method of patterning the dielectric layer 40 is, for example, patterning the dielectric layer 40 by a reactive ion etching (RIE) step S1 of an oxygen plasma (O ₂ plasma). In other embodiments, the method of patterning the dielectric layer 40 may also be a reactive ion etching step using a trifluoromethane plasma.

Referring to FIG. 2D, the first type doped semiconductor material layer 30 is patterned by using the columnar pattern P1 as a mask to form a plurality of columnar bodies 30a and a base B as described in FIG. A region other than the columnar body 30a of the semiconductor material layer 30 (i.e., the bottom portion 30b), the substrate 10, and the undoped semiconductor layer 20 are doped. In this embodiment, the patterning process is, for example, inductively coupled plasma etching (ICP etching) step S2, patterning the first type doped semiconductor The material layer 30 forms a plurality of columnar bodies 30a and a bottom portion 30b connecting the columnar bodies 30a.

It is worth mentioning that when the first type doped semiconductor material layer 30 is patterned, part of the first type doped semiconductor material layer 30 is removed, and the plurality of columnar bodies 30a are lattice mismatched ( The defect density of the dislocation generated by the lattice mismatch is reduced as the removed area of the first type doped semiconductor material layer 30 is increased, and the luminous efficiency of the semiconductor element is thereby increased.

Referring to FIG. 2E, the columnar pattern P1 and the columnar pattern P2 on the columnar body 30a are removed to initially complete the fabrication of the substrate 100. In the present embodiment, the outline of the columnar body 30a in the substrate 100 is the same as the columnar pattern P1 and the columnar pattern P2. In other words, the diameter D _{30a of the} columnar body 30a and the pitch P _30a between the adjacent two columnar bodies 30a are the same as the diameter D ₅₀ and the pitch P _{50 of the} columnar pattern P1. Specifically, the diameter D _{30a of the} columnar body 30a and the pitch P _30a between the adjacent two columnar bodies 30a are both about 0.35 μm, and the height H _30a of the columnar body 30a is about 1 μm. In other embodiments, after the preliminary formation of the substrate 100, the diameter D _30a , the pitch P _{30a ,} and the height H _30a of each of the columnar bodies 30a may be selectively finely adjusted by a reactive ion etching step. In this way, the topography or size of the first type doped semiconductor structure formed on the columnar bodies 30a may be changed.

3A to 3G are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention. Referring to FIG. 3A, a substrate 310 having a base B and a plurality of columnar bodies 30a on the base B is provided. In the present embodiment, the substrate 310 is, for example, a substrate to which the foregoing embodiments are applied. 100. In other embodiments, the columnar body 30a of the substrate 310 may also be fabricated by other etching, laser processing, or other suitable methods.

Referring to Figure 3B, on a sidewall of each columnar body _30a S 30a, 30a and a region other than the pillar-shaped first-type doping layer of semiconductor material of the body 30 (i.e., the bottom 30b) formed on the protective layer 320. In the present embodiment, the material of the protective layer 320 is, for example, hafnium oxide, but the invention is not limited thereto. Further, the method of forming the protective layer 320 includes, for example, the following steps. First, the material of the protective layer 320 is formed on the substrate 310, and the method of forming may be a plasma chemical vapor deposition (PECVD) method or a spin on glass (SOG) method. . Next, a temperature rising process can be performed to create a void V1 between the adjacent two columnar bodies 30a. And then by a reactive ion etching step, removing the material located in the top surface of the protective layer 30a of each columnar body _30a of T 320 and expose the top surface 30a of each columnar body _30a of the T, the protective layer 320 covering The side wall S _30a of each of the columnar bodies 30a covers the bottom portion 30b between the columnar bodies 30a.

It should be noted that different process methods change the appearance of the protective layer 320. In the present embodiment, a void V1 exists between adjacent two columnar bodies 30a. However, in other embodiments, the protective layer 320 may also fill between the adjacent two columns 30a.

Referring to FIG. 3C, the first type doped semiconductor material is grown twice on the top surface T _30a of the columnar body 30a to form a plurality of first type doped semiconductor structures 330. In the present embodiment, the first type doped semiconductor material described herein is, for example, the same as the material of the first type doped semiconductor material layer 30 described above. In other words, the first type doped semiconductor material is, for example, N-type gallium nitride. In addition, the foregoing method of forming the plurality of first type doped semiconductor structures 330 is, for example, growing the first type doped semiconductor material by means of an organometallic chemical vapor deposition method in a selective area epitaxy manner.

In addition, when the first type doped semiconductor material is grown, the first type doped semiconductor material is extended from the top surface T _{30a of} the columnar body 30a to the two columnar bodies 30a, and finally joined together and formed into a plurality of The first type doped semiconductor structure 330. In detail, each first-type doped semiconductor structure 330 is positioned on each of which a columnar body 30a, and each of the first type doped semiconductor structure 330 having a bottom surface and a plurality of side wall surfaces ₃₃₀ B connected to the bottom surface ₃₃₀ of the B S _330, A portion of the bottom surface B ₃₃₀ of the first type doped semiconductor structure 330 is in direct contact with the protective layer 320 and the top surface T _{30a of the} columnar body 30a.

The shape of the bottom surface B ₃₃₀ of the first type doped semiconductor structure 330 is, for example, a hexagon, and the hexagon here does not define a regular hexagon. In detail, the shape of the bottom surface B ₃₃₀ of the first type doped semiconductor structure 330 may vary according to the process parameters. Therefore, the present invention does not limit the hexagon to be a regular hexagon (ie, does not define six sides). The shape is six equal lengths). Further, a first-type doping of the bottom area of the semiconductor structure 330 away from the bottom surface to the bottom surface ₃₃₀ B B ₃₃₀ decreasing direction, and each side wall surface opposite the bottom surface ₃₃₀ S B ₃₃₀ is inclined a first angle θ1. This first angle θ1 is, for example, not more than 65 degrees. The first angle θ1 herein refers to the angle between the sidewall surface S _{330 of the} first type doped semiconductor structure 330 and the bottom surface B ₃₃₀ , and the first angle θ1 “not greater than” 65 degrees means that the first angle θ1 Between 0 and 65 degrees.

With process parameters (including process time, temperature, pressure, etc.), changes in the first type of doped semiconductor material (affecting the lattice arrangement) and the spacing P _30a or column between the adjacent two columns 30a The change in the diameter D _30a of 30a, the topography (including the shape and the first angle θ1) or the size of the first type doped semiconductor structure 330 formed on the columnar body 30a may also differ. For example, when the temperature of the process is changed, the sidewall face S _{330 of the} first type doped semiconductor structure ₃₃₀ may form a face of {10-1n}, where n is an integer. Taking n as 1 as an example, the angle between the side wall surface S ₃₃₀ (ie, the surface of {10-11}) and the bottom surface B ₃₃₀ (for example, the c plane) is, for example, about 62 degrees, but the present invention does not need to define the bottom surface B ₃₃₀ or The plane of the side wall surface S ₃₃₀ shall be a plane of c plane and {10-1N}. In other embodiments, the bottom surface B ₃₃₀ may also be a -c plane, and the side wall surface S ₃₃₀ may be a plane that is not more than 65 degrees with respect to the -c plane.

Further, the shape of the first type doped semiconductor structure 330 may be a plate shape or a pyramid shape. In detail, referring to FIG. 3C and FIG. 3C', when the process time is small, the temperature is high, the pressure is low, the pitch P _30a between the adjacent two columnar bodies 30a is large or the diameter D of the columnar body 30a is D. _{When 30a is} large, the shape of the first type doped semiconductor structure 330 may be, for example, a plate shape as shown in FIG. 3C'. It should be noted that in order to smoothly extend and bond the first type doped semiconductor material from the top surface T _{30a of} the columnar body 30a to the two columnar bodies 30a, between the adjacent two columnar bodies 30a The pitch P _30a needs to be no more than 5 μm. On the other hand, when the process time is increased, the temperature is lowered, the pressure is increased, the pitch P _30a between the adjacent two columns 30a is reduced, or the diameter D _{30a of the} columnar body 30a is reduced, the first type doped semiconductor structure 330 The shape will be, for example, a pyramid shape as shown in Fig. 3C.

It is worth mentioning that when growing the first type of doped semiconductor material, The secondary growth effect of Epitaxial lateral overgrowth (ELOG) can reduce the stress on the first type of doped semiconductor material and reduce the occurrence of stacking defaults or dislocations. Therefore, the luminous efficiency of the semiconductor element of the present embodiment can be effectively improved.

In addition, after the first type doped semiconductor material is extended from the top surface T _{30a of} the columnar body _30a to the two columnar bodies 30a and joined, the void V1 generated by the temperature rising process described in FIG. 3B forms a Closed space. Since the medium (for example, air) in this space is different from the medium around it (including the material of the first type doped semiconductor material and the protective layer 320), the light emitted by the luminescent layer passes through the closed space. The probability of being refracted is increased, thereby increasing the light extraction rate of the semiconductor element, and the luminous efficiency of the semiconductor element of the present embodiment is further improved.

Referring to FIG. 3D, a plurality of light emitting layers 340 are formed on the sidewall surface S ₃₃₀ of the first type doped semiconductor structure 330. This embodiment is exemplified by the two-layer light-emitting layers 340a and 340b, but the present invention is not limited to the number of the light-emitting layers 340. Further, the light emitting layers 340a, 340b are conformed to the sidewall surface S ₃₃₀ of the first type doped semiconductor structure 330. Specifically, the light emitting layers 340a, 340b undulate with respect to the bottom surface B _{330 of the} first type doped semiconductor structure 330.

It is worth mentioning that the light-emitting layer of the prior art is formed on the two-dimensional first-type doped semiconductor layer (the contact surface of the light-emitting layer and the first-type doped semiconductor layer is a plane). In contrast, the light-emitting layer 340 of the present embodiment is formed on the first-type doped semiconductor structure 330 having three dimensions of undulations. Therefore, the light emitting layer 340 of the embodiment and the first type doped semiconductor structure 33 The contact area is large. In other words, the semiconductor structure of the present embodiment can have a larger effective light-emitting area than conventional techniques.

Further, the side wall surface S _{340b of} the uppermost light-emitting layer 340b is inclined with respect to the bottom surface B ₃₃₀ , and the degree of relative inclination is substantially the same as the degree of inclination of the aforementioned side wall surface S _{330 with} respect to the bottom surface B ₃₃₀ . In detail, the second angle θ2 of the side wall surface S _{340b of the} light-emitting layer 340b and the bottom surface B ₃₃₀ is substantially the same as the first angle θ1. Therefore, the sidewall surface S _{340b of the} light-emitting layer 340b can follow the sidewall surface S _{330 of the} first-type doped semiconductor structure ₃₃₀ to form a surface of, for example, {10-1N}.

It is worth mentioning that in the c plane, when a voltage is applied to the semiconductor component, the generation of the polarization field is liable to cause a Quantum Confined Stark Effect (QCSE) in the quantum well, which reduces the semiconductor component. Luminous efficiency. In general, in order to alleviate the quantum-limited Stark effect, conventional techniques use a substrate having a semi-polarized surface instead of the aforementioned c-plane substrate to grow a film layer of a semiconductor element. However, such substrates are very expensive to manufacture. In contrast, by the present embodiment may be a light emitting layer 340b, a first side wall surface S inherited type side wall surface _340b of the semiconductor structure 330 is doped to form ₃₃₀ S {10-1N} The semi-polar surfaces, thereby slowing quantum Limiting the Stark effect, the built-in electric field in the quantum well is reduced, the internal quantum efficiency (IQE) is improved, and the radiation recombination time of the quantum well is reduced. In other words, the present embodiment can produce a semi-polarized surface in a general plane (referring to a non-semi-polar plane, such as a c plane), and achieve the aforementioned effect of slowing down the quantum confined Stuck effect.

In addition, the multilayer light-emitting layer 340 includes a metal element, and the metal element has a content of three or more kinds in the light-emitting layer 340. In the present embodiment, the metal element is, for example, indium. Specifically, the light-emitting layers 340a, 340b are, for example, a quantum well layer or a multiple quantum well (MQW) layer. In other words, the light-emitting layers 340a, 340b may each include at least one quantum barrier layer and at least one quantum well layer. The chemical barrier of the quantum barrier layer of the luminescent layers 340a, 340b and the quantum well layer is, for example, In _x Ga _1-x N, where x represents the molar law of the element and x is between 0 and 0.4. In the present embodiment, the x of the quantum barrier layer is, for example, between 0 and 0.4, and the x of the quantum well layer is, for example, between 0 and 0.4.

In the same light-emitting layer 340a (or light-emitting layer 340b), the indium content of the quantum barrier layer may be different from the indium content of the quantum well layer, and the indium content of the quantum barrier layer may have an indium content corresponding to the quantum well layer. A preferred range. In other words, within the same luminescent layer 340a (or luminescent layer 340b), there may be two indium contents (ie, the indium content of the quantum barrier layer and the indium content of the quantum well layer). Further, in different light-emitting layers 340a and 340b, the indium content in the quantum well layer may be different. Therefore, in the light-emitting layer 340 of the present embodiment, there may be three or more kinds of indium contents. It should be noted that although the light-emitting layers 340a and 340b are the same thickness in FIG. 3D, the present invention does not limit the thickness of each of the light-emitting layers 340a and 340b, and the thickness of the light-emitting layers 340a and 340b depends on actual needs.

By modulating the content of indium in the light-emitting layer 340 (i.e., changing x), the semiconductor device of the present embodiment can emit light covering the visible light band. For example, when the x of the equivalent subwell layer is 0.13 (the chemical formula is In _0.13 Ga _0.87 N), and the x of the quantum barrier layer is 0 (the chemical formula is GaN), the luminescent layer 340 can emit blue light. Alternatively, when the x of the equivalent sub-well layer is 0.23 (the chemical formula is In _0.23 Ga _0.77 N), and the x of the quantum barrier layer is 0.1 (the chemical formula is In _0.1 Ga _0.9 N), the luminescent layer 340 can emit green light.

It should be noted that the x of the quantum well layer and the x of the quantum barrier layer of the light-emitting layer 340 in the preceding paragraph are merely illustrative and not intended to limit the present invention. Those skilled in the art can obtain different bands by changing the molar fraction (indicator x) of the indium content of the quantum well layer in each of the light-emitting layers 340 and the molar fraction of the indium content of the quantum barrier layer. Light. Further, the molar fraction (indicator x) of the indium content of the quantum well layer in each of the light-emitting layers 340 may be different from the molar fraction of the indium content of the quantum barrier layer, and the indium content of the quantum barrier layer is Mohr. The fraction will vary with the change in the molar fraction of the indium content of the quantum well layer. For example, the molar fraction of the indium content of the quantum barrier layer may increase as the molar fraction of the indium content of the quantum well layer increases.

In this embodiment, the content of the metal element indium in the multilayer light-emitting layer 340 disposed on the first-type doped semiconductor structure 330 is modulated (the content of the metal gallium varies with the content of indium), so that the multilayer The wavelength of the light emitted by the luminescent layer 340 can cover the wavelength range of visible light. In this way, the semiconductor component can emit color light of different wavelength bands and mix white light. In other words, the semiconductor device of the present embodiment can modulate the content of the metal element in the plurality of light-emitting layers 340 disposed on the first-type doped semiconductor structure 330 without arranging the phosphor layer, thereby making the multi-layer light-emitting layer The wavelength of the light emitted by 340 can cover the wavelength range of visible light. Therefore, compared to the prior art The fluorescent element is mixed with white light, and the semiconductor element of the embodiment can reduce the problem of the absorption energy of the phosphor powder and the problem of poor conversion efficiency of the long-wavelength light of the phosphor powder, thereby producing high power and good color rendering. Semiconductor component.

Referring to FIG. 3E, a second type doped semiconductor layer 350 is formed on the uppermost light emitting layer 340b, wherein the second type doped semiconductor layer 350 is, for example, conformed to the sidewall surface S _{340b of the} light emitting layer _340b . In addition, in the present embodiment, the second type doped semiconductor layer 350 is exemplified by P-type gallium nitride, but the present invention is not limited to the first type and the second type, but only the first type. One of the first type and the second type is a P type, and the other of the first type and the second type is an N type. In addition, the method of forming the second type doped semiconductor layer 350 may be organic metal chemical vapor deposition, molecular beam epitaxy, sputtering, evaporation, pulsed laser deposition, vapor epitaxy or liquid phase epitaxy. .

Referring to FIG. 3F, the semiconductor device of the present embodiment may further form a conductive layer 360 on the second type doped semiconductor layer 350. The conductive layer 360 described herein is the aforementioned current diffusion layer. In the present embodiment, the material of the conductive layer 360 is, for example, a transparent material, particularly a transparent conductive material. The transparent material described herein generally refers to a material that generally has a high transmittance, and is not intended to define a material having a transmittance of 100%. Further, the transparent conductive material is, for example, a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or at least The stack of the two.

Referring to FIG. 3G, the semiconductor device 200 of the present embodiment may further be in a region other than the columnar body of the first type doped semiconductor material layer (ie, A first electrode 372 and a second electrode 374 are respectively formed on the bottom portion 30b) and the conductive layer 360. The first electrode 372 and the second electrode 374 may be a single layer or a plurality of layers of conductive materials, and the conductive material is, for example, Gold, titanium, aluminum, chromium, platinum, other conductive materials or a combination of these materials. After the first electrode 372 and the second electrode 374 are completed, the semiconductor device 200 of the present embodiment is initially completed.

In summary, the present invention modulates the content of the metal element in the multi-layered light-emitting layer disposed on the first-type doped semiconductor structure, so that the wavelength of the light emitted by the multi-layered light-emitting layer can cover the wavelength range of visible light. . The semiconductor element of the present embodiment can reduce the problem of the energy absorption of the phosphor powder and the problem of poor conversion efficiency of the long-wavelength light of the phosphor powder, thereby producing high power and color rendering. Good semiconductor components.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Substrate

20‧‧‧Undoped semiconductor layer

30‧‧‧First type doped semiconductor material layer

30a‧‧‧ columnar body

30b‧‧‧ bottom

40‧‧‧ dielectric layer

50‧‧‧generation transfer layer

100, 310‧‧‧ substrate

200‧‧‧Semiconductor components

320‧‧‧Protective layer

330‧‧‧First type doped semiconductor structure

340, 340a, 340b‧‧‧ luminescent layer

350‧‧‧Second type doped semiconductor layer

360‧‧‧ Conductive layer

372‧‧‧first electrode

374‧‧‧second electrode

B‧‧‧Base

P1, P2‧‧‧ columnar pattern

V1‧‧‧ pores

S _30a ‧‧‧ Sidewall

S ₃₃₀ , S _340b ‧‧‧ side wall

T _30a ‧‧‧ top

B ₃₃₀ ‧‧‧Bottom

D _30a , D ₅₀ ‧‧‧ diameter

P _30a , P ₅₀ ‧‧‧ spacing

H _30a ‧‧‧ Height

H ₂₀ , H ₃₀ , H ₄₀ , H ₅₀ ‧ ‧ thickness

Θ1‧‧‧ first angle

Θ2‧‧‧second angle

1 is a flow chart showing the fabrication of a semiconductor device in accordance with an embodiment of the invention.

2A to 2E are schematic cross-sectional views showing a manufacturing process of the substrate described in the step S100.

3A to 3G are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

10‧‧‧Substrate

20‧‧‧Undoped semiconductor layer

30a‧‧‧ columnar body

30b‧‧‧ bottom

200‧‧‧Semiconductor components

320‧‧‧Protective layer

330‧‧‧First type doped semiconductor structure

340, 340a, 340b‧‧‧ luminescent layer

350‧‧‧Second type doped semiconductor layer

360‧‧‧ Conductive layer

372‧‧‧first electrode

374‧‧‧second electrode

B‧‧‧Base

S ₃₃₀ , S _340b ‧‧‧ side wall

B ₃₃₀ ‧‧‧Bottom

Θ1‧‧‧ first angle

Θ2‧‧‧second angle

Claims (17)

A method of fabricating a semiconductor device, comprising: providing a substrate having a base and a plurality of columnar bodies on the base; the sidewalls of each of the columns and the columnar body Forming a protective layer on the base; growing a first type of doped semiconductor material on the top surface of the plurality of columns to form a plurality of first type doped semiconductor structures, wherein each of the first type doped semiconductor structures has a bottom surface and a plurality of sidewall surfaces connected to the bottom surface, wherein each of the sidewall surfaces is inclined with respect to the bottom surface; forming a plurality of light emitting layers on the sidewall surfaces of the first type of doped semiconductor structures, wherein each of the light emitting layers comprises a light emitting layer a metal element, and the metal element has a content of three or more kinds in the light-emitting layers; and forming a second-type doped semiconductor layer on the uppermost light-emitting layer, wherein a sidewall surface of the uppermost light-emitting layer and the first layer The bottom surface of the doped semiconductor structure is sandwiched by an angle that is no greater than 65 degrees. The method for fabricating a semiconductor device according to claim 1, wherein the protective layer is made of cerium oxide. The method for fabricating a semiconductor device according to claim 1, wherein the first type of doped semiconductor structure has a shape of a plate or a pyramid. The method of fabricating a semiconductor device according to claim 1, wherein the metal element is indium. The method of fabricating a semiconductor device according to claim 1, wherein the luminescent layer has a chemical formula of In _x Ga _1-x N and x is between 0 and 0.4. The method of fabricating a semiconductor device according to claim 1, wherein one of the first type and the second type is a P type, and the other of the first type and the second type is an N type. The method for fabricating a semiconductor device according to claim 1, further comprising: forming a conductive layer on the second type doped semiconductor layer. The method of fabricating the semiconductor device of claim 7, wherein the conductive layer is a transparent conductive layer. The method for fabricating a semiconductor device according to claim 1, wherein the substrate is formed by: forming an undoped semiconductor layer on a substrate; growing the first type on the undoped semiconductor layer Doping a semiconductor material to form a first type doped semiconductor material layer; and patterning the first type doped semiconductor material layer to form the columnar body and the base, wherein the base includes the first type of doping A region other than the plurality of pillars of the semiconductor material layer, the substrate, and the undoped semiconductor layer. A semiconductor device comprising: a substrate; an undoped semiconductor layer disposed on the substrate; a first doped semiconductor material layer disposed on the undoped semiconductor layer, wherein the first doped semiconductor The material layer includes a plurality of columnar bodies; a protective layer disposed on sidewalls of the pillars and the first type of doped semiconductor material layer between the pillars; and a plurality of first type doped semiconductor structures disposed on the pillars The top surface of the first type doped semiconductor structure has a bottom surface and a plurality of sidewall surfaces connected to the bottom surface, and each of the sidewall surfaces is inclined with respect to the bottom surface; and the plurality of light emitting layers are disposed in the first type of doping The sidewalls of the semiconductor structure, wherein each of the light-emitting layers comprises a metal element, and the metal element has a content of three or more kinds in the light-emitting layers; and a second-type doped semiconductor layer is disposed at the most On the upper luminescent layer, the sidewall surface of the uppermost luminescent layer is at an angle to the bottom surface of the first type doped semiconductor structure, the angle being no more than 65 degrees. The semiconductor device according to claim 10, wherein the protective layer is made of cerium oxide. The semiconductor device of claim 10, wherein the first type of doped semiconductor structure has a shape of a plate or a pyramid. The semiconductor device according to claim 10, wherein the metal element is indium. The semiconductor device according to claim 10, wherein the luminescent layer has a chemical formula of In _x Ga _1-x N and x is between 0 and 0.4. The semiconductor device of claim 10, wherein one of the first type and the second type is a P type, and the other of the first type and the second type is an N type. For example, the semiconductor component described in claim 10, And comprising: a conductive layer disposed on the second type doped semiconductor layer. The semiconductor device of claim 16, wherein the conductive layer is a transparent conductive layer.