TWI502604B - Memory card device, computer system and control method of solid state disk thereof - Google Patents

Description

Memory card device, computer system and solid state hard disk control method thereof

The present invention relates to a solid state hard disk control technology, and more particularly to a memory card device, a computer system and a solid state hard disk control method thereof.

For an existing device with a hard disk drive (HDD) or a solid state disk (SSD), in the idle state, the power saving mode is entered through the power management setting. The so-called power saving mode can be divided into a partial sleep mode and a slumber mode. However, when the aforementioned device enters the partial sleep mode, the host side still needs to wake up every 10 μs, or when the aforementioned device enters the slumber mode, the host side also needs to wake up every 10 ms. That is to say, the aforementioned device cannot enter a complete sleep state, so that power cannot be turned off and there is a phenomenon of energy consumption.

In addition, with the existing SSD device, the SSD device has only one set of ICs for controlling data storage and memory particles for data storage, so the memory particles on the SSD device may be damaged after being used for a long time. Therefore, there is a risk of data loss. In severe cases, it is more likely that the electronic device using the SSD device will not function properly. It can be seen that there are still many improvements in current SSD devices.

In view of this, the present invention provides a memory card device, a computer system and a solid state hard disk control method thereof, thereby solving the problems described in the prior art.

The invention provides a computer system comprising a host and a memory card device. The host includes an embedded controller, a chipset, and a detection circuit. The chip set is coupled to the embedded controller. The detection circuit is coupled to the embedded controller. The memory card device includes a first control unit, a solid state hard disk interface, and an identification circuit. The solid state hard disk interface is coupled to the first control unit. The identification circuit is coupled to the solid state hard disk interface. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

The present invention further provides a solid state hard disk control method comprising the following steps. A host is provided, wherein the host comprises an embedded controller, a chip set and a detecting circuit, and the embedded controller is coupled to the chip set and the detecting circuit. A memory card device is provided, wherein the memory card device comprises a first control unit, a solid state hard disk interface and an identification circuit, and the solid state hard disk interface is coupled to the first control unit and the identification circuit. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

The present invention further provides a memory card device suitable for use in a host. The host includes an embedded controller, a chip set, and a detection circuit. The embedded controller is coupled to the chip set and the detection circuit. The memory card device includes a first control unit, a solid state hard disk interface, and an identification circuit. The solid state hard disk interface is coupled to the first control unit and the identification circuit. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

In an embodiment of the invention, the solid state hard disk interface is a mini serial advanced technology attachment (mSATA) interface.

In an embodiment of the invention, the detecting circuit includes a first resistor and a second resistor, and the first resistor is coupled between the embedded controller and a ground. The second resistor is coupled between an operating voltage and the solid state hard disk interface.

In an embodiment of the invention, the memory card device further includes a first memory unit, a second control unit, and a second memory unit. The first memory unit is operative to react to the control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface. The second control unit is coupled to a reserved pin other than the standard pin of the solid state hard disk interface. The second memory unit operates in response to control by the second control unit.

In an embodiment of the invention, the first memory unit and the second memory unit perform data backup with each other to form a RAID (RAID 0) disk.

Based on the above, the present invention uses a detection circuit, and the memory card device uses an identification circuit to generate a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve power off and power. On the other hand, the present invention can extend the memory card device to two sets of control units for data storage, and back up each other to form a disk application with a zone set (RAID 0), thereby improving speed, data backup, and large Reduce the risk of data loss.

The above described features and advantages of the invention will be apparent from the following description.

Reference will now be made in detail be made to the embodiments of the invention In addition, wherever possible, the same reference numerals in the drawings

1 is a schematic diagram of a computer system 100 in accordance with an embodiment of the present invention. Please refer to Figure 1. Computer system 100 includes a memory card device 50 and a host computer 90. The host 90 includes an embedded controller 60, a chipset 70, and a detection circuit 80. Moreover, the embedded controller 60 is coupled between the chip set 70 and the detecting circuit 80.

The memory card device 50 is a solid state disk (SSD) device including a memory unit 10, a control unit 12, a solid state hard disk interface 40, and an identification circuit 30. The solid state hard disk interface 40 is coupled between the control unit 12 and the identification circuit 30. The memory unit 10 can operate in response to the control of the control unit 12. The memory unit 10 can be a NAND flash memory, but is not limited thereto.

When the memory card device 50 is connected to the host 90, the solid state hard disk interface 40 is coupled to the embedded controller 60, the chip set 70 and the detecting circuit 80, so that the detecting circuit 80 can generate a detect in response to the identifying circuit 30. Measuring voltage V _DET . On the other hand, the power saving mode of the power management may be a partial sleep mode as well as a slumber mode. If the memory card device 50 enters the power saving mode and has passed the preset time or is awakened a predetermined number of times but has not received the use command, the chipset 70 can transmit the consistent energy signal S _DEVSLP to the solid state according to the detected voltage V _{DET .} The disc interface 40 is used to cause the memory card device 50 to turn off the power to enter the full sleep mode.

In some embodiments, the identification circuit 30 can include a resistor R1 coupled between the operating voltage V _CC and the solid state hard disk interface 40. The detecting circuit 80 includes a resistor R2 coupled between the embedded controller 60 and the ground GND. When the memory card device 50 is connected to the host 90, a detection voltage V _DET can be generated by the voltage division principle. The embedded controller 60 can discriminate the type of the memory card device according to the level of the detected detection voltage V _DET . For a memory card device that does not have the identification circuit 30, the detection voltage V _DET can be a zero potential at the ground.

Based on the above, the embodiment of the present invention uses the detection circuit, and the memory card device uses the identification circuit, and generates a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve the purpose of power off and power saving.

More specifically, the solid state hard disk interface 40 can be a mini serial advanced technology attachment (mSATA) interface. The mSATA interface 40 has 52 pins, wherein the standard pins are 2, 4, 6, 9, 15, 18, 21, 23-35, 37, 39-41, 43, 45, 47-52, and the rest. The pin is reserved. The design for the identification circuit 30 and the receive enable signal S _DEVSLP can be configured to be coupled to the 12th pin Pin12 and the 8th pin Pin8 of the reserved pin, respectively. Please note that the reserved reserved bits are not limited to this, and all depend on actual design requirements.

2 is a schematic diagram of a computer system 200 in accordance with another embodiment of the present invention. Please refer to Figure 2. The computer system 200 includes a host computer 90 and a memory card device 150. The computer system 200 is similar to the architecture of the computer system 100. For the same part, see the contents of the embodiment of FIG. 1. Only the differences will be described in detail.

The memory card device 150 includes a memory unit 10, a control unit 12, a memory unit 20, a control unit 22, and a solid state hard disk interface 40. The memory unit 10 is configured to operate in response to the control of the control unit 12, wherein the control unit 12 is coupled to a standard foot of the solid state hard disk interface 40. The memory unit 20 operates in response to control by the control unit 22, and the control unit 22 is coupled to a reserved foot other than the standard pin of the solid state hard disk interface 40. This embodiment can extend the memory card device 150 to two sets of control units 12, 22 for data storage.

It is worth mentioning that, for the application of Redundant Array of Independent Disks (RAID), the memory card device 150 (solid state hard disk device) can make the memory units 10 and 20 back up each other. A disk application with a zone set (RAID 0) is formed, and RAID 0 is the fastest, so that the memory card device 150 can speed up, back up data, and greatly reduce the risk of data loss.

In addition, when the solid state hard disk interface 40 is an mSATA interface, the control unit 12 can be coupled to the standard pins 23, 25, 31, and 33 of the solid state hard disk interface 40. The control unit 22 can be coupled to the reserved pins 3, 5, 11, and 13 of the mSATA interface 40 or to the 36th, 38th, 46th, and 48th pins. Please note that the reserved reserved bits are not limited to this, and all depend on actual design requirements.

Based on the content disclosed in the above embodiments, a general-purpose solid state hard disk control method can be integrated. More specifically, FIG. 3 is a flow chart of a solid state hard disk control method according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 3 together, the solid state hard disk control method of this embodiment may include the following steps: Step S301, a host 90 is provided. The main unit 90 includes an embedded controller 60, a chip set 70, and a detecting circuit 80. The embedded controller 60 is coupled to the chip set 70 and the detecting circuit 80.

In step S303, a memory card device 50 is provided. The memory card device 50 includes a control unit 12, a solid state hard disk interface 40, and an identification circuit 30, wherein the solid state hard disk interface 40 is coupled to the control unit 12 and the identification circuit 30.

In step S305, the host 90 is connected to the memory card device 50. Next, in step S307, it is determined whether or not the detection voltage V _DET is generated. If the determination result is YES, the process proceeds to step S309. When the memory card device 50 is connected to the host 90, the solid state hard disk interface 40 is coupled to the embedded controller 60, the chip set 70 and the detecting circuit 80, so that the detecting circuit 80 generates a response in response to the identifying circuit 30. Detection voltage V _DET .

In step S309, it is determined whether or not the power saving mode is entered. If the determination result is YES, the process proceeds to step S311.

In step S311, it is determined whether a predetermined time has elapsed or is awakened a predetermined number of times but the usage instruction has not been received. If the determination result is yes, the process proceeds to step S313.

In step S313, the chipset 70 of the host 90 transmits the coincidence signal S _DEVSLP to the solid-state hard disk interface 40 of the memory card device 50 according to the detection voltage V _DET . Next, in step S315, the memory card device 50 enters the full sleep mode according to the enable signal S _DEVSLP to achieve the purpose of power off and power saving.

In summary, the present invention uses a detection circuit for the host, and the memory card device uses an identification circuit to generate a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve power off and power. On the other hand, the present invention can extend the memory card device to two sets of control units for data storage, and back up each other to form a disk application with a zone set (RAID 0), thereby improving speed, data backup, and large Reduce the risk of data loss.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Memory unit

12. . . control unit

30. . . Identification circuit

40. . . Solid state hard disk interface

50. . . Memory card device

60. . . Embedded controller

70. . . Chipset

80. . . Detection circuit

90. . . Host

100. . . computer system

GND. . . Ground terminal

Pin12, Pin8. . . Reserved feet outside the standard pin

R1, R2. . . resistance

S _DEVSLP . . . Enable signal

V _CC . . . Operating Voltage

V _DET . . . Detection voltage

S301～S315. . . Each step of the solid state hard disk control method according to an embodiment of the present invention

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention

1 is a schematic diagram of a computer system in accordance with an embodiment of the present invention.

2 is a schematic diagram of a computer system in accordance with another embodiment of the present invention.

3 is a flow chart of a solid state hard disk control method in accordance with an embodiment of the present invention.

10. . . Memory unit

12. . . control unit

30. . . Identification circuit

40. . . Solid state hard disk interface

50. . . Memory card device

60. . . Embedded controller

70. . . Chipset

80. . . Detection circuit

90. . . Host

100. . . computer system

GND. . . Ground terminal

Pin12, Pin8. . . Reserved feet outside the standard pin

R1, R2. . . resistance

S _DEVSLP . . . Enable signal

V _CC . . . Operating Voltage

V _DET . . . Detection voltage

Claims (8)

A computer system comprising: a host, comprising: an embedded controller; a chipset coupled to the embedded controller; and a detection circuit coupled to the embedded controller; and a memory card device, including a first control unit; a solid state hard disk interface coupled to the first control unit; and an identification circuit coupled to the solid state hard disk interface; wherein, when the memory card device is connected to the host, the solid state hard The disc interface is coupled to the embedded controller, the chip set and the detecting circuit, so that the detecting circuit generates a detecting voltage in response to the identifying circuit; and if the memory card device enters the power saving mode and passes through After a predetermined time or a predetermined number of times of waking up but still not receiving the use instruction, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby causing the memory card device to enter a full sleep mode; The detection circuit includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. The computer system of claim 1, wherein the memory card device further comprises: a first memory unit is operatively coupled to the control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface; and a second control unit coupled to the solid state drive a reserved pin other than the standard pin of the interface; and a second memory unit that operates in response to control by the second control unit. The computer system of claim 2, wherein the first memory unit and the second memory unit back up each other to form a magnetic disk of a band set. A solid state hard disk control method includes: providing a host, wherein the host includes an embedded controller, a chip set, and a detecting circuit, the embedded controller is coupled to the chip set and the detecting circuit; a memory card device, wherein the memory card device comprises a first control unit, a solid state hard disk interface and an identification circuit, the solid state hard disk interface is coupled to the first control unit and the identification circuit; when the memory card device is connected The solid state hard disk interface is coupled to the embedded controller, the chip set and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit; and if the memory card After the device enters the power-saving mode, and after a predetermined time or wake-up a predetermined number of times but has not received the use command, the chipset transmits a consistent energy signal to the solid-state hard disk interface according to the detected voltage, thereby making the memory The card device enters a full sleep mode; The detection circuit includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. The solid state hard disk control method of claim 4, wherein the memory card device further comprises: a first memory unit, responsive to control of the first control unit, wherein the first control unit is coupled a standard pin connected to the solid state hard disk interface; a second control unit coupled to the reserved pin outside the standard pin of the solid state hard disk interface; and a second memory unit responsive to the second The control unit operates under the control of the control unit. A memory card device is suitable for use in a host, the host includes an embedded controller, a chip set, and a detecting circuit, the embedded controller is coupled to the chip set and the detecting circuit, the memory card device The method includes: a first control unit; a solid state hard disk interface coupled to the first control unit; and an identification circuit coupled to the solid state hard disk interface; wherein the solid state device is connected to the host, the solid state The hard disk interface is coupled to the embedded controller, the chip set and the detecting circuit, so that the detecting circuit generates a detecting voltage in response to the identifying circuit; and if the memory card device enters a power saving mode, and After a preset time After being awake for a predetermined number of times but still not receiving the use command, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, so that the memory card device enters a full sleep mode; wherein the detecting circuit The method includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. The memory card device of claim 6, wherein the memory card device further comprises: a first memory unit, responsive to control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface; a second control unit coupled to the reserved pin other than the standard pin of the solid state hard disk interface; and a second memory unit responsive to the second control unit Control and operate. The memory card device of claim 7, wherein the first memory unit and the second memory unit back up each other to form a magnetic disk of a zone set.