TWI502604B - Memory card device, computer system and control method of solid state disk thereof - Google Patents

Memory card device, computer system and control method of solid state disk thereof Download PDF

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TWI502604B
TWI502604B TW101116568A TW101116568A TWI502604B TW I502604 B TWI502604 B TW I502604B TW 101116568 A TW101116568 A TW 101116568A TW 101116568 A TW101116568 A TW 101116568A TW I502604 B TWI502604 B TW I502604B
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solid state
hard disk
coupled
memory card
state hard
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TW101116568A
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TW201346928A (en
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Chih Chieh Yin
Che Wei Lin
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Acer Inc
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記憶卡裝置、計算機系統及其固態硬碟控制方法Memory card device, computer system and solid state hard disk control method thereof

本發明是有關於一種固態硬碟控制技術,且特別是有關於一種記憶卡裝置、計算機系統與其固態硬碟控制方法。The present invention relates to a solid state hard disk control technology, and more particularly to a memory card device, a computer system and a solid state hard disk control method thereof.

對於現有具硬碟機(hard disk drive,HDD)或固態硬碟(solid state disk,SSD)的裝置而言,在閒置狀態時,會透過電源管理的設定而進入省電模式。所謂省電模式可以分為部分睡眠模式(partial mode)以及微睡模式(slumber mode)。然而,當前述裝置進入部分睡眠模式時,主機端仍然需要每10μs醒來一次,或者當前述裝置進入微睡模式時,主機端也需要每10ms醒來一次。也就是說,前述裝置無法進入完全休眠,於是無法關電而存在耗能的現象。For an existing device with a hard disk drive (HDD) or a solid state disk (SSD), in the idle state, the power saving mode is entered through the power management setting. The so-called power saving mode can be divided into a partial sleep mode and a slumber mode. However, when the aforementioned device enters the partial sleep mode, the host side still needs to wake up every 10 μs, or when the aforementioned device enters the slumber mode, the host side also needs to wake up every 10 ms. That is to say, the aforementioned device cannot enter a complete sleep state, so that power cannot be turned off and there is a phenomenon of energy consumption.

另外,對於現有的SSD裝置而言,SSD裝置上僅具有一組用於控制資料儲存的IC與用於資料保存的記憶顆粒,因此在使用久之後,SSD裝置上的記憶顆粒有可能會損壞,所以存在資料遺失的風險,嚴重時更可能造成使用SSD裝置的電子設備無法正常運作。由此可見,目前的SSD裝置仍有許多改進之處。In addition, with the existing SSD device, the SSD device has only one set of ICs for controlling data storage and memory particles for data storage, so the memory particles on the SSD device may be damaged after being used for a long time. Therefore, there is a risk of data loss. In severe cases, it is more likely that the electronic device using the SSD device will not function properly. It can be seen that there are still many improvements in current SSD devices.

有鑑於此,本發明提出一種記憶卡裝置、計算機系統與其固態硬碟控制方法,藉以解決先前技術所述及的問題。In view of this, the present invention provides a memory card device, a computer system and a solid state hard disk control method thereof, thereby solving the problems described in the prior art.

本發明提出一種計算機系統,其包括一主機以及一記憶卡裝置。主機包括一嵌式控制器、一晶片組以及一偵測電路。晶片組耦接至嵌式控制器。偵測電路耦接至嵌式控制器。記憶卡裝置包括一第一控制單元、一固態硬碟介面以及一識別電路。固態硬碟介面耦接第一控制單元。識別電路耦接固態硬碟介面。當記憶卡裝置連接至主機時,固態硬碟介面耦接至嵌式控制器、晶片組與偵測電路,藉以使偵測電路反應於識別電路產生一偵測電壓。倘若記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則晶片組根據偵測電壓傳送一致能信號至固態硬碟介面,藉以使記憶卡裝置進入完全休眠模式。The invention provides a computer system comprising a host and a memory card device. The host includes an embedded controller, a chipset, and a detection circuit. The chip set is coupled to the embedded controller. The detection circuit is coupled to the embedded controller. The memory card device includes a first control unit, a solid state hard disk interface, and an identification circuit. The solid state hard disk interface is coupled to the first control unit. The identification circuit is coupled to the solid state hard disk interface. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

本發明另提出一種固態硬碟控制方法,包括下列步驟。提供一主機,其中主機包括一嵌式控制器、一晶片組以及一偵測電路,嵌式控制器耦接至晶片組與偵測電路。提供一記憶卡裝置,其中記憶卡裝置包括一第一控制單元、一固態硬碟介面以及一識別電路,固態硬碟介面耦接至第一控制單元與識別電路。當記憶卡裝置連接至主機時,固態硬碟介面耦接至嵌式控制器、晶片組與偵測電路,藉以使偵測電路反應於識別電路產生一偵測電壓。倘若記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則晶片組根據偵測電壓傳送一致能信號至固態硬碟介面,藉以使記憶卡裝置進入完全休眠模式。The present invention further provides a solid state hard disk control method comprising the following steps. A host is provided, wherein the host comprises an embedded controller, a chip set and a detecting circuit, and the embedded controller is coupled to the chip set and the detecting circuit. A memory card device is provided, wherein the memory card device comprises a first control unit, a solid state hard disk interface and an identification circuit, and the solid state hard disk interface is coupled to the first control unit and the identification circuit. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

本發明另提出一種記憶卡裝置,適於一主機使用,其中主機包括一嵌式控制器、一晶片組以及一偵測電路,嵌式控制器耦接至晶片組與偵測電路。記憶卡裝置包括一第一控制單元、一固態硬碟介面以及一識別電路,固態硬碟介面耦接至第一控制單元與識別電路。當記憶卡裝置連接至主機時,固態硬碟介面耦接至嵌式控制器、晶片組與偵測電路,藉以使偵測電路反應於識別電路產生一偵測電壓。倘若記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則晶片組根據偵測電壓傳送一致能信號至固態硬碟介面,藉以使記憶卡裝置進入完全休眠模式。The present invention further provides a memory card device suitable for use in a host. The host includes an embedded controller, a chip set, and a detection circuit. The embedded controller is coupled to the chip set and the detection circuit. The memory card device includes a first control unit, a solid state hard disk interface, and an identification circuit. The solid state hard disk interface is coupled to the first control unit and the identification circuit. When the memory card device is connected to the host, the solid state hard disk interface is coupled to the embedded controller, the chipset and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit. If the memory card device enters the power saving mode and has not received the use command after a predetermined time or is awake for a predetermined number of times, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby making the memory card The device enters full sleep mode.

在本發明的一實施例中,固態硬碟介面為微型序列先進技術附件(mini serial advanced technology attachment,mSATA)介面。In an embodiment of the invention, the solid state hard disk interface is a mini serial advanced technology attachment (mSATA) interface.

在本發明的一實施例中,偵測電路包括一第一電阻以及一第二電阻,第一電阻耦接於嵌式控制器與一接地端之間。第二電阻耦接於一工作電壓與固態硬碟介面之間。In an embodiment of the invention, the detecting circuit includes a first resistor and a second resistor, and the first resistor is coupled between the embedded controller and a ground. The second resistor is coupled between an operating voltage and the solid state hard disk interface.

在本發明的一實施例中,記憶卡裝置更包括一第一記憶體單元、一第二控制單元以及一第二記憶體單元。第一記憶體單元用以反應於第一控制單元的控制而運作,其中第一控制單元耦接於固態硬碟介面的標準腳位。第二控制單元耦接固態硬碟介面的標準腳位之外的保留腳位。第二記憶體單元反應於第二控制單元的控制而運作。In an embodiment of the invention, the memory card device further includes a first memory unit, a second control unit, and a second memory unit. The first memory unit is operative to react to the control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface. The second control unit is coupled to a reserved pin other than the standard pin of the solid state hard disk interface. The second memory unit operates in response to control by the second control unit.

在本發明的一實施例中,第一記憶體單元與第二記憶體單元相互做資料備份而形成一帶區集(RAID 0)的磁碟。In an embodiment of the invention, the first memory unit and the second memory unit perform data backup with each other to form a RAID (RAID 0) disk.

基於上述,本發明因主機採用偵測電路,而記憶卡裝置採用識別電路,在記憶卡裝置連接至主機時可產生一偵測電壓,使得主機得知記憶卡裝置的種類。並且在記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,主機根據偵測電壓傳送一致能信號至記憶卡裝置,藉以使記憶卡裝置進入完全休眠模式,達到關電及省電。另一方面,本發明可以使記憶卡裝置擴展至兩組用於資料儲存的控制單元,相互做資料備份而形成一帶區集(RAID 0)的磁碟應用,所以可以提升速度、資料備份以及大幅地減低資料遺失的風險。Based on the above, the present invention uses a detection circuit, and the memory card device uses an identification circuit to generate a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve power off and power. On the other hand, the present invention can extend the memory card device to two sets of control units for data storage, and back up each other to form a disk application with a zone set (RAID 0), thereby improving speed, data backup, and large Reduce the risk of data loss.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.

現將詳細參考本發明之實施例,並在附圖中說明所述實施例之實例。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件代表相同或類似部分。Reference will now be made in detail be made to the embodiments of the invention In addition, wherever possible, the same reference numerals in the drawings

圖1是依照本發明一實施例之計算機系統100的示意圖。請參閱圖1。計算機系統100包括記憶卡裝置50以及主機90。其中主機90包括嵌式控制器60、晶片組70以及偵測電路80。並且,嵌式控制器60耦接於晶片組70與偵測電路80之間。1 is a schematic diagram of a computer system 100 in accordance with an embodiment of the present invention. Please refer to Figure 1. Computer system 100 includes a memory card device 50 and a host computer 90. The host 90 includes an embedded controller 60, a chipset 70, and a detection circuit 80. Moreover, the embedded controller 60 is coupled between the chip set 70 and the detecting circuit 80.

記憶卡裝置50為一種固態硬碟(solid state disk,SSD)的裝置,其包括記憶體單元10、控制單元12、固態硬碟介面40以及識別電路30。固態硬碟介面40耦接於控制單元12與識別電路30之間。而記憶體單元10可反應於控制單元12的控制而運作。記憶體單元10可以為反及閘快閃記憶體(NAND flash memory),但不以此為限。The memory card device 50 is a solid state disk (SSD) device including a memory unit 10, a control unit 12, a solid state hard disk interface 40, and an identification circuit 30. The solid state hard disk interface 40 is coupled between the control unit 12 and the identification circuit 30. The memory unit 10 can operate in response to the control of the control unit 12. The memory unit 10 can be a NAND flash memory, but is not limited thereto.

當記憶卡裝置50連接至主機90時,固態硬碟介面40會耦接至嵌式控制器60、晶片組70與偵測電路80,藉以使偵測電路80可反應於識別電路30產生一偵測電壓VDET 。另一方面,電源管理的省電模式可以為部分睡眠模式以及微睡模式。倘若記憶卡裝置50進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則晶片組70可根據偵測電壓VDET 傳送一致能信號SDEVSLP 至固態硬碟介面40,藉以使記憶卡裝置50關閉電能而進入完全休眠模式。When the memory card device 50 is connected to the host 90, the solid state hard disk interface 40 is coupled to the embedded controller 60, the chip set 70 and the detecting circuit 80, so that the detecting circuit 80 can generate a detect in response to the identifying circuit 30. Measuring voltage V DET . On the other hand, the power saving mode of the power management may be a partial sleep mode as well as a slumber mode. If the memory card device 50 enters the power saving mode and has passed the preset time or is awakened a predetermined number of times but has not received the use command, the chipset 70 can transmit the consistent energy signal S DEVSLP to the solid state according to the detected voltage V DET . The disc interface 40 is used to cause the memory card device 50 to turn off the power to enter the full sleep mode.

在部分實施例中,識別電路30可包括電阻R1,此電阻R1耦接於工作電壓VCC 與固態硬碟介面40之間。偵測電路80包括電阻R2,此電阻R2耦接於嵌式控制器60與接地端GND之間。當記憶卡裝置50連接至主機90時,藉由分壓原理,可以產生出一偵測電壓VDET 。嵌式控制器60可根據所輸入的偵測電壓VDET 的準位來辨別記憶卡裝置的種類。對於不具有識別電路30的記憶卡裝置而言,偵測電壓VDET 可為接地端的零電位。In some embodiments, the identification circuit 30 can include a resistor R1 coupled between the operating voltage V CC and the solid state hard disk interface 40. The detecting circuit 80 includes a resistor R2 coupled between the embedded controller 60 and the ground GND. When the memory card device 50 is connected to the host 90, a detection voltage V DET can be generated by the voltage division principle. The embedded controller 60 can discriminate the type of the memory card device according to the level of the detected detection voltage V DET . For a memory card device that does not have the identification circuit 30, the detection voltage V DET can be a zero potential at the ground.

基於上述,本發明實施例因主機採用偵測電路,而記憶卡裝置採用識別電路,並在記憶卡裝置連接至主機時可產生一偵測電壓,使得主機得知記憶卡裝置的種類。並且在記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,主機根據偵測電壓傳送一致能信號至記憶卡裝置,藉以使記憶卡裝置進入完全休眠模式,達到關電及省電的目的。Based on the above, the embodiment of the present invention uses the detection circuit, and the memory card device uses the identification circuit, and generates a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve the purpose of power off and power saving.

更清楚來說,固態硬碟介面40可以為微型序列先進技術附件(mini serial advanced technology attachment,mSATA)介面。關於mSATA介面40具有52個腳位,其中標準腳位為第2、4、6、9、15、18、21、23-35、37、39-41、43、45、47-52,其餘的腳位為保留腳位。針對識別電路30與用於接收致能信號SDEVSLP 的設計可以經配置而分別連接於保留腳位中的第12腳位Pin12與第8腳位Pin8。請注意,所配置的保留腳位不以此為限,一切端視實際設計需求而論。More specifically, the solid state hard disk interface 40 can be a mini serial advanced technology attachment (mSATA) interface. The mSATA interface 40 has 52 pins, wherein the standard pins are 2, 4, 6, 9, 15, 18, 21, 23-35, 37, 39-41, 43, 45, 47-52, and the rest. The pin is reserved. The design for the identification circuit 30 and the receive enable signal S DEVSLP can be configured to be coupled to the 12th pin Pin12 and the 8th pin Pin8 of the reserved pin, respectively. Please note that the reserved reserved bits are not limited to this, and all depend on actual design requirements.

圖2是依照本發明另一實施例之計算機系統200的示意圖。請參閱圖2。計算機系統200包括主機90與記憶卡裝置150,其中計算機系統200類似於計算機系統100的架構,相同的部分請見圖1實施例的內容。現僅針對不同之處進行詳細說明。2 is a schematic diagram of a computer system 200 in accordance with another embodiment of the present invention. Please refer to Figure 2. The computer system 200 includes a host computer 90 and a memory card device 150. The computer system 200 is similar to the architecture of the computer system 100. For the same part, see the contents of the embodiment of FIG. 1. Only the differences will be described in detail.

記憶卡裝置150包括記憶體單元10、控制單元12、記憶體單元20、控制單元22以及固態硬碟介面40。記憶體單元10用以反應於控制單元12的控制而運作,其中控制單元12耦接於固態硬碟介面40的標準腳位。記憶體單元20反應於控制單元22的控制而運作,而控制單元22耦接固態硬碟介面40的標準腳位之外的保留腳位。本實施例可以使記憶卡裝置150擴展至兩組用於資料儲存的控制單元12、22。The memory card device 150 includes a memory unit 10, a control unit 12, a memory unit 20, a control unit 22, and a solid state hard disk interface 40. The memory unit 10 is configured to operate in response to the control of the control unit 12, wherein the control unit 12 is coupled to a standard foot of the solid state hard disk interface 40. The memory unit 20 operates in response to control by the control unit 22, and the control unit 22 is coupled to a reserved foot other than the standard pin of the solid state hard disk interface 40. This embodiment can extend the memory card device 150 to two sets of control units 12, 22 for data storage.

在此值得一提的是,對於獨立磁碟冗餘陣列(Redundant Array of Independent Disks,RAID)的應用,記憶卡裝置150(固態硬碟裝置)可以使記憶體單元10、20相互做資料備份而形成一帶區集(RAID 0)的磁碟應用,且RAID 0的速度最快,從而記憶卡裝置150可以提升速度、資料備份以及大幅地減低資料遺失的風險。It is worth mentioning that, for the application of Redundant Array of Independent Disks (RAID), the memory card device 150 (solid state hard disk device) can make the memory units 10 and 20 back up each other. A disk application with a zone set (RAID 0) is formed, and RAID 0 is the fastest, so that the memory card device 150 can speed up, back up data, and greatly reduce the risk of data loss.

另外,當固態硬碟介面40為mSATA介面時,控制單元12可耦接於固態硬碟介面40的標準腳位第23、25、31、33腳位。控制單元22可耦接於mSATA介面40的標準腳位之外的保留腳位第3、5、11、13腳位,或者耦接於第36、38、46、48腳位。請注意,所配置的保留腳位不以此為限,一切端視實際設計需求而論。In addition, when the solid state hard disk interface 40 is an mSATA interface, the control unit 12 can be coupled to the standard pins 23, 25, 31, and 33 of the solid state hard disk interface 40. The control unit 22 can be coupled to the reserved pins 3, 5, 11, and 13 of the mSATA interface 40 or to the 36th, 38th, 46th, and 48th pins. Please note that the reserved reserved bits are not limited to this, and all depend on actual design requirements.

基於上述實施例所揭示的內容,可以彙整出一種通用的固態硬碟控制方法。更清楚來說,圖3繪示為本發明一實施例之固態硬碟控制方法的流程圖。請合併參閱圖1和圖3,本實施例之固態硬碟控制方法可以包括以下步驟:步驟S301,提供一主機90。主機90包括嵌式控制器60、晶片組70以及偵測電路80,其中嵌式控制器60耦接至晶片組70與偵測電路80。Based on the content disclosed in the above embodiments, a general-purpose solid state hard disk control method can be integrated. More specifically, FIG. 3 is a flow chart of a solid state hard disk control method according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 3 together, the solid state hard disk control method of this embodiment may include the following steps: Step S301, a host 90 is provided. The main unit 90 includes an embedded controller 60, a chip set 70, and a detecting circuit 80. The embedded controller 60 is coupled to the chip set 70 and the detecting circuit 80.

步驟S303,提供一記憶卡裝置50。記憶卡裝置50包括控制單元12、固態硬碟介面40以及識別電路30,其中固態硬碟介面40耦接至控制單元12與識別電路30。In step S303, a memory card device 50 is provided. The memory card device 50 includes a control unit 12, a solid state hard disk interface 40, and an identification circuit 30, wherein the solid state hard disk interface 40 is coupled to the control unit 12 and the identification circuit 30.

步驟S305,將主機90與記憶卡裝置50進行連接。接著進行步驟S307,判斷是否產生偵測電壓VDET ,倘若判斷結果為是,則進入步驟S309。其中,當記憶卡裝置50連接至主機90時,固態硬碟介面40會耦接至嵌式控制器60、晶片組70與偵測電路80,藉以使偵測電路80反應於識別電路30產生一偵測電壓VDETIn step S305, the host 90 is connected to the memory card device 50. Next, in step S307, it is determined whether or not the detection voltage V DET is generated. If the determination result is YES, the process proceeds to step S309. When the memory card device 50 is connected to the host 90, the solid state hard disk interface 40 is coupled to the embedded controller 60, the chip set 70 and the detecting circuit 80, so that the detecting circuit 80 generates a response in response to the identifying circuit 30. Detection voltage V DET .

步驟S309,判斷是否進入省電模式,倘若判斷結果為是,則進入步驟S311。In step S309, it is determined whether or not the power saving mode is entered. If the determination result is YES, the process proceeds to step S311.

步驟S311,判斷是否經過一預設時間或是被喚醒預定次數但仍未接收使用指令,倘若判斷結果為是,則進入步驟S313。In step S311, it is determined whether a predetermined time has elapsed or is awakened a predetermined number of times but the usage instruction has not been received. If the determination result is yes, the process proceeds to step S313.

步驟S313,主機90的晶片組70根據偵測電壓VDET 傳送一致能信號SDEVSLP 至記憶卡裝置50的固態硬碟介面40。接著進行步驟S315,記憶卡裝置50根據致能信號SDEVSLP 而進入完全休眠模式,達到關電及省電的目的。In step S313, the chipset 70 of the host 90 transmits the coincidence signal S DEVSLP to the solid-state hard disk interface 40 of the memory card device 50 according to the detection voltage V DET . Next, in step S315, the memory card device 50 enters the full sleep mode according to the enable signal S DEVSLP to achieve the purpose of power off and power saving.

綜上所述,本發明因主機採用偵測電路,而記憶卡裝置採用識別電路,在記憶卡裝置連接至主機時可產生一偵測電壓,使得主機得知記憶卡裝置的種類。並且在記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,主機根據偵測電壓傳送一致能信號至記憶卡裝置,藉以使記憶卡裝置進入完全休眠模式,達到關電及省電。另一方面,本發明可以使記憶卡裝置擴展至兩組用於資料儲存的控制單元,相互做資料備份而形成一帶區集(RAID 0)的磁碟應用,所以可以提升速度、資料備份以及大幅地減低資料遺失的風險。In summary, the present invention uses a detection circuit for the host, and the memory card device uses an identification circuit to generate a detection voltage when the memory card device is connected to the host, so that the host knows the type of the memory card device. And after the memory card device enters the power saving mode, and after a predetermined time or is awake for a predetermined number of times but has not received the use command, the host transmits a consistent energy signal to the memory card device according to the detected voltage, so that the memory card device enters Complete sleep mode, to achieve power off and power. On the other hand, the present invention can extend the memory card device to two sets of control units for data storage, and back up each other to form a disk application with a zone set (RAID 0), thereby improving speed, data backup, and large Reduce the risk of data loss.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10...記憶體單元10. . . Memory unit

12...控制單元12. . . control unit

30...識別電路30. . . Identification circuit

40...固態硬碟介面40. . . Solid state hard disk interface

50...記憶卡裝置50. . . Memory card device

60...嵌式控制器60. . . Embedded controller

70...晶片組70. . . Chipset

80...偵測電路80. . . Detection circuit

90...主機90. . . Host

100...計算機系統100. . . computer system

GND...接地端GND. . . Ground terminal

Pin12、Pin8...標準腳位之外的保留腳位Pin12, Pin8. . . Reserved feet outside the standard pin

R1、R2...電阻R1, R2. . . resistance

SDEVSLP ...致能信號S DEVSLP . . . Enable signal

VCC ...工作電壓V CC . . . Operating Voltage

VDET ...偵測電壓V DET . . . Detection voltage

S301~S315...本發明一實施例之固態硬碟控制方法的各步驟S301~S315. . . Each step of the solid state hard disk control method according to an embodiment of the present invention

下面的所附圖式是本發明的說明書的一部分,繪示了本發明的示例實施例,所附圖式與說明書的描述一起說明本發明的原理。The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention

圖1是依照本發明一實施例之計算機系統的示意圖。1 is a schematic diagram of a computer system in accordance with an embodiment of the present invention.

圖2是依照本發明另一實施例之計算機系統的示意圖。2 is a schematic diagram of a computer system in accordance with another embodiment of the present invention.

圖3是依照本發明一實施例之固態硬碟控制方法的流程圖。3 is a flow chart of a solid state hard disk control method in accordance with an embodiment of the present invention.

10...記憶體單元10. . . Memory unit

12...控制單元12. . . control unit

30...識別電路30. . . Identification circuit

40...固態硬碟介面40. . . Solid state hard disk interface

50...記憶卡裝置50. . . Memory card device

60...嵌式控制器60. . . Embedded controller

70...晶片組70. . . Chipset

80...偵測電路80. . . Detection circuit

90...主機90. . . Host

100...計算機系統100. . . computer system

GND...接地端GND. . . Ground terminal

Pin12、Pin8...標準腳位之外的保留腳位Pin12, Pin8. . . Reserved feet outside the standard pin

R1、R2...電阻R1, R2. . . resistance

SDEVSLP ...致能信號S DEVSLP . . . Enable signal

VCC ...工作電壓V CC . . . Operating Voltage

VDET ...偵測電壓V DET . . . Detection voltage

Claims (8)

一種計算機系統,包括:一主機,包括:一嵌式控制器;一晶片組,耦接該嵌式控制器;以及一偵測電路,耦接該嵌式控制器;以及一記憶卡裝置,包括:一第一控制單元;一固態硬碟介面,耦接該第一控制單元;以及一識別電路,耦接該固態硬碟介面;其中,當該記憶卡裝置連接至該主機時,該固態硬碟介面耦接至該嵌式控制器、該晶片組與該偵測電路,藉以使該偵測電路反應於該識別電路產生一偵測電壓;以及倘若該記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則該晶片組根據該偵測電壓傳送一致能信號至該固態硬碟介面,藉以使該記憶卡裝置進入完全休眠模式;其中該偵測電路包括:一第一電阻,耦接於該嵌式控制器與一接地端之間;以及一第二電阻,耦接於一工作電壓與該固態硬碟介面之間。 A computer system comprising: a host, comprising: an embedded controller; a chipset coupled to the embedded controller; and a detection circuit coupled to the embedded controller; and a memory card device, including a first control unit; a solid state hard disk interface coupled to the first control unit; and an identification circuit coupled to the solid state hard disk interface; wherein, when the memory card device is connected to the host, the solid state hard The disc interface is coupled to the embedded controller, the chip set and the detecting circuit, so that the detecting circuit generates a detecting voltage in response to the identifying circuit; and if the memory card device enters the power saving mode and passes through After a predetermined time or a predetermined number of times of waking up but still not receiving the use instruction, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, thereby causing the memory card device to enter a full sleep mode; The detection circuit includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. 如申請專利範圍第1項所述之計算機系統,其中該記憶卡裝置更包括: 一第一記憶體單元,反應於該第一控制單元的控制而運作,其中該第一控制單元耦接於該固態硬碟介面的標準腳位;一第二控制單元,耦接該固態硬碟介面的標準腳位之外的保留腳位;以及一第二記憶體單元,反應於該第二控制單元的控制而運作。 The computer system of claim 1, wherein the memory card device further comprises: a first memory unit is operatively coupled to the control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface; and a second control unit coupled to the solid state drive a reserved pin other than the standard pin of the interface; and a second memory unit that operates in response to control by the second control unit. 如申請專利範圍第2項所述之計算機系統,其中該第一記憶體單元與該第二記憶體單元相互做資料備份而形成一帶區集的磁碟。 The computer system of claim 2, wherein the first memory unit and the second memory unit back up each other to form a magnetic disk of a band set. 一種固態硬碟控制方法,包括:提供一主機,其中該主機包括一嵌式控制器、一晶片組以及一偵測電路,該嵌式控制器耦接至該晶片組與該偵測電路;提供一記憶卡裝置,其中該記憶卡裝置包括一第一控制單元、一固態硬碟介面以及一識別電路,該固態硬碟介面耦接至第一控制單元與該識別電路;當該記憶卡裝置連接至該主機時,該固態硬碟介面耦接至該嵌式控制器、該晶片組與該偵測電路,藉以使該偵測電路反應於該識別電路產生一偵測電壓;以及倘若該記憶卡裝置進入省電模式,且經過一預設時間或是被喚醒預定次數但仍未接收使用指令後,則該晶片組根據該偵測電壓傳送一致能信號至該固態硬碟介面,藉以使該記憶卡裝置進入完全休眠模式; 其中該偵測電路包括:一第一電阻,耦接於該嵌式控制器與一接地端之間;以及一第二電阻,耦接於一工作電壓與該固態硬碟介面之間。 A solid state hard disk control method includes: providing a host, wherein the host includes an embedded controller, a chip set, and a detecting circuit, the embedded controller is coupled to the chip set and the detecting circuit; a memory card device, wherein the memory card device comprises a first control unit, a solid state hard disk interface and an identification circuit, the solid state hard disk interface is coupled to the first control unit and the identification circuit; when the memory card device is connected The solid state hard disk interface is coupled to the embedded controller, the chip set and the detection circuit, so that the detection circuit generates a detection voltage in response to the identification circuit; and if the memory card After the device enters the power-saving mode, and after a predetermined time or wake-up a predetermined number of times but has not received the use command, the chipset transmits a consistent energy signal to the solid-state hard disk interface according to the detected voltage, thereby making the memory The card device enters a full sleep mode; The detection circuit includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. 如申請專利範圍第4項所述之固態硬碟控制方法,其中該記憶卡裝置更包括:一第一記憶體單元,反應於該第一控制單元的控制而運作,其中該第一控制單元耦接於該固態硬碟介面的標準腳位;一第二控制單元,耦接於該固態硬碟介面的標準腳位之外的保留腳位;以及一第二記憶體單元,反應於該第二控制單元的控制而運作。 The solid state hard disk control method of claim 4, wherein the memory card device further comprises: a first memory unit, responsive to control of the first control unit, wherein the first control unit is coupled a standard pin connected to the solid state hard disk interface; a second control unit coupled to the reserved pin outside the standard pin of the solid state hard disk interface; and a second memory unit responsive to the second The control unit operates under the control of the control unit. 一種記憶卡裝置,適於一主機使用,該主機包括一嵌式控制器、一晶片組以及一偵測電路,該嵌式控制器耦接至該晶片組與該偵測電路,該記憶卡裝置包括:一第一控制單元;一固態硬碟介面,耦接該第一控制單元;以及一識別電路,耦接該固態硬碟介面;其中,當該記憶卡裝置連接至該主機時,該固態硬碟介面耦接至該嵌式控制器、該晶片組與該偵測電路,藉以使該偵測電路反應於該識別電路產生一偵測電壓;以及倘若該記憶卡裝置進入省電模式,且經過一預設時間 或是被喚醒預定次數但仍未接收使用指令後,則該晶片組根據該偵測電壓傳送一致能信號至該固態硬碟介面,藉以使該記憶卡裝置進入完全休眠模式;其中該偵測電路包括:一第一電阻,耦接於該嵌式控制器與一接地端之間;以及一第二電阻,耦接於一工作電壓與該固態硬碟介面之間。 A memory card device is suitable for use in a host, the host includes an embedded controller, a chip set, and a detecting circuit, the embedded controller is coupled to the chip set and the detecting circuit, the memory card device The method includes: a first control unit; a solid state hard disk interface coupled to the first control unit; and an identification circuit coupled to the solid state hard disk interface; wherein the solid state device is connected to the host, the solid state The hard disk interface is coupled to the embedded controller, the chip set and the detecting circuit, so that the detecting circuit generates a detecting voltage in response to the identifying circuit; and if the memory card device enters a power saving mode, and After a preset time After being awake for a predetermined number of times but still not receiving the use command, the chipset transmits a consistent energy signal to the solid state hard disk interface according to the detected voltage, so that the memory card device enters a full sleep mode; wherein the detecting circuit The method includes: a first resistor coupled between the embedded controller and a ground; and a second resistor coupled between an operating voltage and the solid state hard disk interface. 如申請專利範圍第6項所述之記憶卡裝置,其中該記憶卡裝置更包括:一第一記憶體單元,反應於該第一控制單元的控制而運作,其中該第一控制單元耦接於該固態硬碟介面的標準腳位;一第二控制單元,耦接該固態硬碟介面的標準腳位之外的保留腳位;以及一第二記憶體單元,反應於該第二控制單元的控制而運作。 The memory card device of claim 6, wherein the memory card device further comprises: a first memory unit, responsive to control of the first control unit, wherein the first control unit is coupled to a standard pin of the solid state hard disk interface; a second control unit coupled to the reserved pin other than the standard pin of the solid state hard disk interface; and a second memory unit responsive to the second control unit Control and operate. 如申請專利範圍第7項所述之記憶卡裝置,其中該第一記憶體單元與該第二記憶體單元相互做資料備份而形成一帶區集的磁碟。The memory card device of claim 7, wherein the first memory unit and the second memory unit back up each other to form a magnetic disk of a zone set.
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TW200818125A (en) * 2006-10-13 2008-04-16 Optimark Technology Co Ltd Power saving method for an external hard-disk
TW201015286A (en) * 2008-10-02 2010-04-16 Alcor Micro Corp Bridging device with power-saving function

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TW200818125A (en) * 2006-10-13 2008-04-16 Optimark Technology Co Ltd Power saving method for an external hard-disk
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