TWI502597B - A data inversion and reverting method of non-volatile memory - Google Patents

Description

Data inversion and recovery method for non-volatile memory

The invention relates to a fault masking method for non-volatile memory, in particular to a data inversion and recovery method for non-volatile memory using a compensation circuit to invert data to improve process yield.

Non-volatile memory is one of the most important types of semiconductor memory in the world. It is widely used in mobile computing products that require high performance and low power consumption. Its characteristic is that the stored content will not be stored after the power is turned off. It disappears, so the output value in the context of using it with a microcontroller and a digital processor is quite high. The non-volatile memory may include magnetoresistive random access memory (MRAM), read only memory (ROM), flash memory, phase change memory (PCM), and the like. Due to the increasing volume of information traffic, the transfer rate is also increasing, resulting in an increase in the memory capacity required. When manufacturing non-volatile memory, the yield of the entire product is often affected by the damage of the integrated circuit of the memory. In order to improve the production yield of memory products and reduce the production cost, the world-class manufacturers have developed a memory with repair function, which can be used when some of the memory cells of the main memory are damaged. Redundant memory is used for patching.

The conventional memory with repair function usually records the position of the damaged memory cells measured during the production test, and then fuses the fuses in a laser manner so that the entire column (or row) is reserved. Memory, the main memory that replaces the entire column (or row) of bit failures. Figure 1A shows an example of the use of alternate lines in accordance with the prior art. During memory array testing, it is often found that only one memory cell has defects. This defect can usually be divided into the case of fault model 1 or 0 (Stuck-at 1 or 0), that is, the data read by it is always 1 or 0. If faulty cell 101 is encountered in row 1, line 1 is considered to be the faulty line and mapped to spare row A, and this mapping is recorded in a certain way, and row 1 is no longer used. The fault line is typically indicated by blowing a fuse to record the mapping operation. When the original data is now sent to line 1, the data not sent to line 1 will be sent to the alternate line A due to the remapping operation. The replacement cell 102 is used to replace the faulty cell 101. In addition, it replaces all other non-faulty memory cells in row 1 with other cells in alternate row A.

FIG. 1B shows a simplified schematic diagram of one of the memory banks 200 for performing the alternate row shown in FIG. 1A. During the test, it will blow a fuse to indicate the location of the fault line. For each non-backup row of the memory array 221, there is a fuse. When the memory system 200 is booted, the fuse 220 is read into the control register 222, and thereby the location of the faulty line and its replacement of the alternate line can be indicated by the contents of the registers. When the host sends a memory access instruction, it compares the physical address to be accessed with the row address in control register 222. If the indication is a faulty line, it will be accessed to the alternate line instead of attempting to access the faulty line. Thus, control register 222 provides an alternate row address to address decoder 224 without accessing the failed line and thereby replacing multiple failed lines in a manner. In general, a plurality of spare lines 226 are provided to replace a plurality of fault lines. However, although the memory system 200 with the repair function has greatly improved the process stability, the proportion of the spare memory is still high, so that the volume is large and the application flexibility is not good, and the manufacturing process is Lower yields and higher costs.

It is an object of the present invention to provide a data inversion and recovery method for non-volatile memory that can reduce or eliminate redundant manufacturing mechanisms in non-volatile memory to reduce manufacturing costs.

Another object of the present invention is to provide a data inversion and recovery method for non-volatile memory, which utilizes the design of the variable compensation circuit to achieve fault tolerance and shadowing effects, thereby improving the process yield of the non-volatile memory. .

In order to achieve one or a part or all of the above or other purposes The present invention provides a data inversion and recovery method for non-volatile memory, which is applicable to a non-volatile memory array. The non-volatile memory array includes a fault bit, the fault bit is used to receive a data, and can only output a fixed value, and the data has an initial value. The data inversion and recovery method of the non-volatile memory includes: providing a first transformer and a second transformer, wherein the fault bit is electrically connected between the first transformer and the second transformer The first transformer writes the data into a fault bit after performing a first variable action, wherein the value of the data after the first variable action is converted into a fixed value; providing a control array, which is electrically charged Connected to the first transformer, after the control array records the first change action of the first transformer, the control array adds a first change event record; according to the data in the fault bit and the first change of the control array Complementing the event record, the second transformer performs a second variable action on the data in the fault bit, wherein the value of the data after the second change action is returned to the initial value.

In an embodiment, the step of providing a first transformer and a second transformer provides a first reverse circuit and a second reverse circuit, wherein the first reverse circuit is used to perform the first The complementing action is performed, and the second inverting circuit is used to perform the second variable action.

In one embodiment, the data inversion and recovery method of the non-volatile memory further includes: providing a built-in self-test circuit (BIST) electrically connected to the non-volatile memory array, the built-in self-test The circuit reads the contents of the non-volatile memory array to inspect the non-volatile memory array and generates a test data.

In one embodiment, the data inversion and recovery method of the non-volatile memory further includes: providing a multi-input feature shift register (MISR) electrically connected to the built-in self-test circuit and the non-volatile Between the memory arrays, after the built-in self-test circuit (BIST) checks the non-volatile memory array, the multi-input feature shift register compresses the checked test data and transmits it back to the built-in self-test circuit (BIST). In the comparison.

In an embodiment, the data inversion and recovery method of the non-volatile memory further includes: the control array provides a control signal end, the control signal end is connected to the second transformer, and the control signal terminal selectively reads the data. .

101‧‧‧Failed cells

102‧‧‧Replace cells

200‧‧‧ memory system

220‧‧‧Fuse

221‧‧‧ memory array

222‧‧‧Control register

224‧‧‧ address decoder

226‧‧‧ spare line

300‧‧‧Non-volatile memory array

310‧‧‧ Fault Bits

320‧‧‧Control array

330‧‧‧ spare memory array

340‧‧‧ Built-in self-test circuit

350‧‧‧Multiple Input Feature Displacement Register

410‧‧‧First Compensator

420‧‧‧Secondary

500‧‧‧Control signal end

Figure 1A is an example of the use of an alternate line of the prior art.

FIG. 1B is a memory system for performing the alternate line shown in FIG. 1A.

2 to 4 illustrate a data inversion and recovery method for a non-volatile memory according to an embodiment of the present invention.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. The directional terms mentioned in the following embodiments, such as upper, lower, left, right, front or rear, etc., are only used to refer to the directions of the accompanying drawings. Therefore, the directional terms are used for illustration only and are not intended to limit the invention.

2A and 2B are data inversion and recovery methods for non-volatile memory according to an embodiment of the present invention. The data inversion and recovery method for non-volatile memory is applicable to a non-volatile memory array 300. The non-volatile memory array 300 can include a fault bit 310 that is used to receive a data and can only output a fixed value that has an initial value that is not equal to the fixed value. For non-volatile memory, the data written is fixed and the data can be one-bit or one-tuple. Non-volatile memory data inversion and recovery methods include:

Step S110: A first transformer 410 and a second transformer 420 are provided. The fault bit 310 is electrically connected between the first transformer 410 and the second transformer 420. The first transformer The 410 system writes the data into the fault bit 310 after performing a first complementing operation, and the value of the data after the first patching operation is converted into a fixed value.

Step S120: A control array 320 is provided, which is electrically connected to the first patch 410. After the first patch 410 performs the first patching operation, the control array 320 adds a first patch event record. .

Step S130: The second patcher 420 records the fault bit 310 according to the data in the fault bit 310 and the first supplement event record of the control array 320. The data in the data performs a second change action, wherein the value of the data after the second change action is returned to the initial value.

In an embodiment, the step of providing the first transformer 410 and the second patch 420 in the data inversion and recovery method of the non-volatile memory provides a first reverse circuit and a second reverse The circuit, that is, the first transformer 410 and the second transformer 420, can all be an inverter, the first reverse circuit is used for the first variable action, and the second reverse circuit is Used to perform the second variable action. The fault bit 310 can only output a fixed value of, for example, 1 and the value of the data is 0. If the data is directly written into the fault bit 310, the non-volatile memory array 300 is faulty and cannot be used. . Therefore, in conjunction with the data inversion and recovery method of the non-volatile memory of the present invention, the first transformer 410 can change the value of the data to 1 after performing a reverse operation on the data, and then The fault bit 310 is written to shield the fault so that the non-volatile memory array 300 can continue to be used. At the same time, the control array 320 records the reverse operation of the first transformer 410. Before the data is read out, the control array 320 displays that the data has been reversed, so the data needs to pass through the second transformer. 420, and reverse the operation again to return to the value of 0. In this embodiment, the data is not changed, and only the value of the data is used for the conversion operation.

In an embodiment, the first transformer 410 and the second transformer 420 may also be a mutually exclusive or (XOR) logic gate. When the initial value of the data is the same as the fixed value of the fault bit 310, the first The patcher 410 can optionally write directly without performing a reverse operation. Referring to FIG. 4A at the same time, the control array 320 provides a control signal terminal 530, the control signal terminal 530 is connected to the second transformer 420, and can selectively read data, if it is determined that the data has not been reversed, Read.

As shown in FIG. 3, it is a data inversion and recovery method for non-volatile memory according to an embodiment of the present invention. In the non-volatile memory array 300, C6R0, C4R1, C2R3, C0R4, C4R5 and C7R7 all include fault bits 310, and CB0~CB7 are control arrays 320, 330a and 330b are spare memory arrays. Displaying "0" in the control array 320 means that the data to be written to the column does not need to be reversed. The non-volatile memory array 300 can be directly written, and the display of "1" means that the data to be written to the column has been inverted to be written into the non-volatile memory array 300. 3 shows that C4R1, C0R4, C4R5, and C7R7 contain the fail bit 310, but when the value of the data to be written to the column is the same as the fixed value of the fault bit 310, the non-volatile is directly written without the reverse operation. The fault is also not caused in the memory array 300, so the relative control array 320 is shown as "0".

Continuing to refer to FIG. 3, although 99% of the faults in the non-volatile memory have been masked in the above embodiment, when the faulty bit 310 in the non-volatile memory array 300 is excessive, and the non-volatile memory When the entire column or the entire row is not obscured by the reverse operation, the data inversion and recovery method of the non-volatile memory provides the spare memory arrays 330a, 330b to replace the entire row or the entire column of non-volatile memory. . However, under the mechanism of the data inversion and recovery method of the non-volatile memory of the present invention, the use of the spare memory can be greatly reduced, thereby reducing the manufacturing cost of the non-volatile memory.

4A and 4B are a data inversion and recovery method for non-volatile memory according to an embodiment of the present invention, which further includes the following steps:

Step S140: providing a Built-in Self-Test (BIST) 340 electrically connected to the non-volatile memory array 300, and the built-in self-test circuit 340 can read the non-volatile memory The contents of array 300 are used to inspect non-volatile memory array 300 and generate a test data.

Step S150: providing a multiple input feature shift register (MISR) 350 electrically connected between the built-in self-test circuit 340 and the non-volatile memory array 300, and built-in self-test After the circuit (BIST) and the non-volatile memory array are inspected, the multi-input feature shift register 350 compresses the read data and transmits it back to the built-in self-test circuit (BIST) 340 for comparison.

In this embodiment, the data inversion and recovery method of the non-volatile memory of the present invention can integrate the built-in self-test circuit 340 so that the non-volatile memory can be self-tested to reduce labor consumption, and the multi-input feature displacement is temporarily suspended. Saver 350 Used to compress the data used for inspection to reduce the memory space.

However, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention. All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

300‧‧‧Non-volatile memory array

310‧‧‧ Fault Bits

320‧‧‧Control array

410‧‧‧First Compensator

420‧‧‧Secondary

Claims (6)

A non-volatile memory data inversion and recovery method, the non-volatile memory array includes a fault bit, the fault bit is used to receive a data, and can only output a fixed value, wherein the data has a The initial value, the non-volatile memory data inversion and recovery method includes: providing a first transformer and a second transformer, the fault bit is electrically connected to the first transformer and the first Between the two transformers; the first transformer writes the data to the fault bit after performing a first variable action, wherein the value of the data after the first variable action is converted For the fixed value, a control array is provided, the control array is electrically connected to the first transformer, and the control array adds a first after the first patching operation of the first transformer Compensating the event record; and when the data is to be accessed from the fault bit, the second patcher is based on the data in the fault bit and the first supplement event record of the control array, And the second change in the data in the fault bit For which the value of data after performing the operation of this second variant complement, will return for an initial value. The data inversion and recovery method of the non-volatile memory according to claim 1, wherein the first transformer and the second transformer are respectively a first reverse circuit and a second The reverse circuit, wherein the first reverse circuit is configured to perform the first variable action, and the second reverse circuit is configured to perform the second variable action. The data inversion and recovery method of the non-volatile memory according to claim 1, wherein the first transformer and the second transformer are a mutually exclusive or (XOR) logic gate. The data inversion and recovery method of the non-volatile memory according to claim 1 further includes: providing a built-in self-test circuit (BIST) electrically connected to the non-volatile memory array, The built-in self-test circuit reads the contents of the non-volatile memory array to inspect the non-volatile memory array and generate a test capital material. The data inversion and recovery method of the non-volatile memory according to claim 4 of the patent application scope further includes: providing a multi-input feature displacement register (MISR) electrically connected to the built-in self-test Between the circuit and the non-volatile memory array, after the built-in self-test circuit (BIST) checks the non-volatile memory array, the multi-input feature shift register compresses the test data and transmits it back to the inside. Build a self-test circuit (BIST) for comparison. The data inversion and recovery method of the non-volatile memory according to claim 1 further includes: the control array provides a control signal end, and the control signal end is connected to the second transformer and selects Sexually read the information.