TWI502353B - Core logic circuit, computer system and method for initializing peripheral device - Google Patents

Description

Core logic circuit, computer system and peripheral device initialization method

The case is a core logic circuit and a peripheral device initialization method, especially a core logic circuit and a peripheral device initialization method applied in a computer system.

In the conventional technical means, a peripheral component interconnect bus (Peripheral Component Interconnect bus (hereinafter referred to as PCI bus) is a bus bar that is commonly used when peripheral components are connected to a computer system, and a plurality of PCI slots or interfaces are usually provided on the motherboard to allow The system builder uses the peripheral device add-on card (PCI card) for connecting the peripheral components of the network card, the sound card, and the like on the computer system. In order to allow peripheral components to be added to the computer system before the operation system has been loaded, the manufacturer of the peripheral component add-on card usually provides the corresponding initialization code to store. Up to PCI expansion read-only memory (PCI Expansion ROM, or PCI option ROM).

The PCI extended read-only memory is initially disposed on the peripheral component add-on card, but in order to save cost, the PCI extended read-only memory may be omitted and the initialization code (initialization code may also be used). The PCI option ROM code is stored in the read-only memory of the computer system for storing the basic input/output system (BIOS). Therefore, the manufacturer of the peripheral component add-on card must first provide the PCI select read-only memory code to the manufacturer of the motherboard for writing to the read-only memory on the motherboard together with the basic input/output system (BIOS). When the basic input/output system is loaded, the PCI selects the read-only memory code to complete the initialization of the peripheral component add-on card. After the initialization is completed, the peripheral component add-on card can operate to realize a certain function before the operating system has been loaded. For example, the peripheral component add-on card is a PCI network card (PCI LAN card), then the PCI network The road card can implement the function of remote booting system (remote boot).

However, in recent years, many new peripheral component interfaces have been developed, such as Universal Serial Bus (USB), Secure Digital Input/Output (SDIO), and Universal Non-Synchronous Receiver Transmit Bus (UART). The peripheral components of the transmission interface may be replaced by a new interface to the computer system. However, the initialization code of the new peripheral component interface can only be loaded when the operating system is loaded, resulting in such peripheral components not working properly on the computer system in which the operating system is not loaded, resulting in users. Troubled. How to improve the lack of the above-mentioned conventional technical means is the main purpose of developing the case.

The present invention is a core logic circuit applied to a computer system having a basic input/output system and a bus bar, the core logic circuit comprising: a first bus bar controller electrically connected to the first peripheral device; and a first virtual bus bar a controller electrically connected to the bus bar, having a first peripheral device identification code, and when the computer system configures the bus bar, the computer system correspondingly finds the basic input/output system according to the first peripheral device identification code The first initialization code is executed, and then the first initialization code is executed to complete initialization of the first peripheral device.

Another aspect of the present invention is a computer system comprising a basic input/output system, a bus bar and a first peripheral device, the first peripheral device is not electrically connected to the bus bar, and the computer system further comprises: a first bus bar a controller electrically connected to the first peripheral device; and a first virtual busbar controller electrically connected to the busbar having a first peripheral device identification code, and when the computer system configures the busbar The computer system correspondingly finds the first initialization code in the basic input/output system according to the first peripheral device identification code, and then executes the first initialization code to complete initialization of the first peripheral device.

A further aspect of the present invention is a peripheral device initialization method for a computer system having a basic input/output system and a bus bar, wherein the first bus bar controller of the computer system is electrically connected to the first peripheral device of the computer system, The initialization method includes the following steps: performing a basic input/output system loading program; and correspondingly finding the basic input/output system according to the first peripheral device identification code in the first virtual busbar controller electrically connected to the busbar in the computer system a first initialization code; and executing the first initialization code to complete initialization of the first peripheral device.

Please refer to the first figure (a), which is a functional block diagram of a preferred embodiment of a computer system developed in the present invention for improving the lack of conventional means. The computer system 1 mainly includes a central processing unit 10 and a core logic circuit 11 And the read-only memory 12 storing the basic input/output system code 120, wherein the core logic circuit 11 is generally composed of a north bridge module 111 and a south bridge module 112, and the south bridge module 112 is provided with a first A universal serial controller (USB controller) 1121 and a second universal serial controller (USB controller) 1122 are connected to the first peripheral device 191 and a second peripheral device 192. Here, the first and second universal serial bus controllers 1121 and 1122 are merely illustrative, and the first and second peripheral devices 191 and 192 may also be peripheral devices of other transmission interfaces, such as a secure digital input/output (SDIO) bus. Or a universal non-synchronous receiver transmission bus (UART) or the like, and the first universal serial bus controller 1121 and the second universal serial bus controller 1122 may also be different transmission interfaces, where the universal serial bus (USB) is just an example, but is not limited to this.

Since the universal serial bus in the conventional technology can only be initialized on the computer system after the operating system is loaded, the universal serial bus interface is used as the first peripheral device 191 and a second peripheral device of the connection interface. 192 will not function properly until the operating system is loaded. In order to improve these defects, the case is connected to the core logic circuit 11 (in this example, in the south bridge module 112, of course, the north bridge module 111), and the connection to the peripheral component busbar (PCI bus) is added. A plurality of virtual peripheral components of the 18 are connected to a PCI bus controller, and two are listed in this example, respectively, and the first virtual peripheral component is connected to the busbar controller 181 and the second virtual peripheral component. Row controller 182. The connection of the busbar controllers in the virtual peripheral components does not require an actual controller circuit structure, and only the register groups 1810 and 1820 for reading and writing are required, and the register groups can be It is written into an identification code representing the first peripheral device 191 and the second peripheral device 192, such as a Vendor ID and a device ID, and a class code, and the like. The first initialization code 1201 and the second initialization code 1202 of the peripheral device 191 and the second peripheral device 192 are placed in the basic input/output system code 120. In an embodiment of the invention, the register groups 1810, 1820 of the virtual peripheral components connected to the bus controllers 181 and 182 are located in the configurable space in the virtual peripheral components connecting the bus controllers 181 and 182. Within the configuration space header, the register sets 1810, 1820 can be set to be writable on the back door.

As shown in the first figure (b), it is the format of the first initialization code 1201 and the second initialization code 1202 in the basic input/output system code 120 of the present case, wherein the first initialization code 1201 is a first The header 12010 is composed of a first PCI extended ROM code ROM 12011. The second initialization code 1202 is a second header 12020 and a second PCI extended read-only memory code 12021. The composition, wherein the contents of the headers 12010 and 12020 will correspond to the identification codes written in the register groups 1810, 1820. In an embodiment of the present invention, the first initialization code 1201 and the second initialization code 1202 are provided by the manufacturer of the first peripheral device 191 and the second peripheral device 192, wherein the contents of the headers 12010 and 12020 include The identification codes representing the first peripheral device 191 and the second peripheral device 192, such as a Vendor ID and a device ID, a class code, and the like. Therefore, the identification codes provided by the peripheral device manufacturer are respectively written in the first virtual peripheral component connection busbar controller 181 and the second virtual peripheral component connection busbar controller 182 in the register group 1810, 1820. The contents of the register sets 1810, 1820 are made to correspond to the contents of the headers 12010 and 12020.

Since the basic input/output system code 120 is loaded after the computer system starts to execute the power-on self-test program (POST), the basic input/output system scans one by one according to the specifications of the peripheral bus connection configuration (PCI bus configuration). The peripheral device is connected to the peripheral device connected to the bus bus, and the corresponding initialization code is found in the basic input/output system code 120 according to the identification code of the peripheral device to complete the initialization of the peripheral devices. Therefore, please refer to the second figure, which is a flow chart of the initialization method that can be run in the above peripheral device. First, when the basic input/output system is loaded (step 21), the peripheral component connection confluence is performed by the way. The PCI bus configuration program is used to configure the bus bar (step 22) to determine whether to connect the bus bar controller to any peripheral components in the peripheral bus (PCI bus). Bus controller) (step 23), if not, directly complete the loading of the basic input and output system (step 24), and enter the loading of the operating system (step 25), and if it is scanned into the peripheral components When one of the identification codes of the PCI bus controller is connected, the initialization code corresponding to the identification code can be found in the basic input/output system code. For example, the basic input/output system can be scanned and checked. Whether the initialization code in the basic input/output system (for example, the first initialization code 1201 and the second initialization code 1202 in the first figure (a)) includes the identification a code, if yes, the initialization code is associated with the connection bus controller in the virtual peripheral component (step 26), and the initialization code is executed to successfully identify the code corresponding to the initialization code but is connected to the other The peripheral device on the busbar (e.g., the first peripheral device 191 in the first diagram (a)) is initialized (step 27) so that it can operate normally before the operating system is loaded. For example, since the first virtual peripheral component (PCI bus controller) 181 in the first figure (a) is hung on the peripheral bus (PCI bus) 18, the first virtual periphery The in-component connection bus controller 181 is scanned when the peripheral bus connection configuration (PCI bus configuration) program is executed in steps 22 and 23; when the step 26 is executed, the first virtual is checked in the basic input/output system. The identification code in the register group 1810 of the peripheral component connected to the bus controller 181 is equal to the identification code in the first header 12010 of the first initialization code 1201, and then step 27 is executed to execute the first initialization code. 1201 initializes the first peripheral device 191. Similarly, the second virtual peripheral component connection bus controller 182 is also scanned when the peripheral bus bus configuration program is executed, and the second initialization program corresponding to the identification code is executed. Code 1202 initializes the second peripheral device 192.

As can be seen from the above description, in this case, only the register group is added to the core logic circuit 11, and the identification codes such as the Vendor ID, the device ID, and the class code are written. A peripheral function PCI function can be generated as a virtual peripheral component internal connection bus controller for simulating the connection to the other peripheral device 191 or the second peripheral device 192 on the other bus bar, due to the virtual The peripheral component connection busbar controller can be scanned when the peripheral bus component configuration (PCI bus configuration) program is executed, so that the first peripheral device 191 or the second peripheral device 192 is connected to the system. In turn, the first peripheral device 191 or the second peripheral device 192 is successfully initialized, and the register groups in the virtual peripheral components connected to the bus controller are normally read-only, but through a The setting of the back door register, for example, is changed from 0 to 1, and these register groups are converted to write, which allows the engineer to configure these temporary Container group.

For example, the network card is originally connected to the busbar as a transmission interface in the peripheral component. Even if the universal serial busbar is used as the transmission interface to save the pin, according to the technical means of the present case, the manufacturer only needs to be at the core. In the logic circuit 11, a PCI bus controller corresponding to one of the virtual peripheral components of the network card is added to the connection bus bar 18 in the peripheral component, wherein the write represents the network card identification. The code register can be used. In this way, through the technical means of this case, the motherboard manufacturer can make the peripheral devices such as the network card operate normally before the operation system is loaded without greatly changing the design, thereby effectively improving the conventional means. Missing. The technical means of this case does not limit the number of peripheral devices. If there are multiple peripheral devices that need to be initialized before entering the operating system, that is, you need to select the option ROM code function, you only need to provide multiple virtual peripheral components to connect to the bus controller. Features.

In addition to the general-purpose serial bus, other peripheral components, such as secure digital input/output (SDIO) bus or universal non-synchronous receiver transmission bus (UART), can also be used to complete the peripheral components. Initialization, and peripheral devices can be various peripheral components such as network cards and sound effects cards. Therefore, this case can effectively improve the lack of the above-mentioned conventional technical means and achieve the main purpose of developing the case. However, the invention of the present invention is modified by those skilled in the art, and is not intended to be protected by the scope of the patent application.

The components included in the diagram of this case are listed as follows:

1. . . computer system

10. . . Central processing unit

11. . . Core logic circuit

12. . . Read only memory

111. . . North Bridge Module

112. . . South Bridge Module

120. . . Basic input and output system code

1121. . . First universal serial bus controller

1122. . . Second universal serial bus controller

191. . . First peripheral device

192. . . Second peripheral device

18. . . Connected busbars in peripheral components

181. . . a first virtual peripheral component connected to the busbar controller

182. . . a second virtual peripheral component connected to the busbar controller

1810, 1820. . . Scratchpad group

1201. . . First initialization code

1202. . . Second initialization code

12010. . . First header

12011. . . First PCI expansion read-only memory code

12020. . . Second header

12021. . . Second PCI expansion read-only memory code

The case can be further understood by the following diagrams and explanations:

The first figure (a) is a functional block diagram of a preferred embodiment of a computer system developed in the present case to improve the lack of conventional means.

The first figure (b) is a schematic diagram of the format of the first initialization code and the second initialization code in the basic input/output system code of the present case.

The second figure is a flow chart of an initialization method that can be run in the above-mentioned peripheral device.

Claims (29)

A core logic circuit is applied to a computer system having a basic input/output system and a bus bar, the core logic circuit comprising: a first bus bar controller electrically connected to a first peripheral device; and a first a virtual busbar controller electrically connected to the busbar having a first peripheral device identification code, and when the computer system configures the busbar, the computer system correspondingly finds the first peripheral device identification code The first initialization code in the basic input/output system, and then the first initialization code is executed to complete the initialization of the first peripheral device, wherein the initialization of the first peripheral device is performed before the loading of the operating system. The core logic circuit of claim 1, wherein the first bus controller has a different transmission interface specification than the bus. The core logic circuit of claim 1, wherein the first bus controller can be a universal serial bus controller, a secure digital input/output bus controller, or a universal asynchronous receiver. Bus controller. The core logic circuit of claim 1, wherein the transmission interface specification of the bus bar is a connection bus bar specification in the peripheral component. The core logic circuit of claim 1, wherein the first virtual bus controller comprises a virtual peripheral component connection bus controller including a register group, the register group storing the The first peripheral device identification code. The core logic circuit as described in claim 5, wherein the A peripheral device identification code includes a manufacturer identification code representing one of the first peripheral devices, a component identification code, and a category code. The core logic circuit of claim 5, wherein the first initialization code in the basic input/output system comprises: a first header, the first peripheral device identification code; and corresponding One of the first peripheral devices first expands the read-only memory code. The core logic circuit of claim 5, wherein the register group is preset to be read only, and the register group is converted to be writable by a setting of a backdoor register. The core logic circuit of claim 1, further comprising: a second busbar controller electrically connected to a second peripheral device; and a second virtual busbar controller electrically connected to the confluence a row having a second peripheral device identification code, and when the computer system configures the bus bar, the computer system correspondingly finds a second initialization program in the basic input/output system according to the second peripheral device identification code And executing the second initialization code to complete initialization of the second peripheral device, wherein the initialization of the second peripheral device is performed before the operating system is loaded. The core logic circuit of claim 9, wherein the second initialization code in the basic input/output system comprises: a second header, the second peripheral device identification code; and corresponding One of the second peripheral devices is a second extended read-only memory code. A computer system comprising a basic input/output system, a bus bar and a first peripheral device, the first peripheral device is not electrically connected to the bus bar, the computer system further comprising: a first bus bar controller, Electrically connected to the first peripheral device; and a first virtual busbar controller electrically connected to the busbar having a first peripheral device identification code, and when the computer system configures the busbar, the computer The system correspondingly finds a first initialization code in the basic input/output system according to the first peripheral device identification code, and then executes the first initialization code to complete initialization of the first peripheral device, wherein the first peripheral device The initialization is performed before the operating system is loaded. The computer system of claim 11, wherein the first bus controller has a different transmission interface specification than the bus. The computer system of claim 11, wherein the first bus controller can be a universal serial bus controller, a secure digital input/output bus controller, or a universal asynchronous receiver. Row controller. The computer system according to claim 11, wherein the transmission interface specification of the busbar is a connection busbar specification in the peripheral component. The computer system of claim 11, wherein the first virtual busbar controller comprises a virtual peripheral component connection busbar controller including a register group, the register group storing the first A peripheral device identification code. The computer system of claim 15, wherein the first peripheral device identification code comprises a vendor identification representative of the first peripheral device A code, a component identification code, and a class code. The computer system of claim 15, wherein the first initialization code in the basic input/output system comprises: a first header, the first peripheral device identification code; and a corresponding One of the peripheral devices first expands the read-only memory code. The computer system of claim 15, wherein the register group is preset to be read only, and the register group is converted to be writable by a setting of a back door register. The computer system of claim 11, further comprising: a second busbar controller electrically connected to a second peripheral device; and a second virtual busbar controller electrically connected to the busbar The system has a second peripheral device identification code, and when the computer system configures the bus bar, the computer system correspondingly finds a second initialization code in the basic input/output system according to the second peripheral device identification code. And executing the second initialization code to complete initialization of the second peripheral device, wherein the initialization of the second peripheral device is performed before the operating system is loaded. The computer system of claim 19, wherein the second initialization code in the basic input/output system comprises: a second header, the second peripheral device identification code; and a corresponding One of the two peripheral devices is a second extended read-only memory code. A peripheral device initialization method is applied to a computer system having a basic input/output system and a bus bar, and a first confluence in the computer system The row controller is electrically connected to a first peripheral device of the computer system, and the initialization method comprises the steps of: performing a basic input/output system loading program; and electrically connecting to the first virtual sink of the bus bar according to the computer system Corresponding to one of the first peripheral device identification codes in the row controller, corresponding to finding a first initialization code in the basic input/output system; and executing the first initialization code to complete initialization of the first peripheral device, wherein the first The initialization of a peripheral device is performed before the operating system is loaded. The method for initializing a peripheral device according to claim 21, wherein the first bus bar controller and the bus bar are different in transmission interface specifications. The method for initializing a peripheral device according to claim 21, wherein the first busbar controller is applied to a universal serial bus controller, a secure digital input/output bus controller, or a universal The asynchronous receiver transmits the bus controller. The peripheral device initialization method according to claim 21, wherein the transmission interface specification of the bus bar is a connection bus bar specification in the peripheral component. The method for initializing a peripheral device according to claim 21, wherein the first virtual bus controller is configured to include a register group, wherein the register group stores the first peripheral device identification code. . The method for initializing a peripheral device according to claim 25, wherein the first peripheral device identification code comprises a manufacturer identification code representing one of the first peripheral devices, a component identification code, and a category code. The method for initializing a peripheral device according to claim 21, further comprising: performing a bus configuration program to scan the first peripheral device identification code on the bus bar. The method for initializing a peripheral device according to claim 21, wherein the step of finding the first initialization code in the basic input/output system further comprises: scanning the basic input/output system; and checking the first initialization program. Whether the first peripheral device identification code is included in one of the code headers. The method for initializing a peripheral device according to claim 21, wherein a second busbar controller in the computer system is electrically connected to a second peripheral device of the computer system, the initialization method further comprises: according to the computer system Electrically connecting to one of the second virtual bus controllers of the bus bar and corresponding to finding a second initialization code in the basic input/output system; and executing the second initialization code The initialization of the second peripheral device is completed, wherein the initialization of the second peripheral device is performed before the loading of the operating system.