TWI502333B - Heterogeneous multiprocessor design for power-efficient and area-efficient computing - Google Patents

Description

Heterogeneous multiprocessor design for power savings and area savings calculations

The present invention relates generally to multiprocessor computer systems and, more particularly, to a heterogeneous multiprocessor design for power saving and area saving calculations.

Battery-powered mobile computing platforms have become increasingly important in recent years, thereby increasing the need for efficient, low-power systems that enable highly scalable computing at low cost. A typical mobile device may need to operate in a wide range of performance depending on workload requirements. Different performance ranges are known to be different operating modes, and power consumption is proportionally related to performance within a given mode of operation. In low power sleep mode, the mobile device can provide a small amount of computing power, for example, to maintain radio contact with the cellular base station. In active mode, the mobile device can provide a low latency response to user input, for example, through a window manager. Many of the operations associated with a typical application are performed with satisfactory performance in an active mode. In the high-performance mode, the mobile device needs to provide peak computing capabilities, for example, to perform an instant game or to implement a short user interface operation. Active mode and high performance mode typically require ever-increasing power consumption.

Several techniques have been developed to improve the performance and power efficiency of mobile devices. Such techniques include reducing device parasitic loading, reducing operating voltage and threshold voltage, reducing power efficiency with efficiency, and adding different circuit configurations that are tailored to operate well in a particular mode of operation by reducing device size.

In one example, the mobile device processor complex includes a low power low performance processor and a high performance high power processor. In the idle and low-active active mode, the low-power processor is more power-efficient at lower performance levels, so it is selected for execution; in high-performance mode, the high-performance processor is more power efficient, so Selected to perform a larger workload. herein In the case, the swap space includes the cost component because the mobile device carries the cost burden of two processors, and only one processor at a time has an effect. When this processor complex enables low power operation and high efficiency operation, the processor complex uses expensive resources in an inefficient manner.

As explained earlier, there is a need in the art for a more efficient technique to accommodate a wide range of different workloads.

An embodiment of the present invention provides a method for configuring one or more cores in a processing unit to perform different workloads, the method comprising: receiving information related to a new workload; determining the basis based on the information The new workload is different from the current workload; based on the information, it is determined how many of the one or more cores should be configured to execute the new workload; how many of the one or more cores Should be configured to perform this new workload as a basis to determine if a new core configuration is required; and if a new core configuration is required, then the processing unit is converted to the new core configuration, or if a new core configuration is not required Then, then keep the current core configuration to perform the new workload.

Other embodiments of the invention include, but are not limited to, a computer readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to perform the techniques described herein; and a computing device It includes a processing unit configured to implement the techniques described herein.

One advantage of the disclosed technology is that it can advantageously improve the power efficiency of a multi-core central processing unit over a wide range of workloads while efficiently utilizing processing resources.

100‧‧‧ computer system

102‧‧‧Central Processing Unit

104‧‧‧System Memory

105‧‧‧Memory Bridge

106‧‧‧Communication path

107‧‧‧Input/Output (I/O) Bridge

108‧‧‧User input device

110‧‧‧ display device

112‧‧‧Parallel Processing Subsystem

113‧‧‧Second communication path

114‧‧‧System Disc

116‧‧‧Switcher

118‧‧‧Network Adapter

120‧‧‧Extension card

140(0)‧‧‧First Processor Core/Low Power Core

140(N)‧‧‧Second Processor Core/High Performance Core

150‧‧‧Operating system core

152‧‧‧ Scheduler

154‧‧‧ device driver

156‧‧‧ device driver

210(0)‧‧‧VF domain

210(N)‧‧‧VF domain

212‧‧‧Programmable virtual identifier (ID)

212(0)‧‧‧Unspecified

212(N)‧‧‧Unspecified

220‧‧‧core interconnects

222‧‧‧ cache

224‧‧‧ memory interface

226‧‧‧ interrupt distributor

230‧‧‧ Cluster Control Unit

310‧‧‧ total throughput

312‧‧‧ Power

314‧‧‧Maximum total throughput of low power core 140(0)

316‧‧‧Maximum total throughput of high performance core 140(N)

320‧‧‧Power curve

322‧‧‧Power curve

324‧‧‧Power curve

330‧‧‧Low power core area

332‧‧‧High-performance core area

334‧‧‧Double core area

400‧‧‧ method

410-490‧‧‧Steps

The invention has been described in detail with reference to the preferred embodiments of the invention, However, the present invention is intended to be limited only by the exemplary embodiments of the invention.

The first diagram is a block diagram of a computer system configured to perform one or more aspects of the present invention; 2 is a block diagram of a central processing unit (CPU) of a computer system according to a first embodiment of the present invention; and the third diagram is included according to an embodiment of the present invention. The different operating areas of the multi-core CPU; and the fourth diagram is a flow diagram of method steps for configuring a CPU including multiple cores to operate in a power saving zone, in accordance with an embodiment of the present invention.

In the following description, numerous specific details are set forth in order to provide a better understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of the precise details.

System Overview

The first figure is a block diagram of a computer system 100 configured to perform one or more aspects of the present invention. The computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 that communicate via an interconnection path, which may include a memory bridge 105. The memory bridge 105 (for example, a north bridge wafer) may be connected to an input/output (I/O, Input/output) via a bus or other communication path 106 (for example, a HyperTransport link). Bridge 107. For example, I/O bridge 107 may be a south bridge wafer that receives user input and communicates from one or more user input devices 108 (eg, keyboard, indicator device, capacitive touch panel) Path 106 and memory bridge 105 pass the input forward to CPU 102. A parallel processing subsystem 112 is coupled to the memory bridge through a bus or second communication path 113 (for example, a Peripheral Component Interconnect (PCI), an accelerated graphics port, or a HyperTransport link). 105. In one embodiment, the parallel processing subsystem 112 is a graphics subsystem that transmits pixels to a display device 110. The display device 110 may be any conventional cathode ray tube, liquid crystal display, light emitting diode display, or the like. Things. A system disk 114 is also coupled to an I/O bridge 107 and may be configured to store content and applications and materials for use by the CPU 102 and the parallel processing subsystem 112. System Disk 114 is used for non-volatile storage of applications and data, and may include fixed or removable hard drives, fast Flash memory device and CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Video Disc Read Only Memory), Blu-ray, high-definition DVD (HD- DVD, High Definition DVD) or other magnetic, optical or solid state storage devices.

A switch 116 provides a connection between the I/O bridge 107 and other devices (e.g., network one adapter 118 and various add-in cards 120). Other devices (not explicitly shown) (including Universal Serial Bus (USB) or other ports, CD (Compact Disc), Digital Versatile Disc (DVD), Video recording devices and the like may also be connected to the I/O bridge 107. The various communication paths shown in the first figure (including communication paths 106 and 113 with well-defined names) can be implemented using any suitable protocol, such as PCI Express, Accelerated Graphics Port (AGP), HyperTransport, or any Other bus or point-to-point communication protocols, and connections between different devices may use different protocols known in the art.

In one embodiment, parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the parallel processing subsystem 112 will incorporate circuitry optimized for general purpose processing while preserving the basic computing architecture, as described in more detail herein. Moreover, in another embodiment, the parallel processing subsystem 112 may be integrated with one or more other system components in a single subsystem, for example, in conjunction with the memory bridge 105, the CPU 102, and the I/O bridge 107. A system on chip (SoC) is formed.

It should be understood that the systems shown herein are illustrative and can be modified and modified. The connection topology (including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112) can be modified as desired. For example, in some embodiments, system memory 104 is directly connected to CPU 102 rather than via a bridge; while other devices are coupled to system memory 104 via memory bridge 105 and CPU 102. communication. In other alternative topologies, the parallel processing subsystem 112 is connected to the I/O bridge 107 or directly to the CPU 102 rather than being connected to the memory bridge 105 connector. Again, in other embodiments, I/O bridge 107 and memory bridge 105 can be integrated into a single wafer rather than one or more discrete devices. Most A sub-embodiment may include two or more CPUs 102 and two or more parallel processing subsystems 112. The particular devices shown herein are non-essential; for example, any number of add-in cards or peripheral devices can be supported. In some embodiments, the switch 116 is eliminated and the network adapter 118 and the add-in card 120 are directly connected to the I/O bridge 107. Also, in other embodiments, computer system 100 includes a mobile device and network adapter 118 implements a digital wireless communication subsystem. In these embodiments, the input device 108 includes a touch panel subsystem, and the display device 110 implements a mobile screen subsystem, such as a liquid crystal display module.

The CPU 102 includes at least two processor cores 140(0), 140(N). A first processor core 140(0) is designed for low power operation; and a second processor core 140(N) is designed for high efficiency operation. In one embodiment, a symmetrical number of low power processor cores and high performance processor cores are implemented within CPU 102. A work system core 150 resident in system memory 104 includes a scheduler 152 and device drivers 154, 156. The core 150 is configured to provide a particular known core service, including services related to processing and thread management. Scheduler 152 is configured to manage thread and process assignment jobs assigned to different processor cores 140 within CPU 102. Device driver 154 is configured to manage which processor core 140 is to be enabled for use and which is disabled, for example, by powering down. Device driver 156 is configured to manage parallel processing subsystem 112, including processing and buffering commands and input data strings to be processed.

Heterogeneous multiprocessor

The second figure shows a block diagram of a CPU 102 of a computer system 100 in accordance with a first embodiment of an embodiment of the present invention. As shown, the CPU 102 includes at least two cores 140(0), 140(N), a core interconnect 220, a cache 222, a memory interface 224, an interrupt distributor 226, and a cluster control unit. 230.

Each core 140 is operable within a corresponding Voltage-Frequency (VF) domain, unlike other VF domains. For example, circuitry associated with core 140(0) can operate at a first voltage and a first operating frequency associated with VF domain 210(0); circuitry associated with core 140(N) The system is operable at a second voltage and a second operating frequency associated with the VF domain 210(N). In this example, each voltage and each frequency can be independently varied within a technically feasible range to achieve specific power and performance goals.

In this example, core 140(0) is designed for low power operation; core 140(N) is designed for high performance operation while preserving the compatibility of each other's Instruction Set Architecture (ISA). . The core 140(N) can be compared to any applicable technology (eg, circuit design for high clock speeds, logic design for simultaneous delivery and processing of multiple simultaneous instructions, and architectural design for improved cache size and performance) high efficiency. The design offset associated with core 140(0) can tolerate high marginal power consumption to achieve greater marginal performance. Core 140(0) can achieve lower power operation through circuit design for reducing leakage current, crossbar current, parasitic losses, and logic design for reducing switching energy associated with processing an instruction. Design offsets associated with core 140(0) should generally be preferred to reduce power consumption, even sacrificing clock speed and processing performance.

Each core 140(0), 140(N) includes a programmable virtual identifier (ID) 212(0), 212(N) that identifies the processor core. Each core 140(0), 140(N) can be programmed with an arbitrary core identifier through virtual IDs 212(0), 212(N), which may be reserved with scheduler 152. Special threads or processes are associated. Each core 140 may include logic to facilitate copying an internal execution state to another core 140.

In one embodiment, core interconnect 220 couples core 140 to a cache 222, which is further coupled to a memory interface 224. Core interconnects 220 can be configured to facilitate state replication between cores 140. The interrupt dispatcher 226 is configured to receive an interrupt signal and transmit the interrupt signal to a suitable core 140 identified by the programmed value in the virtual ID 212. For example, a core zero-targeted interrupt will be sent to a core 140 whose virtual ID 212 is programmed to zero.

The cluster control unit 230 manages the available state of each of the cores 140, and each of the cores 140 can be individually hot-plugged to become available or hot-drawn to become unusable. Before the hot swapping of a given core, the cluster control unit 230 may have the execution state of the core copied to another core for continued execution. For example, if execution should transition from a low power core to a high performance core, the execution state of the low power core may be copied to the high performance core before the high performance core begins execution. Execution status is proprietary and may include, but is not limited to, scratchpad data, translation buffer data, and cache status.

In one embodiment, the cluster control unit 230 is configured to turn off one or more voltage supplies of the core that have been hot extracted and turn on one or more voltage supplies of the core that have been hot plugged. For example, the cluster control unit 230 may turn off the voltage supply associated with the VF domain 210(0) to hot pull out the core 140(0). The cluster control unit 230 may also perform frequency control circuitry for each core 140. The cluster control unit 230 receives commands from a cluster switcher software module resident in the device driver 154. The cluster switcher manages the transition between core configurations. For example, the cluster switch can instruct each core to hold the text (including the virtual ID 212) and load a saved text (including any virtual ID 212). The cluster switcher may include hardware support for saving and loading the text through the cluster control unit 230. Control unit 230 can provide automatic detection of workload changes and indicate to the cluster switch that a new workload requires a new configuration. The cluster switcher then instructs the control unit 230 to transfer the workload from one core 140 to another core 140 or to enable the additional cores by hot plugging additional cores.

The third figure shows different operating areas of a CPU including multiple cores in accordance with an embodiment of the present invention. The CPU (e.g., CPU 102 of the first figure) includes at least one low power core 140(0) and a high performance core 140(N). As shown, a power curve 320 of the low power core 140(0) is plotted as a function of a total throughput 310. Similarly, a power curve 322 is drawn for the high performance core 140(N) and a power curve 324 is drawn for the dual core configuration. The total throughput 310 is defined herein as an instruction executed per second, while the power 312 is defined as the power unit required to maintain the corresponding total throughput 310, such as watts (or its fraction).

A core clock frequency can be varied to achieve a continuous varying degree of total throughput along the total throughput 310 axis. As shown, a maximum total throughput of the low power core 140(0) is less than a maximum total throughput of the high performance core 140(N). In an implementation scenario, the high performance core 140(N) is capable of operating at a clock frequency above the low power core 140(0). In a dual core mode associated with power curve 324, low power core 140(0) can be driven by one bit at a clock frequency in an associated upper operating range, while high performance core 140(N) can be The bits are driven at different clock frequencies in the associated medium operating range. In one configuration, each of the cores 140(0), 140(N) in the dual core mode is driven at the same clock frequency within the range of the two cores. In a different configuration, each of the cores 140(0), 140(N) in the dual core mode is at each core. The correlation range is driven by a different clock. In one embodiment, each clock frequency can be selected to achieve a similar forward execution process for each core. In a particular embodiment, the plurality of cores 140 are configured for operation with a common voltage supply and are operable in separate clock frequencies.

Within the low power core zone 330, the low power core 140(0) is capable of meeting the total throughput requirements of the minimum power using the three core configurations (low power, high performance, dual core). Within the high performance core zone 332, the high performance core 140(N) is capable of meeting the total throughput requirements of the minimum power using the three core configurations while the extended total throughput 310 exceeds a maximum total of the low power core 140(0). Processing amount 314. In a dual core zone 334, simultaneous operation of both the low power core 140(0) and the high performance core 140(N) can achieve a total throughput greater than the maximum total throughput 316 of the high performance core 140(N), This extends the overall total throughput, but at the expense of additional power consumption.

Given three operating zones 330, 332, 334 and a low power core 140(0) and a high performance core 140(N), six state transitions are supported between different core configurations. The first state transition is between region 330 and region 332; the second state transition is between region 332 and region 330; the third state transition is between region 330 and region 334; the fourth state transition is at region 334. Between region 330; fifth state transition is between region 332 and region 334; and sixth state transition is between region 334 and region 332. Those skilled in the art will appreciate that additional cores may add additional operational zones and additional potential state transitions between core configurations without departing from the scope and spirit of the present invention.

In one embodiment, core 140 within CPU 102 is characterized by power consumption as a function of voltage and frequency, and total throughput. The final features include a series of power curves and different operating zones with different power requirements. These different operating zones can be statically determined for a given CPU 102 design. The different operating zones may be stored in a table within the device driver 154, which in turn can configure the CPU 102 for different cores 140 for hot plugging and hot unplugging based on primary workload requirements. In one embodiment, device driver 154 re-responsive to current workload demands and reconfigures different cores 140 within CPU 102 to best meet these needs. In another embodiment, scheduler 152 is configured to schedule workloads based on available cores 140. Scheduler 152 can instruct device driver 154 to hot plug or hot pull out based on current and future knowledge of workload requirements The same core.

The fourth diagram shows a flow diagram of method steps for configuring a multi-core CPU to operate in a power saving zone in accordance with an embodiment of the present invention. The method steps are described in conjunction with the systems of the first to second figures; however, those skilled in the art will appreciate that any system configured to perform the method steps in any order falls within the scope of the present invention. Inside the category. In one embodiment, the method steps are implemented by CPU 102 of the first figure.

As shown, the method 400 begins at step 410 where the cluster control unit 230 of the second diagram initializes the core configuration of the CPU 102. In one embodiment, the cluster control unit 230 initializes the core configuration of the CPU 102 to reflect the low power core 140(0) availability of the first map. In this configuration, core 140(0) performs an operating system boot chronology, including loading and starting execution of core 150.

In step 412, device driver 154 receives the workload information. Workload information may include, but is not limited to, CPU load statistics, latency statistics, and the like. The workload information may be received from the cluster control unit 230 within the CPU 102 or a known core task and thread service. If there is a change in the workload reflected by the workload information in step 420, then the method proceeds to step 422, otherwise the method returns to step 412. In step 422, the device driver determines a commensurate core configuration to support the new workload information. The drive may use a static, previously calculated workload table that maps the power curve information to an effective core configuration that supports the necessary workload as reflected in the workload information.

If the commensurate core configuration indicates a change in the current core configuration in step 430, then the method proceeds to step 432, otherwise the method returns to step 412. In step 432, the device driver causes CPU 102 to transition to the commensurate core configuration. The transition process may involve hot insertion of one or more cores and may also involve hot extraction of one or more cores in accordance with a difference function between a current core configuration and the commensurate core configuration.

If the method should be terminated in step 440, then the method proceeds to step 490, otherwise the method returns to step 412. The method may have to be terminated upon receipt of a termination signal, for example during a full shutdown event.

Briefly, this document discloses a technique for managing processor cores within a multi-core CPU. This technology involves hot swapping core resources when necessary. Each core includes a virtual ID to allow the core execution context to be extracted from a particular physical core circuit. As system workload increases, the core configuration may change to support these increases. Similarly, as system workloads decrease, core configurations may change to reduce power consumption while supporting reduced workloads.

An advantage of the disclosed technology is that it can advantageously improve the power efficiency of a multi-core central processing unit over a wide range of workloads while efficiently utilizing processing resources.

The foregoing is a description of the embodiments of the present invention, and other embodiments of the invention may be devised without departing from the basic scope of the invention. For example, aspects of the invention may be practiced in the form of a hard or soft body or a combination of a hardware and a soft body. An embodiment of the present invention can be implemented as a program commodity for a computer system. The program of the program product defines the functionality of the embodiment (including the methods described herein) and can be housed in a wide variety of computer readable storage media. Exemplary computer readable storage media include, but are not limited to: (i) non-writable storage media on which information is permanently stored (eg, a read-only memory device within the computer, for example, a read-only memory) CD-ROM disc, flash memory, read only memory (ROM), or any type of solid non-volatile semiconductor read by CD-ROM (Compact Disc Read Only Memory) And (ii) a writable storage medium on which the changeable information is stored (for example, a floppy disk in a disk drive or a hard disk drive or any type of solid state random access semiconductor memory).

The invention has been described above with reference to specific embodiments. However, those skilled in the art will appreciate that various modifications and changes can be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims. Therefore, the foregoing description and drawings are to be considered as illustrative and not limiting.

Therefore, the scope of the invention is determined by the scope of the following claims.

400‧‧‧ method

410-490‧‧‧Steps

Claims (10)

A method for configuring two or more cores in a processing unit to perform different workloads, the method comprising: receiving information related to a new workload; determining, based on the information, that the new workload is different from current work Loading; extracting characteristic data associated with power consumption characteristics included in each of the two or more cores; determining the number of the two or more cores based on the information and the characteristic data Should be configured to execute the new workload; determine if a new core configuration is needed based on how many of the two or more cores should be configured to perform the new workload; and if a new core configuration is required If so, then the processing unit is converted to the new core configuration, or, if a new core configuration is not required, then the current core configuration is maintained to perform the new workload. The method of claim 1, wherein only one low power core performs work in the current core configuration, and determining how many of the two or more cores should be configured includes determining that only one high performance core should Configuring to perform the new workload, and further comprising determining that a new core configuration is required, and transitioning the processing unit by turning off the low power core and turning on the high performance core to execute the new workload. The method of claim 1, wherein only one high performance core performs work in the current core configuration, and determining how many of the two or more cores should be configured includes determining that only one low power core should be Configuring to perform the new workload, and further comprising determining that a new core configuration is required, and transitioning the processing unit by shutting down the high performance core and turning on the low power core to execute the new workload. The method of claim 1, wherein only one low power core performs work in the current core configuration, and determining how many of the two or more cores should be configured comprises determining the low power core and one Both of the high performance cores should be configured to perform the new workload, and further include determining that a new core configuration is needed, and by turning on the The high performance core executes the new workload to transform the processing unit. The method of claim 1, wherein only one high performance core performs work in the current core configuration, and determining how many of the two or more cores should be configured includes determining a low power core and the Both of the high performance cores should be configured to execute the new workload, and further include determining that a new core configuration is needed, and transitioning the processing unit by turning on the low power core to execute the new workload. The method of claim 1, wherein a low power core and a high performance core perform work in the current core configuration, and determining how many of the two or more cores should be configured includes determining that only The high performance core should be configured to execute the new workload, and further includes determining that a new core configuration is needed, and transitioning the processing unit by shutting down the low power core to perform the new workload. The method of claim 1, wherein a low power core and a high performance core perform work in the current core configuration, and determining how many of the two or more cores should be configured includes determining that only The low power core should be configured to execute the new workload, and further includes determining that a new core configuration is needed, and transitioning the processing unit by shutting down the high performance core to perform the new workload. The method of claim 1, wherein the processing unit comprises a central processing unit or a graphics processing unit. The method of claim 1, wherein each core included in the two or more cores is identifiable by a programmable identifier, and one or more programmable identifiers are Used to transition the processing unit to the new core configuration. A computing device comprising: a central processing unit comprising at least one low power core and at least one high performance core, the central processing unit having been programmed to configure two or more cores to perform different functions by: Workload: receiving information related to a new workload; determining, based on the information, that the new workload is different from the current workload; extracting the associated power included in each of the two or more cores Characteristic data of the consumption feature; Based on the information and the feature data, it is determined how many of the two or more cores should be configured to execute the new workload; and how many of the two or more cores should be configured to be used Performing this new workload as a basis to determine if a new core configuration is required; and if a new core configuration is required, then the processing unit is converted to the new core configuration, or, if a new core configuration is not required, then Keep the current core configuration to perform this new workload.