TWI500117B - Method of manufacturing non-volatile memory - Google Patents

Description

Non-volatile memory manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a non-volatile memory device.

Non-volatile memory (NVM) is widely used in various electronic products because the written data does not disappear after power-off and can be read, written, and erased multiple times. Among them, portable electronic devices such as mobile phones and digital cameras. A typical non-volatile memory includes a stacked gate structure composed of a floating gate (FG) and a control gate (CG), wherein the floating gate is disposed on the substrate and the control gate Between the electrodes, there is a tunneling dielectric layer between the floating gate and the substrate, and a gate dielectric layer between the control gate and the floating gate. By controlling the state of electron distribution in the floating gate, the threshold voltage (Vt) of the memory cell is changed, thereby achieving the effect of reading, writing, or erasing data.

For different types of non-volatile memory devices, an appropriate voltage is applied to the control gate so that electrons in the channel of the memory cell enter and exit the floating gate through different mechanisms to change the floating gate. The state of charge distribution. Therefore, the interface properties of the floating gate of the memory cell (such as the surface uniformity between the floating gate and the gate dielectric layer) have a significant impact on the reading, writing, and erasing of the data.

1A to 1D are a series of cross-sectional views for explaining the flow of a conventional method of manufacturing the non-volatile memory device 100. First, an isolation structure, such as shallow trench isolation (STI), may be formed on the substrate 10 to electrically isolate the various electronic components. As shown in FIG. 1A, the substrate 10 includes a memory cell region C and a peripheral region P. The two regions (the memory cell region C and the peripheral region P) respectively have a plurality of isolation structures 102c and 102p protruding from the surface of the substrate 10. Dielectric layers 104c and 104p are formed between the respective isolation structures 102c and 102p, respectively. Forming first mask layers 106c and 106p above the dielectric layers 104c and 104p, respectively, the first mask The layers 106c and 106p are used as a mask layer for forming a non-isolated structure when forming an isolation structure. Next, as shown in FIG. 1B, in order to form the floating gate of the memory cell, the first mask layers 106c and 106p are removed to expose the openings between the respective isolation structures 102c, 102p, and well implanted )I. As shown in FIG. 1C, after removing the dielectric layers 104c and 104p and forming the tunneling dielectric layers 104c' and 104p', the conductor layer 108 is blanket-formed on the surface of the substrate 10 to fill the isolation structures. An opening between 102c and 102p as a floating gate of a non-volatile memory device.

After filling in the conductor layer 108 as a floating gate, it is necessary to planarize the surface of the structure above the substrate 10 to ensure the electrical properties of the memory cell and facilitate the subsequent process, so that a chemical mechanical polish can be implemented. , CMP) steps. This step is usually performed by first forming a patterned polishing barrier layer over the peripheral region of the substrate 10, and polishing the structure above the substrate 10 to an appropriate thickness and surface uniformity based on the patterned polishing barrier layer. . As shown in FIG. 1C, the polishing barrier layer 110 is generally formed by depositing a layer of a film having a different etching selectivity from the conductor layer 108 over the substrate 10. For example, when a polysilicon is used as the conductor layer 108, a nitrogen can be deposited. A two-layer structure in which a ruthenium layer is laminated with tetraethyl orthosilicate (TEOS) is used as the polishing barrier layer 110. The portion of the polishing barrier layer 110 located in the memory cell region C can be selectively removed by an optical lithography and etching step, leaving a portion of the peripheral region P to form a patterned polishing barrier layer 110'. However, please refer to FIG. 1C~1D at the same time. Since the patterned polishing barrier layer 110' is disposed on the conductor layer 108, the thickness of the portion of the substrate 10 on which the conductor layer 108 is thin may be slightly lower than the pattern. The polishing barrier layer 110' causes the thinner regions to be subjected to sufficient polishing to cause surface uniformity of the structure above the substrate 10 to deteriorate, for example, in the memory of the non-volatile memory device 100. A dishing may be formed on the floating gate of the cell C, or a residual material of the conductor layer may be present in the peripheral region P, thereby causing device failure, Vt distribution shift, Equipment reliability is reduced, and production yield is reduced.

Therefore, there is a need to find a new method for manufacturing non-volatile memory to solve the above problems in the conventional methods and to improve the performance of the memory device.

An embodiment of the present invention provides a method for manufacturing a non-volatile memory, including The invention comprises: providing a substrate, the substrate comprises a memory cell region and a peripheral region, the substrate has a plurality of isolation structures protruding from the surface of the substrate, and a dielectric layer between the isolation structures and a first cover on the dielectric layer Curtain layer; etch back the first mask layer to make the first mask layer lower than the isolation structure; blanket forming a second mask layer on the isolation structure and the first mask layer; selectively removing the memory layer a second mask layer and a first mask layer; removing a second mask layer located in the peripheral region, leaving a first mask layer in the peripheral region; forming a gap between the isolation structures located in the memory unit region a conductive layer; and a chemical mechanical polishing step is performed by using a first mask layer located in the peripheral region as a polishing stop layer.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

10, 20‧‧‧ base

100, 200‧‧‧ non-volatile memory devices

102c, 102p, 202c, 202p‧‧‧ isolation structure

104c, 104p, 204‧‧‧ dielectric layer

104c', 104p', 204'‧‧‧ tunneling dielectric layer

108‧‧‧Conductor layer

110‧‧‧Making stop layer

110’‧‧‧ patterned grinding stop layer

206c, 206p‧‧‧ first cover layer

208‧‧‧second cover layer

208’‧‧‧ patterned second mask

210c‧‧‧ openings

212c‧‧‧Floating gate

C‧‧‧ memory unit area

P‧‧‧ surrounding area

D‧‧‧ Defects in dishing

T‧‧‧ height difference

I‧‧‧ well planting (ion implant)

Figures 1A to 1D are a series of cross-sectional views illustrating the flow of a conventional method of manufacturing a non-volatile memory.

2A-2E are a series of cross-sectional views for explaining the flow of an embodiment of the non-volatile memory manufacturing method of the present invention.

The present invention is to be construed as being limited to the scope of the present invention. Non-essential elements may be omitted from the drawings, and different features may not be drawn to scale. The present disclosure may have overlapping element symbols in different embodiments and does not represent an association between different embodiments or drawings. In addition, an element formed "above", "above", "below" or "below" another element may include an embodiment in which two elements are in direct contact, or may include other additional elements interposed between the two elements. An embodiment. The various components may be displayed at any different scale to make the illustration clear and concise.

2A-2E are a series of cross-sectional views for explaining the flow of an embodiment of the method of manufacturing the non-volatile memory of the present invention.

First, referring to FIG. 2A, a substrate 20 is provided. The substrate 20 includes a memory cell region C and a peripheral region P. A plurality of isolation structures 202c and 202p are formed in the two regions (the memory cell region C and the peripheral region P) of the substrate 20, respectively, which protrude from the surface of the substrate 20. The isolation structures 202c and 202p can be formed by using a shallow trench isolation process well known in the art. For example, a dielectric layer material (not shown) and a first mask layer material can be sequentially deposited on the substrate 20. After being shown, a portion of the first mask layer material, the dielectric layer material, and the substrate 20 are removed by an optical lithography and etching step to form a plurality of trenches in the substrate 20, and between the trenches. A dielectric layer 204 and first mask layers 206c and 206p on the dielectric layer 204 are formed. Dielectric materials are then filled into the trenches to form isolation structures 202c and 202p that protrude from the surface of substrate 20, respectively, for electrically isolating different devices, such as memory cells. In this step, the substrate 20 may be a germanium substrate, and the dielectric layer 204 (or dielectric layer material) may include germanium oxide, which may have a thickness between 140 and 180 nanometers, and may be thermally oxidized or Formed by chemical vapor deposition. The first mask layers 206c and 206p may include tantalum nitride and may be formed by chemical vapor deposition. The isolation structures 202c and 202p may include ruthenium oxide formed by a suitable method, such as ruthenium oxide formed by high density plasma chemical vapor deposition (HDP-CVD). After the isolation structures 202c and 202p are formed, the first mask layers 206c and 206p are not removed, so that the first mask layers 206c and 206p remain on the dielectric layer 204 between the isolation structures 202c and 202p.

Next, referring to FIG. 2B, a portion of the surface of the first mask layers 206c and 206p is etched back so that the surfaces of the first mask layers 206c and 206p are lower than the isolation structures 202c and 202p, and have one with the isolation structures 202c and 202p. Height difference t. Subsequently, a second mask layer 208 is blanket formed on the isolation structures 202c and 202p and the first mask layers 206c and 206p. Prior to the etch back step, a de-glass process well known in the art can be used to make the isolation structures 202c and 202p approximately lower than the first mask layers 206c and 206p for ease of blanketing. The first mask layers 206c and 206p are removed. In the present embodiment, the height difference t is 150 to 300 Å (Å). The second mask layer 208 can use a polysilicon having a thickness greater than 300 angstroms and can be formed using, for example, chemical vapor deposition.

Referring to FIG. 2C, in order to form the floating gates of the respective memory cells, it is necessary to remove at least the first mask layer 206c and the second mask layer 208 located in the memory cell region C to expose between the isolation structures 202c. Opening 210c. In this embodiment, after the second mask layer 208 is formed, the second mask layer 208 is patterned by an optical lithography and etching step to selectively remove the second mask layer 208 in the memory unit. Part of the area C leaves only the second mask pattern layer 208' located in the peripheral area P. Thereafter, the first mask layer 206c located in the memory cell region C is removed. in When the first mask layer 206c located in the memory cell region C is removed, since the first mask layer 206p located in the peripheral region P is protected by the second mask pattern layer 208', it is not located in the memory cell region C. The first mask layer 206c is removed together and can remain in the subsequent steps. The method of removing the first mask layer 206 can include wet etching.

Referring to Figure 2D, the second mask pattern layer 208' is removed and the memory cell can be implanted in accordance with techniques well known in the art. Thereafter, referring to FIG. 2E, after the implantation is completed, the dielectric layer 204c located in the memory cell region C can be removed, and the tunnel dielectric layer 204c' is separately formed to ensure the quality of the dielectric layer of the memory cell, and Forming a conductor layer (not shown) on the structure shown in FIG. 2D to fill the opening 210c (in the 2D figure) between the isolation structures 202c and 202p in the memory cell region C, and The first mask layer 206p located in the peripheral region P is used as a polishing stop layer, a chemical mechanical polishing step is performed to planarize the surface, and a floating gate 212c is formed in the memory cell region C. In the present embodiment, since the etching selection of polycrystalline germanium and cerium oxide is relatively close when chemical mechanical polishing is performed, and the etching selectivity ratios of polycrystalline germanium and tantalum nitride are largely different, when chemical mechanical polishing is performed, polycrystalline germanium is formed. The polishing layer material and the isolation structures 202c and 202p composed of yttrium oxide are relatively faster and faster, and the first mask layer 206p composed of tantalum nitride has a slower polishing speed. The first mask layer 206p of the peripheral region P serves as a reference point for polishing. After the chemical mechanical polishing step is completed, a non-volatile memory device 200 having a floating gate 212c between the isolation structures 202c located in the memory cell region C is obtained. In the present embodiment, the first mask layer 206p remains between the isolation structures 202p of the peripheral region P.

Since the present invention uses the first mask layer 206p which is lower in height than the isolation structures 202c and 202p and disposed under the conductor layer material as the polishing stop layer, it may be higher than that disposed in the conductor layer 108 in the prior art. The first mask layer 110 of the conductor layer 108 in a portion of the region serves as a polishing stop layer (refer to FIG. 1D), and the present invention ensures that the surface of the non-volatile memory device 200 is ground to the target during fabrication. The height can avoid poor surface uniformity (such as disc-shaped depressions, defects in the conductor layer material, etc.), resulting in problems such as device failure, critical voltage drift, device reliability, and reduced production yield. In addition, the non-volatile memory manufacturing method provided by the present invention is compatible with the current process, and the steps are simple, so that the device performance can be improved without increasing the production cost.

Although the invention has been disclosed above in several preferred embodiments, it is not intended to be limiting The invention may be modified and modified in any way without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. Prevail.

20‧‧‧Base

202c, 202p‧‧‧ isolation structure

204‧‧‧Dielectric layer

206p‧‧‧First cover layer

208’‧‧‧Second mask pattern layer

210c‧‧‧ openings

C‧‧‧ memory unit area

P‧‧‧ surrounding area

t‧‧‧The difference between the height of the first mask layer and the isolation structure

Claims (8)

A method of manufacturing a non-volatile memory, comprising: providing a substrate, the substrate comprising a memory cell region and a peripheral region, the substrate having a plurality of isolation structures protruding from a surface of the substrate, and having between the isolation structures a dielectric layer and a first mask layer on the dielectric layer; etch back the first mask layer such that the first mask layer is lower than the isolation structures; and etching back the first mask After the layer, a second mask layer is blanket-formed on the isolation structures and the first mask layer; and the second mask layer and the first mask layer located in the memory cell region are selectively removed Removing the second mask layer in the peripheral region, leaving the first mask layer in the peripheral region; forming a conductive layer between the isolation structures located in the memory cell region; The first mask layer of the peripheral region is a polishing stop layer, and a chemical mechanical polishing step is performed on the conductive layer. The method of manufacturing a non-volatile memory according to claim 1, wherein the second mask layer is polycrystalline germanium. The method of manufacturing a non-volatile memory according to claim 1, wherein the step of selectively removing the second mask layer and the first mask layer located in the memory unit region comprises performing a lithography And etching steps. Manufacturer of non-volatile memory as described in claim 1 The method wherein the step of forming the second mask layer comprises a chemical vapor deposition step. The method of manufacturing a non-volatile memory according to claim 1, wherein the first mask layer comprises tantalum nitride. The method of manufacturing a non-volatile memory according to claim 1, wherein the isolation structure comprises ruthenium oxide. The method of manufacturing a non-volatile memory according to claim 1, wherein the dielectric layer comprises ruthenium oxide. The method of manufacturing a non-volatile memory according to claim 1, wherein the conductive layer comprises polycrystalline germanium.