TWI496961B - Electrical chemical plating process - Google Patents

Description

Electrochemical plating step

The present invention relates to a plating step, particularly a plating step having a preliminary plating step, which helps to improve the bottom filling ability of the copper conductive layer.

Due to the shrinking of the line width of the components, the metal materials used to fill the trenches to form the inner metal wires are unable to meet the needs of the current semiconductor industry due to factors such as poor hole filling ability and high resistance value. Therefore, metallic copper having high conductivity is widely used for making inner metal wiring of a low line width.

Conventionally, a method of forming a copper conductive layer is a chemical vapor deposition process. Chemical vapor deposition uses a chemical substance containing an organic substance as a source gas, and thus the formed copper conductive layer has a high resistivity, and particularly when the thickness of the copper layer is decreased, the resistivity is further increased. In addition, residues generated after chemical vapor deposition cause problems in adhesion between the copper layer and subsequent deposited thin film layers. On the other hand, the cost of chemical vapor deposition is relatively high, which is not conducive to the production of current semiconductor processes.

At present, electrochemical plating (ECP) technology is widely used in the industry to form a copper conductive layer, which is not only low in cost but also does not increase the resistivity of the copper layer. In the electrochemical plating process, the semiconductor substrate is immersed in the electrolyte, and the copper ions in the electrolyte are reduced to metal copper, and the copper conductive layer can be gradually formed on the semiconductor substrate. However, the conventional electrochemical plating process often has a problem of poor bottom up fill rate, and the trench cannot be completely filled by the copper conductive layer, thereby causing a short circuit and affecting the quality of the component. Therefore, various manufacturers are committed to research and improve the existing electrochemical plating process to obtain a copper conductive layer with better hole filling ability.

The invention thus proposes an electrochemical plating method which contributes to the improvement of the bottom filling ability of the copper conductive layer.

The method of electrochemical plating proposed by the present invention first provides a semiconductor structure in an electroplating machine. A preliminary plating step is then performed, which is performed in a fixed voltage environment and continues for 0.2 to 0.5 seconds after the current exceeds the threshold current of the plating station. After the preliminary plating step, a first plating step is performed on the semiconductor structure.

In the electrochemical plating step of the present invention, there is a preliminary plating step, and the preliminary plating step is performed in a predetermined voltage environment. The preliminary plating step proposed by the present invention is preferably between 0.2 seconds and 0.5 seconds, which can achieve a better balance between the plating time and the plating quality, thereby improving the overall production quality.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 6 , which are schematic diagrams showing the steps of the method for electrochemical plating in the present invention. As shown in FIG. 1, a semiconductor structure 400 is first provided. In one embodiment, the semiconductor structure 400 includes a substrate 401 and an insulating layer 403 on the substrate 401. The substrate 401 is, for example, a germanium substrate or a metal interlayer dielectric layer, and the substrate 401 has a conductive region 405, such as a source/drain region doped with ions, or a metal interconnect pattern ( The metal interconnection pattern can be electrically connected to the conductive layer 405 in a subsequent metal layer formed by electrochemical plating. The insulating layer 403 may be germanium dioxide or other low-k material.

Next, as shown in FIG. 2, a single damascene pattern or a dual damascene pattern of the trench 402 or the like is formed in the insulating layer 403 of the semiconductor structure 400. The manner in which the trenches 402 are formed is, for example, photo-etching-process (PEP) to expose the conductive regions 405 in the substrate 401. The shape of the opening of the trench 402 may be a circular hole or other irregular pattern. In one embodiment, the trench 402 has a depth of between about 2,000 angstroms and about 10,000 angstroms.

Next, as shown in FIG. 3, a seed layer 404 is formed over the semiconductor structure 400. The manner of forming the seed layer 404 is, for example, a physical vapor deposition or a chemical vapor deposition, wherein the seed layer 404 is formed on the insulating layer 403 and along the trench 402. The surface is conformally formed with a thickness between approximately 30 angstroms and 200 angstroms. The material of the seed layer 404 is adjusted according to the material of the subsequent metal layer. For example, when the metal layer is copper, the seed layer 404 is a copper seed layer. In another embodiment, a barrier layer (not shown) may be selectively formed conformally before forming the seed layer 404, such as a Ti/TiN layer or a Ta/TaN layer.

As shown in Fig. 4, a preliminary plating step is performed. As described above, the trench 402 in the semiconductor structure 400 has been covered with a seed layer 404. In performing the preliminary plating step, the semiconductor structure 400 is placed in a plating machine 406 having an electrolyte, and a voltage is supplied to the seed layer 404 with the electrode 408 to perform a preliminary plating step. The preliminary plating step of the present invention is a preparation operation before the formal plating step. Since the semiconductor structure 400 cannot be stably plated when initially placed in the plating machine 406, the preliminary plating step helps to improve the quality of the subsequent formal plating step. .

Please refer to FIG. 7 , which is a schematic diagram showing the waveforms of voltage and current with respect to time in the electrochemical plating step of the present invention. As shown in Fig. 7, when the electrode 408 is passed through a predetermined voltage, the current in the plating machine 406 is gradually increased. When the current is greater than a preset threshold current (the lowest current value at which the plating machine 406 can operate stably) in the plating machine 406, the present invention enters the preliminary plating step 410. The preliminary plating step 410 of the present invention is carried out in a fixed voltage environment. In one embodiment of the invention, the fixed voltage ranges generally between 0.6 volts and 1.0 volts, preferably 0.8 volts. The time for the preliminary plating step 410 is substantially 0.2 to 0.5 seconds, preferably 0.3 seconds. In one embodiment of the invention, in the preliminary plating step 410, the current will gradually rise and eventually stay at a maximum value which is approximately 8 amps to 10 amps.

A first plating step 412 is then performed. As shown in FIG. 5, the first plating step 412 is a formal plating step, and the metal layer 414 is gradually formed on the seed layer 404 on the surface of the trench 402. And since the preliminary plating step 410 is performed before the first plating step 412, the formation speed of the metal layer 414 at the bottom of the trench 402 at the first plating step 412 is faster, so that a better bottom hole filling capability can be obtained. Fill rate). As shown in FIG. 7, in a preferred embodiment of the present invention, the first plating step 412 is performed under a first fixed current condition, and the first fixed current ranges from about 4.0 amps to 5.0 amps, preferably. It is 4.5 amps.

Next, as shown in FIG. 6, a second plating step 416 is performed. In the second plating step 416, the metal layer 414 gradually fills the trench 402 and is finally slightly above the trench 402. As shown in FIG. 7, in the preferred embodiment of the present invention, the second plating step 414 is performed under a second fixed current, and the value of the second fixed current is preferably greater than the value of the first fixed current. For example, between 6.0 amps and 7.0 amps, preferably 6.5 amps.

After the second plating step 416 is completed, the metal layer 414 has been formed on the surface of the semiconductor structure 400 and has been well filled in the trench 402. In another embodiment of the present invention, a third plating step may be selectively performed after the second plating step 416, depending on the thickness of the metal layer 414 to be formed. Preferably, the third plating step is also performed in a third fixed current environment, and the value of the third fixed current is greater than the value of the second fixed current. Finally, after the electrochemical plating step is completed, the excess metal layer 414 on the semiconductor structure 400 can be removed, for example, a planarization step of a chemical mechanical polish (CMP) or the like is performed in the trench 402. A well-filled metal layer 414 is formed.

In the electrochemical plating step of the present invention, there is a preliminary plating step, and the preliminary plating step is performed in a predetermined voltage environment. If the pre-plating step is too short (for example, less than 0.2 seconds), the subsequent formal electroplating process will take more time. If the pre-plating step is too long (for example, longer than 0.5 seconds), the bottom of the metal layer will be filled, so The preliminary plating step proposed by the present invention is preferably between 0.2 seconds and 0.5 seconds, which can achieve a better balance between the plating time and the plating quality, thereby improving the overall production quality.

Please refer to FIG. 8 , which is a schematic diagram showing the steps of the electroplating step of the present invention. First, a semiconductor structure is provided in a plating machine (step 300). Next, a preliminary plating step is performed wherein the preliminary plating step is performed in a fixed voltage environment and continues for 0.2 to 0.5 seconds after the current exceeds the threshold current of the plating station (step 302). Finally, a formal plating step (step 304) is performed on the semiconductor structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . step

302. . . step

304. . . step

400. . . Semiconductor structure

401. . . Base

402. . . ditch

403. . . Insulation

404. . . Seed layer

405. . . Conductive zone

406. . . Plating machine

408. . . electrode

410. . . Prepare plating step

412. . . First plating step

414. . . Metal layer

416. . . Second plating step

1 to 6 are schematic views showing the steps of the method of electrochemical plating in the present invention.

FIG. 7 is a schematic view showing the waveforms of voltage and current in the electrochemical plating step of the present invention.

Figure 8 is a schematic view showing the steps of the electroplating step of the present invention.

300. . . step

302. . . step

304. . . step

Claims (10)

A method of electrochemical plating, comprising: providing a semiconductor structure in an electroplating machine; performing a preliminary electroplating step, wherein the pre-plating step is performed in a fixed voltage environment and the current exceeds a valve of the electroplating machine The value current is continued for 0.2 to 0.5 seconds; and after the preliminary plating step, a first plating step is performed on the semiconductor structure. The method of electrochemical plating according to claim 1, wherein the preliminary plating step has a duration of 0.3 seconds. The method of electrochemical plating according to claim 1, wherein the fixed voltage of the preliminary plating step is substantially 0.8 volts. The method of electrochemical plating according to claim 1, wherein the maximum current in the preliminary plating step is 10 amps. The method of electrochemical plating according to claim 1, wherein the first electroplating step is performed in a first fixed current environment. The method of electrochemical plating according to claim 5, wherein the first fixed current of the first electroplating step is substantially between 4.0 amps and 5.0 amps. The method of electrochemical plating according to claim 6, wherein the first fixed current of the first electroplating step is substantially 4.5 amps. The method of electrochemical plating according to claim 5, wherein after the first plating step, a second plating step is further included, the second plating step being performed in a second fixed current. The method of electrochemical plating according to claim 8, wherein the second fixed current is greater than the first fixed current. The method of electrochemical plating according to claim 8, wherein the second fixed current is substantially between 6.0 amps and 7.0 amps.