TWI495045B - Stack capacitor and method of forming the same - Google Patents

Description

Stacked capacitor and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a stacked capacitor having a reinforced structure and a method of fabricating the same.

The memory cell of the DRAM is composed of an MOS transistor and a capacitor electrically connected to each other. Capacitors are mainly used to store the charge representing the data, and must have high capacitance to ensure that the data is not easily lost.

In addition to increasing the dielectric constant of the dielectric material and reducing the thickness of the dielectric material, the method of increasing the charge storage capacity of the capacitor can also be achieved by increasing the surface area of the capacitor. However, as semiconductor technology continues to move toward submicron and deep submicron advances, conventional capacitor processes are no longer sufficient, so researchers have developed dielectric materials with high dielectric constants and increased the surface area of capacitors to increase capacitor capacitance. value.

In general, the most intuitive way to increase the surface area is to increase the capacitance height, and this approach will directly involve the problem of insufficient mechanical strength of the capacitor itself. When the mechanical strength of the capacitor is insufficient, it is easy to find the phenomenon that the capacitor structure is deformed or even dumped. In view of this, how to form a stacked capacitor having a reinforced structure has been highly noticed by the industry.

The invention provides a stacked capacitor and a method of manufacturing the same. The stacked capacitor of the present invention can have a higher height and a larger capacitor surface area than conventional stacked capacitors, and its reinforcing structure can avoid deformation or even dumping of the capacitor structure.

The present invention provides a method of fabricating a stacked capacitor. Forming a first support layer, a first insulating layer, a second supporting layer, a second insulating layer, a third supporting layer and a hard mask layer on the substrate. Forming at least one first opening in the second supporting layer, the second insulating layer, the third supporting layer, and the hard mask layer. A spacer is formed on the sidewall of the first opening. The second opening is formed in the first supporting layer and the first insulating layer by using the spacer as a mask. A back-off process is performed to increase the width of the second opening in the first insulating layer. Remove the spacers. A lower electrode, a dielectric layer and an upper electrode are sequentially formed in the second opening and the first opening.

The present invention further provides a stacked capacitor comprising a substrate, a first supporting layer, a first insulating layer, a second supporting layer, a second insulating layer, a third supporting layer, a lower electrode, a dielectric layer and an upper electrode. The first supporting layer, the first insulating layer, the second supporting layer, the second insulating layer and the third supporting layer are sequentially disposed on the substrate. The second support layer, the second insulating layer and the third support layer have a first opening, and the first support layer and the first insulating layer have a second opening therein, and the width of the second opening in the first insulating layer is greater than The width of an opening. The lower electrode, the dielectric layer and the upper electrode are sequentially disposed in the second opening and the first opening.

The present invention further provides a stacked capacitor comprising a substrate, a first support layer, a first insulating layer, a second supporting layer, a third supporting layer, a lower electrode, a dielectric layer and an upper electrode. The first support layer, the second support layer and the third support layer are sequentially disposed on the substrate, and the first support layer, the second support layer and the third support layer are separated from each other, wherein the second support layer and the third support layer have The first opening has a second opening in the first supporting layer, and the first opening is in communication with the second opening. The lower electrodes are disposed on the inner side and the bottom of the second opening and on the inner side of the first opening. The dielectric layer is disposed on the inner side and the bottom of the lower electrode in the second opening and on the inner side and the outer side of the lower electrode disposed in the first opening. The upper electrode is disposed on the dielectric layer on the inner side and the bottom of the lower electrode in the second opening and on the inner and outer dielectric layers of the lower electrode in the first opening.

Based on the above, the present invention utilizes a reinforcing structure composed of a first supporting layer (bottom supporting layer), a second supporting layer (middle supporting layer) and a third supporting layer (upper supporting layer) to increase the mechanical strength of the stacked capacitor to avoid The phenomenon that the capacitor structure is deformed or even dumped. In addition, the stacked capacitor of the present invention can have a higher height (that is, a larger capacitance value) than the conventional stacked capacitor by the arrangement of the second supporting layer (the middle supporting layer), and can be The height of an insulating layer and a second insulating layer controls the desired capacitance value. In addition, the surface area of the capacitor can be greatly increased by the back-off process and the demolding step of the present invention, thereby increasing the capacitance.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1F are schematic cross-sectional views showing a method of fabricating a stacked capacitor according to an embodiment of the invention.

Referring to FIG. 1A, a first support layer 102, a first insulating layer 104, a second support layer 106, a second insulating layer 108, a third supporting layer 110, and a hard mask layer 112 are sequentially formed on the substrate 100. The substrate 100 is, for example, a crucible substrate. The materials of the first support layer 102, the second support layer 106, and the third support layer 110 each include tantalum nitride. The materials of the first insulating layer 104 and the second insulating layer 108 each include yttrium oxide. The hard mask layer 112 includes a tantalum nitride mask layer 112a and a carbon mask layer 112b disposed on the tantalum nitride mask layer 112a. The method of forming the above laminate includes performing a chemical vapor deposition (CVD) process.

Then, at least one first opening 114 is formed in the second supporting layer 106, the second insulating layer 108, the third supporting layer 110, and the hard mask layer 112. The first opening 114 has a width W1. The method of forming the first opening 114 is, for example, forming a patterned photoresist layer (not shown) on the carbon mask layer 112b, and then forming a patterned photoresist layer as a mask to perform a dry etching process. Further, in the step of forming the first opening 114, a portion of the carbon mask layer 112b in the hard mask layer 112 is simultaneously removed and a portion of the second support layer 106 remains at the bottom of the first opening 114. The remaining carbon mask layer 112b and the patterned photoresist layer are simultaneously completely removed during the subsequent ashing step.

Next, a spacer 116 is formed on the sidewall of the first opening 114. The method of forming the spacers 116 is, for example, a layer of spacer material (not shown) is formed conformally on the sidewalls and the bottom of the first opening 114 on the tantalum nitride mask layer 112a. The spacer material layer is, for example, a titanium nitride (TiN) layer, and is formed by, for example, a chemical vapor deposition process or an atomic layer deposition (ALD) process. Then, a layer of spacer material on the tantalum nitride mask layer 112a and on the bottom of the first opening 114 is removed. The removing step is performed by, for example, using the second supporting layer 106 remaining at the bottom of the first opening 114 as an etch stop layer to perform an anisotropic etching process.

Thereafter, referring to FIG. 1B , the second opening 118 is formed in the first supporting layer 102 and the first insulating layer 104 with the spacers 116 as a mask. The method of forming the second opening 118 is performed by, for example, using a tantalum nitride mask layer 112a and a spacer 116 as a mask to perform a dry etching process. Further, in the step of forming the second opening 118, the tantalum nitride mask layer 112a in the partial hard mask layer 112 and the second support layer 106 remaining in the bottom of the first opening 114 are simultaneously removed. Of course, a portion of the spacers 116 on the sidewalls of the tantalum nitride mask layer 112a are also removed at the same time.

It is particularly noted that in the step of forming the first opening 114 and the second opening 118, the carbon mask layer 112b and the tantalum nitride mask layer 112a may be separately removed without additional steps to remove the hard Mask layer 112. Therefore, process costs can be saved.

Then, referring to FIG. 1C, a rewinding process is performed to increase the width of the second opening 118 in the first insulating layer 104. The back-off process includes a wet etching process, such as using buffer oxide etchant (BOE), diluted hydrogen fluoride (DHF), or buffered hydrofluoric acid (BHF). In particular, the second opening 118 includes a lower opening 118a in the first support layer 102 and an upper opening 118b in the first insulating layer 104. The width W3 of the lower opening 118a is smaller than the width W2 of the upper opening 118b. The width W2 of the lower opening 118a is substantially greater than or equal to the width W1 of the first opening 114. Further, the width W3 of the lower opening 118a is smaller than the width W1 of the first opening 114. It is particularly noted that the back-off process of FIG. 1C can increase the surface area of the electrode 120 that is subsequently formed, thereby increasing the capacitance. In addition, the back-up process increases the width of the upper opening 118b to W2, and also increases the process window.

Next, referring to FIG. 1D, the spacers 116 are removed. The method of removing the spacers 116 is, for example, a wet etching process, and a mixture of hydrogen peroxide and sulfuric acid can be used. Then, the lower electrode 120 is conformally formed in the second opening 118 and the first opening 114. The lower electrode 120 is disposed on the inner side and the bottom surface of the second opening 118 and on the inner side of the first opening 114. That is, the lower electrode 120 has a hollow cylindrical shape. The material of the lower electrode 120 is, for example, titanium nitride. The method of forming the lower electrode 120 is, for example, a chemical vapor deposition process.

Thereafter, referring to FIG. 1E, a mold stripping step is performed to remove the second insulating layer 108 and expose a portion of the lower electrode 120. The demolding step will be described in detail with reference to the upper view of Fig. 2 and the cross-sectional view of Fig. 1E. 2 illustrates a schematic diagram of a plurality of stacked capacitors, such as, but not limited to, a plurality of first openings 114 and a third opening 122. First, at least a third opening 122 (shown in FIG. 2) is formed in the second insulating layer 108 and the third supporting layer 110. Viewed from the top view of FIG. 2, the third opening 122 overlaps with a portion of the first opening 114. The method for forming the third opening 122 is, for example, forming a patterned photoresist layer (not shown) on the substrate 100, and then performing a pattern by using the patterned photoresist layer as a mask and the second supporting layer 106 as an etch stop layer. Etching process. Next, a wet etching process is performed to inject an etchant from the third opening 122 to remove the second insulating layer 108 and expose a portion of the lower electrode 120 (ie, expose the outside of the lower electrode 120 in the first opening 114). At this time, after the second insulating layer 108 is completely removed, an upper hollow intermediate structure is formed, and the third support layer 110, the second support layer 106, the first insulating layer 104 and the lower electrode 120 support the entire structure.

Next, referring to FIG. 1F, the dielectric layer 124 and the upper electrode 126 are conformally formed on the lower electrode 120. The dielectric layer 124 and the upper electrode 126 further cover the top of the third support layer 110. The dielectric layer 124 is a high dielectric constant layer, and the material thereof is, for example, hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide (TiO), or lanthanum oxide (LaO). ), yttrium oxide (YO), yttrium oxide (GdO), yttrium oxide (TaO) or a combination thereof. The material of the upper electrode 126 is, for example, titanium nitride. The method of forming the dielectric layer 124 and the upper electrode 126 includes performing an atomic layer deposition (ALD) process.

In particular, the dielectric layer 124 can be formed only on the inner side and the bottom of the lower electrode 120 in the second opening 118 and formed by the presence of the second insulating layer 108 without performing the demolding step. On the inner side of the lower electrode 120 in the first opening 114. In the case where the demolding step is performed, since the second insulating layer 108 has been removed, the dielectric layer 124 may be formed on the outer side of the lower electrode 120 in the first opening 114.

Similarly, the upper electrode 120 can be formed only on the dielectric layer 124 on the inner and bottom sides of the lower electrode 120 in the second opening 118 and on the lower electrode in the first opening 114 without performing the demolding step. On the inner dielectric layer 124 of 120. In the case where the demolding step is performed, the upper electrode 120 may be formed on the dielectric layer 124 on the outer side of the lower electrode 120 in the first opening 114.

In other words, after performing the demolding step of FIG. 1E, the dielectric layer 124 and the upper electrode 126 may be further formed on the lower electrode 120 exposed in the demolding step to increase the surface area of the capacitor, thereby increasing the capacitance. So far, the fabrication of the stacked capacitor of the present invention has been completed.

Next, a tungsten layer (not shown) may be formed on the upper electrode 126 to seal the tops of the plurality of stacked capacitors. Then, a protective layer (not shown) is formed on the tungsten layer. The material of the protective layer is, for example, bismuth oxynitride, and the formation method thereof is, for example, a chemical vapor deposition process.

Hereinafter, the structure of the stacked capacitor of the present invention will be explained. The stacked capacitor includes a substrate 100, a first supporting layer 102, a first insulating layer 104, a second supporting layer 106, a second insulating layer 108, a third supporting layer 110, without performing the demolding step of FIG. 1E. Lower electrode 120, dielectric layer 124 and upper electrode 126. The first supporting layer 102, the first insulating layer 104, the second supporting layer 106, the second insulating layer 108, and the third supporting layer 110 are sequentially disposed on the substrate 100. The first support layer 106, the second insulating layer 108, and the third support layer 110 have a first opening 114 therein, and the first support layer 102 and the first insulating layer 104 have a second opening 118 therein, and the second opening 118 is in the first The width W2 in an insulating layer 104 is greater than the width W1 of the first opening (as shown in FIG. 1C). The lower electrode 120, the dielectric layer 124, and the upper electrode 126 are sequentially disposed in the second opening 118 and the first opening 114. The first opening 114 has a first height H1, the second opening 118 has a second height H2, and the first height H1 may be greater than, equal to, or less than the second height H2.

On the other hand, in the case where the demolding step of FIG. 1E is performed, as shown in FIG. 1F, the stacked capacitor includes a substrate 100, a first supporting layer 102, a first insulating layer 104, a second supporting layer 106, and a third support. Layer 110, lower electrode 120, dielectric layer 124, and upper electrode 126. The first support layer 102, the second support layer 106, and the third support layer 110 are sequentially disposed on the substrate 100. The first support layer 102, the second support layer 106, and the third support layer 110 are separated from each other, wherein the second support layer The first support layer 102 has a first opening 114 therein, and the first support layer 102 has a second opening 118 therein, and the first opening 114 communicates with the second opening 118. The lower electrode 120 is disposed on the inner side and the bottom of the second opening 118 and on the inner side of the first opening 114. The dielectric layer 124 is disposed on the inner side and the bottom of the lower electrode 120 in the second opening 118 and on the inner side and the outer side of the lower electrode 120 in the first opening 118. The upper electrode 126 is disposed on the inner and bottom dielectric layers 124 of the lower electrode 120 in the second opening 118 and on the inner and outer dielectric layers 124 of the lower electrode 120 in the first opening 114. In addition, the first insulating layer 104 is disposed between the first support layer 102 and the second support layer 106 . The width W2 of the second opening 118 in the first insulating layer 104 is greater than the width W1 of the first opening 114 (as shown in FIG. 1C). The first opening 114 has a first height H1, the second opening 118 has a second height H2, and the first height H1 may be greater than, equal to, or less than the second height H2.

In summary, the present invention utilizes a reinforcing structure composed of a first supporting layer (bottom support layer), a second supporting layer (middle supporting layer), and a third supporting layer (upper supporting layer) to increase the mechanical strength of the stacked capacitor. To avoid deformation or even dumping of the capacitor structure. In addition, the stacked capacitor of the present invention can have a higher height (that is, a larger capacitance value) than the conventional stacked capacitor by the arrangement of the second supporting layer (the middle supporting layer), and can be The height of an insulating layer and a second insulating layer controls the desired capacitance value. In addition, the surface area of the capacitor can be greatly increased by the back-off process (Fig. 1C) and the demolding step (Fig. 1E) of the present invention, thereby increasing the capacitance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

102. . . First support layer

104. . . First insulating layer

106. . . Second support layer

108. . . Second insulating layer

110. . . Third support layer

112. . . Hard mask layer

112a. . . Tantalum nitride mask layer

112b. . . Carbon mask

114. . . First opening

116. . . Clearance wall

118. . . Second opening

120. . . Lower electrode

122. . . Third opening

124. . . Dielectric layer

126. . . Upper electrode

W1, W2, W3. . . width

H1, H2. . . height

1A to 1F are schematic cross-sectional views showing a method of fabricating a stacked capacitor according to an embodiment of the invention.

2 is a top plan view showing a demolding step according to an embodiment of the invention.

100. . . Base

102. . . First support layer

104. . . First insulating layer

106. . . Second support layer

110. . . Third support layer

114. . . First opening

118. . . Second opening

120. . . Lower electrode

124. . . Dielectric layer

126. . . Upper electrode

H1, H2. . . height

Claims (14)

A method for manufacturing a stacked capacitor includes: sequentially forming a first supporting layer, a first insulating layer, a second supporting layer, a second insulating layer, a third supporting layer and a hard cover on a substrate Forming at least one first opening in the second supporting layer, the second insulating layer, the third supporting layer and the hard mask layer; forming a gap on the sidewall of the first opening; The spacer is a mask, and a second opening is formed in the first supporting layer and the first insulating layer; a retreating process is performed to increase a width of the second opening in the first insulating layer; a spacer; and a lower electrode, a dielectric layer and an upper electrode are sequentially formed in the second opening and the first opening. The method of manufacturing the stacked capacitor of claim 1, wherein in the step of forming the first opening, the remaining portion of the second supporting layer is at the bottom of the first opening, and in forming the second opening In the step, the second support layer remaining at the bottom of the first opening is simultaneously removed. The method for manufacturing a stacked capacitor according to claim 1, after forming the lower electrode and before forming the dielectric layer, further comprising performing a demolding step to remove the second insulating layer and expose Part of the lower electrode. The system for stacking capacitors as described in claim 3 The method of fabricating, wherein the demolding step comprises: forming at least one third opening in the second insulating layer and the third supporting layer, wherein the third opening overlaps with a portion of the first opening; and The third opening is filled with an etchant to remove the second insulating layer and expose a portion of the lower electrode. The method of manufacturing a stacked capacitor according to claim 1, wherein the materials of the first support layer, the second support layer and the third support layer each comprise tantalum nitride. The method of manufacturing a stacked capacitor according to claim 1, wherein the materials of the first insulating layer and the second insulating layer each comprise yttrium oxide. The method of manufacturing a stacked capacitor according to claim 1, wherein the hard mask layer comprises a tantalum nitride mask layer and a carbon mask layer disposed on the tantalum nitride mask layer. The method of manufacturing a stacked capacitor according to claim 1, wherein the material of the spacer comprises titanium nitride. A stacked capacitor includes a first supporting layer, a first insulating layer, a second supporting layer, a second insulating layer and a third supporting layer sequentially disposed on a substrate, wherein the second supporting layer The second insulating layer and the third supporting layer have a first opening, and the first supporting layer and the first insulating layer have a second opening therein, and the second opening is in the first insulating layer Width greater than the width of the first opening; A lower electrode, a dielectric layer and an upper electrode are sequentially disposed in the second opening and the first opening, wherein the third supporting layer is adjacent to and surrounds the first opening. The stacked capacitor of claim 9, wherein the materials of the first support layer, the second support layer and the third support layer each comprise tantalum nitride. The stacked capacitor of claim 9, wherein the materials of the first insulating layer and the second insulating layer each comprise yttrium oxide. The stacked capacitor of claim 9, wherein the first opening has a first height, the second opening has a second height, and the first height is greater than, equal to, or less than the second height. A stacked capacitor includes: a first supporting layer, a second supporting layer and a third supporting layer are sequentially disposed on a substrate, the first supporting layer, the second supporting layer and the third supporting layer are mutually Separating, wherein the second supporting layer and the third supporting layer have a first opening, the first supporting layer has a second opening therein, and the first opening is in communication with the second opening; An inner side and a bottom of the second opening and an inner side of the first opening; a dielectric layer disposed on the inner side and the bottom of the lower electrode in the second opening and disposed in the first opening An inner side and an outer side of the electrode; and an upper electrode disposed on the dielectric layer on the inner side and the bottom of the lower electrode in the second opening and the lower electrode disposed in the first opening On the inner side and the outer side of the dielectric layer, wherein the third supporting layer is adjacent to and surrounds the first opening, wherein the stacked capacitor further comprises a first one disposed between the first supporting layer and the second supporting layer An insulating layer, and a width of the second opening in the first insulating layer is greater than a width of the first opening. The stacked capacitor of claim 13, wherein the materials of the first support layer, the second support layer and the third support layer each comprise tantalum nitride.