TWI493690B - Improved bonding surfaces for direct bonding of semiconductor structures - Google Patents

Description

Improved bond surface for direct bonding of semiconductor structures

The present invention relates to a method of directly bonding semiconductor structures together and a bonded semiconductor structure formed using such methods.

Three-dimensional integration of two or more semiconductor structures can bring many benefits to microelectronic applications. For example, a three-dimensional spatial accumulation of microelectronic components can improve electrical performance and power consumption while reducing component footprint. For related information, see The Handbook of 3D Integration, edited by P. Garrou et al. (Wiley-VCH Publishing, 2008).

The three-dimensional spatial accumulation of the semiconductor structure can be achieved by attaching a semiconductor die to other one or more semiconductor dies (ie, die-to-die (D2D)), A semiconductor die is attached to one or more semiconductor wafers (ie, die-to-wafer (D2W)), and a semiconductor wafer is attached to one or more other semiconductor wafers (ie, wafer-to-wafer Round (W2W)).

The bonding technique used to bond a semiconductor structure to another semiconductor structure can be classified in different ways. One is to classify the two semiconductor structures by an intermediate material, and the second is the key interface. Whether electrons (ie, current) are allowed to be classified through the interface. By "direct bonding method" is meant a method of establishing a direct solid-to-solid chemical bond between two semiconductor structures to bond them together without the use of an intervening bonding material between the semiconductor structures. At present, a metal-to-metal direct bonding method has been developed, which can be a first half. A metal material on a surface of the conductor structure is bonded to a metal material on a surface of a second semiconductor structure.

The metal-to-metal direct bonding method can also be classified according to the temperature range at which each method operates. For example, some metal-to-metal direct bonding methods are performed at relatively high temperatures, thus causing at least partial melting of the metallic material at the bonding interface. Such direct bonding processes may not be suitable for bonding processed semiconductor structures containing one or more component structures, as their relatively high temperatures may adversely affect previously formed component structures.

The "hot press bonding" method is at a high temperature between 200 degrees Celsius (200 ° C) and about 500 degrees Celsius (500 ° C), usually between about 300 degrees Celsius (300 ° C) and about 400 degrees Celsius ( A direct bonding method of applying pressure between the bonding surfaces between 400 ° C).

Other direct bonding methods have also been developed, which can be carried out at temperatures of 200 degrees Celsius (200 ° C) or lower. For such direct bonding processes performed at 200 degrees Celsius (200 ° C) or lower, this specification is referred to as an "ultra-low temperature" direct bonding process. The ultra-low temperature direct bonding process can be carried out by careful removal of surface impurities and surface compounds (eg, native oxide layers), and by increasing the area of intimate contact between the two surfaces on an atomic scale. The area of intimate contact between the two surfaces is typically achieved by grinding the bonding surfaces to reduce the surface roughness to a value close to the atomic scale, applying pressure between the bonding surfaces to cause plastic deformation, or both grinding keys. The surface of the junction is then stressed to achieve such plastic deformation.

Some ultra-low temperature direct bonding methods can be carried out without applying pressure at the bonding interface between the bonding surfaces, but in other ultra-low temperature direct bonding methods, in order to obtain a suitable bonding strength at the bonding interface, the bonding surface can be applied. Pressure is applied to the bonding interface between the two. In the technical field of the present invention, an ultra-low temperature direct bonding method for applying pressure between bonding surfaces is generally referred to as "surface assisting". Help key or "SAB" method. Therefore, in the present specification, "surface auxiliary bonding" and "SAB" mean and include the first material against the second material at a temperature of 200 degrees Celsius (200 ° C) or lower, and at the keys Pressure is applied to the bonding interface between the junction surfaces to directly bond the first material to any direct bonding process of the second material.

In some cases, metal-to-metal bonding between active conductive components in a semiconductor structure can easily cause mechanical or electrical failures after a period of time, even if initially established between the conductive features of the semiconductor structures. Acceptable metals are also directly bonded to the metal. Although the cause is not fully understood, it is believed that such failure may be caused, at least in part, by one or more of the three related mechanisms. These three related mechanisms are strain localization, which may be caused by large grains, grain growth associated with deformation, and mass transfer at the bonding interface. Mass transfer at such bonding interfaces can be at least partially attributed to electromigration, phase separation, and the like.

Electromigration is the migration of metal atoms in a conductive material due to electrical current. Various methods of improving the electromigration lifetime of interconnect structures have been discussed in the art to which the present invention pertains. For example, J. Gambino et al. published the "Copper Interconnect Technology for the 32nm Node and Beyond" (Page 141-48) at the Custom Integrated Circuits Conference (CICC) held by IEEE in 2009, which discusses the improvement of the electromagnetic lifetime of copper connections. The method.

Figures 1A and 1B present a problem that may be encountered in a direct bonding method. 1A presents a semiconductor structure 10 that includes an element layer 12 that may comprise a plurality of element structures, although these structures are not shown in this simplified drawing. Dielectric material 14 is then disposed overlying the device layer 12, and a plurality of recesses 16 extend into the dielectric material 14 at locations where conductive components such as conductive pads, traces, and vias are to be formed. Therefore, the dielectric material 14 is deposited with a layer of conductive metal 18 (such as copper or copper alloy), so that the conductive metal 18 These grooves 16 will be filled. The conductive metal 18 is typically deposited in excess such that the layer of conductive metal 18 extends over the major upper surface 15 of the dielectric material 14, as shown in Figure 1A.

After depositing the conductive metal 18 to form the semiconductor structure 10 of FIG. 1A, the excess conductive metal 18 is removed from the major upper surface 15 of the dielectric material 14 to form the semiconductor structure 20 of FIG. 1B. Removal of the excess conductive metal 18 defines an element structure 22 that contains the conductive metal 18 in the grooves 16. For example, a chemical mechanical polishing (CMP) process can be used to remove excess conductive metal 18 from the major upper surface 15 of the dielectric material 14 and define the component structure 22. However, the CMP process used to remove excess conductive metal 18 from the major upper surface 15 of the dielectric material 14 may result in the exposed surface 23 of the component structures 22 being opposite the major upper surface 15 of the surrounding dielectric material 14. Depression. The exposed surfaces 23 may have an arcuate, concave shape as shown in FIG. 1B. In the technical field to which the present invention pertains, this phenomenon is commonly referred to as "dishing". Moreover, the CMP process used to remove excess conductive metal 18 from the major upper surface 15 of the dielectric material 14 may also cause the dielectric material 14 to be excessively removed at certain locations, such as being closely spaced. The location 26 between the component structures 22, and the random locations on the major upper surface 15 of the dielectric material 14, are such locations 28 as shown in FIG. 1B. In the art to which the present invention pertains, the dielectric material 14 is excessively removed below the reference plane of the major upper surface 15, commonly referred to as "abrasive." These dishing and abrasion phenomena may be caused by non-uniform CMP processes and/or uneven initial thickness of the layer of conductive metal 18 on the major upper surface 15 of the dielectric material 14.

The dishing of the exposed surface 23 of the component structures 22 and the local abrasion of the major upper surface 15 of the dielectric material 14 are for the semiconductor structure 20 of FIG. 1B and another semiconductor structure (not It can be shown that the bond strength and electrical connection established between the two in the subsequent direct bonding process may have a negative impact.

This summary is provided to introduce a series of concepts in a simplified form, which are further described in the embodiments of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the invention includes a method of directly bonding a first semiconductor structure to a second semiconductor structure. Providing a first semiconductor structure comprising at least one component structure and a dielectric material, the at least one component structure comprising a conductive material (such as a metal or a non-metallic conductive material, such as a crucible composed of different crystallites, Typically referred to as "polysilicon", the dielectric material is configured adjacent to the at least one component structure. The at least one element structure and the dielectric material may be exposed on a bonding surface of the first semiconductor structure. An exposed surface of the dielectric material may define a bonding plane of the first semiconductor structure on a bonding surface of the first semiconductor structure. The at least one element structure in the first semiconductor structure may protrude from the bonding plane of the first semiconductor structure a distance beyond the adjacent dielectric material. A second semiconductor structure is provided to include at least one component structure and a dielectric material, the at least one component structure comprising a conductive material, the dielectric material being disposed adjacent to the at least one component structure. The at least one component structure and the dielectric material may be exposed on a bonding surface of the second semiconductor structure. An exposed surface of the dielectric material may define a bonding plane of the second semiconductor structure on a bonding surface of the second semiconductor structure. Direct bond in one of metal to metal In the forming process, the at least one element structure in the first semiconductor structure may be directly bonded to the at least one element structure in the second semiconductor structure.

Other embodiments of the method of directly bonding a first semiconductor structure to a second semiconductor structure include providing a first semiconductor structure, providing a second semiconductor structure, and directly bonding a conductive material to one of the conductive materials (eg, metal In the case of a metal, a polycrystalline germanium, a polycrystalline germanium, a polycrystalline germanium, or the like, the plurality of constituent protrusions of at least one of the first semiconductor structures are directly bonded to at least one of the second semiconductor structures. A plurality of constituent protrusions of the structure. The first semiconductor structure can include at least one element structure including a conductive material, and a dielectric material disposed adjacent to the at least one element structure. The at least one component structure includes a plurality of constituent protrusions extending from a substrate structure. The constituent bumps and the dielectric material are exposed on a bonding surface of the first semiconductor structure. The dielectric material covers a portion of the at least one component structure between the constituent protrusions of the at least one component structure. An exposed surface of the dielectric material defines a bonding plane of the first semiconductor structure on a bonding surface of the first semiconductor structure. The second semiconductor structure also includes at least one element structure including a conductive material, and a dielectric material disposed adjacent to the at least one element structure. The at least one component structure includes a plurality of constituent protrusions extending from a substrate structure. The constituent bumps and the dielectric material are exposed on a bonding surface of the second semiconductor structure. Between the constituent protrusions of the at least one component structure in the second semiconductor structure, a dielectric material of the second semiconductor structure covers a portion of the at least one component structure. An exposed surface of the dielectric material defines a bonding plane of the second semiconductor structure on a bonding surface of the second semiconductor structure.

In other embodiments, the invention includes bonded semiconductor structures. The bonded semiconductor structures include a first semiconductor structure bonded to one of the second semiconductor structures. On a bonding surface of the first semiconductor structure, the first semiconductor structure includes at least one conductive element structure, and a dielectric material disposed adjacent to the at least one conductive element structure. On a bonding surface of the second semiconductor structure, the second semiconductor structure also includes at least one conductive element structure, and a dielectric material disposed adjacent to the at least one conductive element structure. The at least one conductive element structure of the second semiconductor structure is directly bonded to the at least one conductive element structure of the first semiconductor structure along a bonding interface between the conductive element structures of the two semiconductor structures. The dielectric material of the second semiconductor structure abuts the dielectric material of the first semiconductor structure along a bonding plane. A bonding interface between the at least one conductive element structure and the at least one conductive element structure of the second semiconductor structure is spaced apart from the bonding plane by a distance.

In further embodiments, the invention includes other bonded semiconductor structures having a first semiconductor structure bonded to one of the second semiconductor structures. On a bonding surface of the first semiconductor structure, the first semiconductor structure includes at least one conductive element structure, and a dielectric material disposed adjacent to the at least one conductive element structure. The at least one electrically conductive element structure includes a plurality of constituent protrusions extending from a substrate structure, and at least a portion of the dielectric material is disposed between the constituent protrusions of the at least one electrically conductive element structure. On a bonding surface of the second semiconductor structure, the second semiconductor structure also includes at least one conductive element structure, and a dielectric material disposed adjacent to the at least one conductive element structure. The at least one conductive element structure includes a plurality of constituent protrusions extending from a base structure, and at least a portion of the dielectric material is disposed in the second half The constituent protrusions of the at least one conductive element structure in the conductor structure. The dielectric material of the second semiconductor structure abuts the dielectric material of the first semiconductor structure along a bonding plane. The constituent protrusions of the at least one conductive element structure in the first semiconductor structure are directly bonded to the second semiconductor structure along the bonded interface between the constituent bumps of the two semiconductor structures The constituent protrusions of a conductive element structure.

The description of the present specification is not intended to be an actual description of any particular semiconductor structure, component, system or method, but is merely an idealized description for describing embodiments of the invention.

The use of any headings in this specification is not intended to limit the scope of the embodiments of the invention, which is defined by the scope of the following claims and their legal equivalents. The concepts described under any particular heading also generally apply to the rest of the specification.

This specification is hereby incorporated by reference. In addition, the cited references, regardless of how the description describes the features of the invention, are not admitted as prior art.

In the present specification, the term "semiconductor structure" means and includes any structure used in forming a semiconductor element. The semiconductor structure includes, for example, a die and a wafer (eg, a carrier substrate, an interposer, an element substrate, etc.), and two or more crystals in an assembled or composite structure that are combined with each other in a three-dimensional space. Particle, wafer or combination of die and wafer. The semiconductor structure also includes fully fabricated semiconductor components and intermediate structures formed during fabrication of the semiconductor components.

In the present specification, the term "processed semiconductor structure" means and includes any semiconductor structure having at least one or more component structures that have been partially formed. The processed semiconductor structure is a subset of the semiconductor structure, and all of the processed semiconductor structures are semiconductor structures.

In the present specification, the term "bonded semiconductor structure" means and includes any structure having two or more semiconductor structures attached thereto. The bonded semiconductor structure is a subset of the semiconductor structure, and all of the bonded semiconductor structures are semiconductor structures. In addition, one or more of the processed semiconductor structures in the bonded semiconductor structure are also processed semiconductor structures.

In the present specification, the term "elemental structure" means and includes any portion of a processed semiconductor structure that is, includes, or defines at least a portion of an active or passive component of a semiconductor component. Will be formed on or in the semiconductor structure. For example, the component structure includes active and passive components of the integrated circuit, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, conductive contact pads, and the like.

In the present specification, the term "through-wafer via" or "TWI" refers to and includes any conductive via that passes through at least a portion of a first semiconductor structure that spans the first semiconductor structure and a second semiconductor. An interface between the structures provides a structural and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical field of the present invention, there are other names for inter-wafer via connections, such as "through silicon vias", "through substrate vias", and "wafer vias". Through wafer vias), or the abbreviation of the above name, such as "TSV" or "TWV". The TWI typically passes through the semiconductor structure in a direction substantially perpendicular to one of the substantially planar major surfaces in a semiconductor structure (i.e., parallel to the "Z" axis).

In the present specification, the term "active surface" is used in relation to a processed semiconductor structure and refers to and includes one of the treated semiconductor structures exposed to a major surface that has been treated or will be processed to One or more component structures are formed in and/or on the exposed major surface of the semiconductor structure.

In the present specification, the term "back surface" is used in relation to a processed semiconductor structure and refers to and includes one of the treated semiconductor structures exposed to the major surface, which is the opposite of the active surface of the processed semiconductor structure. surface.

In some embodiments, the invention includes an improved method of directly bonding a first semiconductor structure to a second semiconductor structure to form a bonded semiconductor structure. In particular, embodiments of the invention may include forming a bonding surface of a semiconductor structure having a selected topographic pattern that is intentionally non-planar on an atomic scale to a direct bond Bonding processes, such as ultra-low temperature bonding processes (eg, surface assisted bonding (SAB) processes), provide bonding between the bonding surface of the semiconductor structure and the bonding surface of another semiconductor structure without the need for bonding An intermediate bonding material is used between the bonding surfaces of the two semiconductor structures.

A first set of exemplary embodiments of the present invention will now be described with reference to Figures 2A through 2K. Specifically, FIGS. 2A through 2D illustrate the fabrication of one of the first semiconductor structures 130 shown in FIG. 2D, and FIGS. 2E through 2I illustrate the fabrication of one of the second semiconductor structures 240 shown in FIG. 2I, and FIGS. 2J and 2K present the first A semiconductor structure 130 and the second semiconductor structure 240 are bonded together in a direct bonding process to form a bonded semiconductor structure 300 as shown in FIG. 2K.

Referring to Figure 2A, a semiconductor structure 100 is presented which may be formed as described above with reference to Figures 1A and 1B. Like the semiconductor structure 10 of FIG. 1A, the semiconductor structure 100 A dielectric material 102 can be included that includes one or more component structures, such as a transistor, vertically extending conductive vias, horizontally extending conductive traces, and the like. The semiconductor structure 100 includes an element structure 106 defined by a conductive metal 105 disposed within the recess 104 and containing the conductive metal 105. The recess 104 is formed or otherwise provided to the dielectric material 102. in.

The conductive material 105 may comprise industrial grade pure metal elements such as copper, aluminum, tungsten, tantalum, titanium, chromium, or a non-metallic conductive material such as doped polysilicon or the like, or the conductive material 105 may comprise An alloy or mixture of one or more of the foregoing metal elements. Moreover, the component structures 106 can comprise different regions having different compositions. For example, the recesses 104 may be lined with one or more layers of relatively thin metal to serve as a diffusion barrier layer, seed layer, etc., while a bulk conductive metal such as copper or copper alloy may substantially fill the recesses 104. The remaining main space.

As shown in FIG. 2A, the surface 107 of the element structures 106 exposed through the dielectric material 102 may have a concave shape in some embodiments, which may be caused by a dishing phenomenon. Observed when a chemical mechanical polishing (CMP) process is performed to remove excess conductive material 105 from the semiconductor structure 100 and define the element structures 106. Thus, the surface 107 of the element structures 106 can be relatively recessed as compared to the surface 103 of the adjacent surrounding dielectric material 102, as shown in Figure 2A.

As also shown in FIG. 2A, the exposed primary surface 103 of the dielectric material 102 may not be completely flat, and certain locations on the surface may have pits or depressions. For example, the surface 103 has a recess 108 at a location separate from the component structures 106. Such recesses 108 may also be used to remove excess conductive material 105 from the semiconductor structure 100 and define the component junctions. Due to the chemical mechanical polishing (CMP) process of structure 106, the effect of achieving a flat surface may be relatively poor due to the removal of different materials, which is less than a CMP process involving removal of a single homogeneous material (ie, in a CMP process) The entire surface being ground has the same composition).

Referring to FIG. 2B, a semiconductor structure 110 can be formed from the semiconductor structure 100 of FIG. 2A by providing an additional dielectric material 112 on the surface 103 of the dielectric material 102. As shown in FIG. 2B, the additional dielectric material 112 can be provided on the dielectric material 102 and have an average thickness sufficient to fill the recesses 108 and the recesses defined by the concave surfaces 107 of the component structures 106. In some embodiments, the additional dielectric material 112 can cover the dielectric material 102 such that the average distance between the exposed major surface 114 of the additional dielectric material and the surface 103 of the lower dielectric material 102 is at least approximately 10 nm (100 nm), at least about 500 nm (500 nm), or even at least about 1,000 nm (1,000 nm).

The additional dielectric material may comprise, for example, an oxide material such as one or more of cerium oxide, cerium nitride, cerium oxynitride, etc., and the additional dielectric material may utilize known chemical vapor deposition. The (CVD) process is deposited. The temperature at which the additional dielectric material is deposited can be selected to avoid damaging previously fabricated components.

As shown in FIG. 2B, in some embodiments, the additional dielectric material 112 can be deposited in a conformal manner on the semiconductor structure 100 of FIG. 2A such that the exposed major surface 114 of the additional dielectric material 112 is corresponding At the location of the depression of the surface of the lower semiconductor structure 100, one or more recesses are also included. For example, a recess 116 is formed on the exposed major surface 114 of the additional dielectric material 112 over the recess 108 of the surface 103 of the underlying dielectric material 102. Although not shown in FIG. 2B, other recesses may be formed in the exposed major surface 114 of the additional dielectric material 112 over the recessed surface 107 of the component structures 106.

Referring to FIG. 2C, after depositing the additional dielectric material 112, the exposed major surface 114 of the additional dielectric material 112 can be planarized to form another semiconductor structure 120. For example, the exposed main surface 114 of the additional dielectric material 112 may be subjected to a chemical etching process, a mechanical polishing process, a chemical mechanical polishing (CMP) process, or the like to process the additional dielectric material 112. The exposed main surface 114 becomes flat. The process for planarizing the exposed major surface 114 may involve removing a portion of the additional dielectric material 112. Thus, the original contour profile of the additional dielectric material 112 is represented by an imaginary line in Figure 2C. After planarizing the exposed major surface 114 of the additional dielectric material 112, the exposed major surface 114 is at least substantially planar (ie, smooth). Since the process used to planarize the exposed major surface 114 involves flattening the entire surface having the same composition (i.e., the composition of the additional dielectric material 112), the exposed major surface relative to the semiconductor structure 100 of FIG. 2A The smoothness of the exposed main surface 114 after smoothing is smoother.

In some embodiments, the exposed major surface 114 may have a root mean square (RMS) surface roughness after the planarization process of about one-half nanometer (0.5 nm) or less, about two tenths. Nano (0.2 nm) or lower, or even about one tenth of a nanometer (0.1 nm) or less.

As shown in FIG. 2D, after the exposed main surface 114 of the additional dielectric material 112 is planarized, an etching process can be performed on the semiconductor structure 120 of FIG. 2C to remove the additional dielectric material 112 and the dielectric underneath. the portion of the material 102, to cause the plurality of structure elements 106,103 preselected one protruding segment distance D ₁ from the exposed surface of the dielectric material 102 electrically, and a first semiconductor structure 130 is formed of the hereinbefore mentioned.

In some embodiments, the distance D ₁ can be between about one-half nanometer (0.5 nm) and about 50 nanometers (50 nm), between about 1 nanometer (1 nm) and about 10 nanometers ( Between 10 nm), or even between about 2 nm (2 nm) and about 7 nm (7 nm).

The exposed surface of the component structure 106 and the exposed major surface 103 of the surrounding dielectric material 102 together define a bonding surface of the first semiconductor structure 130, and the bonding surface will abut and bond to the surface shown in FIG. 2I. One of the second semiconductor structures 240 is complementary to the bonding surface.

Continuing to refer to FIG. 2D , the component structures 106 and the dielectric material 102 disposed adjacent to the component structures 106 are exposed on the bonding surface of the first semiconductor structure 130 . The exposed primary surface 103 of the dielectric material 102 defines a bonding plane 132 of the first semiconductor structure. The bonding plane 132 may include at least the bonding interface between the first semiconductor structure 130 and the second semiconductor structure 240 (FIG. 2I) after the first semiconductor structure 130 and the second semiconductor structure 240 are bonded together. Most of the plane along the extension is as detailed below with reference to Figures 2J and 2K.

Referring now to Figures 2E through 2I, an exemplary method that can be used to form the second semiconductor structure 240 of Figure 2I is described below.

Referring to FIG. 2E, a semiconductor structure 200 is provided. The semiconductor structure 200 is substantially similar to the semiconductor structure 100 of FIG. 2A and may include an element layer 201 containing one or more element structures, such as a transistor, vertically extending conductive vias, horizontally extending conductive traces, etc. Wait. The semiconductor structure 200 includes a dielectric material 202 and a plurality of element structures 206, wherein the dielectric material is disposed on the element layer 201, and the element structures are defined by a conductive metal 205 disposed in the recess 204. And containing the conductive metal 205, the grooves 204 are formed or Other ways are provided in the dielectric material 202. The conductive metal 205 may have a composition as described above with respect to the conductive material 105 of FIG. 2A.

As shown in FIG. 2E, the surface 207 of the component structures 206 exposed through the dielectric material 202 may have a concave shape in some embodiments, which may be caused by a dishing phenomenon. Observed when a chemical mechanical polishing (CMP) process is performed to remove excess conductive material 205 from the semiconductor structure 200 and define the element structures 206. Thus, the surface 207 of the element structures 206 can be relatively recessed as compared to the surface 203 of the adjacent dielectric material 202, as shown in Figure 2E.

As also shown in FIG. 2E, the exposed major surface 203 of the dielectric material 202 may not be completely flat, and certain locations on the surfaces may have pits or depressions. For example, the surface 203 has a recess 208 at a location that is separate from the component structures 206. Such recesses 208 may also be caused by a chemical mechanical polishing (CMP) process for removing excess conductive material 205 from the semiconductor structure 200 and defining the component structures 206, as discussed above.

Referring to FIG. 2F, a semiconductor structure 210 can be formed from the semiconductor structure 200 of FIG. 2E by providing an additional dielectric material 212 on the surface 203 of the dielectric material 202. As shown in FIG. 2F, the additional dielectric material 212 can be provided on the dielectric material 202 to have an average thickness sufficient to fill the recess 208 and the recess defined by the concave surface 207 of the component structures 206. The composition and composition (e.g., average thickness) of the additional dielectric material 212 can be as disclosed above with respect to the additional dielectric material 112 of FIG. 2B.

As shown in FIG. 2F, in some embodiments, the additional dielectric material 212 can be deposited in a conformal manner on the semiconductor structure 200 of FIG. 2E such that the exposed major surface 214 of the additional dielectric material 212 corresponds to the underlying semiconductor. The location of the depression of the surface of the structure 200 also includes a One or more depressions. For example, a recess 216 is formed over the exposed major surface 214 of the additional dielectric material 212 above the recess 208 of the surface 203 of the underlying dielectric material 202. Although not shown in FIG. 2F, other recesses may be formed in the exposed major surface 214 of the additional dielectric material 212 above the recessed surface 207 of the component structures 206.

Referring to FIG. 2G, after depositing the additional dielectric material 212, the exposed major surface 214 of the additional dielectric material 212 can be planarized as described above with respect to the additional dielectric material 112 portion of FIG. 2C to form another A semiconductor structure 220. For example, the exposed main surface 214 of the additional dielectric material 212 may be subjected to a chemical etching process, a mechanical polishing process, a chemical mechanical polishing (CMP) process, or the like to process the additional dielectric material 212. The exposed main surface 214 becomes flat. The process for planarizing the exposed major surface 214 may involve removing a portion of the additional dielectric material 212. Thus, the original profile profile of the additional dielectric material 212 is represented by an imaginary line in Figure 2G. After planarizing the exposed major surface 214 of the additional dielectric material 212, the exposed major surface 214 is at least substantially planar (ie, smooth). Since the process used to planarize the exposed major surface 214 involves planarizing the entire surface having the same composition (i.e., the composition of the additional dielectric material 212), the exposed major surface relative to the semiconductor structure 200 of FIG. 2E The smoothness, the exposed main surface 214 after the flattening process is smoother.

In some embodiments, the exposed major surface 214 may have a root mean square (RMS) surface roughness after the planarization process of about one-half nanometer (0.5 nm) or less, about two tenths. Nano (0.2 nm) or lower, or even about one tenth of a nanometer (0.1 nm) or less.

Referring to FIG. 2H, after the exposed major surface 214 of the additional dielectric material 212 is planarized, a masking material 232 can be provided over the planarized exposed major surface 214. The masking material 232 can be carpet-deposited over at least substantially the entire exposed major surface 214 and then patterned to form apertures 234 (eg, openings or other openings) through the masking material 232. The apertures 234 can be aligned with the component structures 206, as shown in Figure 2H. In addition, the apertures 234 have dimensions and shapes that correspond to the size and shape of the component structures 206 beneath them. The patterned mask material 232 helps to remove areas of the additional dielectric material 212 overlying the element structures 206 without removing other areas of the additional dielectric material 212.

The mask material 232 can comprise, for example, a polymeric photoresist material such as polymethyl methacrylate (PMMA) that can be rotatably deposited on an uncured photoresist material. Certain selected regions of the uncured photoresist material are then subjected to electromagnetic radiation through a mask with a pattern such that only selected regions of the uncured photoresist material are cured. The uncured regions of the photoresist material can then be removed to form a patterned mask material 232, as shown in Figure 2H. In other embodiments, the mask material 232 may comprise a hard mask material such as tantalum nitride (Si ₃ N ₄ ) and may be deposited using a chemical vapor deposition (CVD) process. A lithographic technique can then be used to impart a pattern on the deposited hard mask material to form a patterned mask material 232, as shown in Figure 2H. Different masking materials and methods of depositing such masking materials and imparting patterns thereto are known in the art to which the present invention pertains and may be employed in embodiments of the present invention.

After the additional dielectric material 212 is formed with the patterned mask material 232 on the planarized exposed main surface 214, it can be removed and overlaid on the component structures 206 through the patterned The aperture 234 of the mask material 232 exposes the additional dielectric material 212 region to form the semiconductor structure 240 shown in FIG. For example, the semiconductor structure 230 of FIG. 2H can be exposed to one or more etchants in a wet chemical etching process or a dry reactive ion etching (RIE) process. The composition of the one or more etchants can be selected to enable etching of the additional dielectric material 212 without removing the patterned mask material 232 and the component structures 206, or enabling them to be at a higher rate The additional dielectric material 212 is etched, relative to the rate at which the patterned mask material 232 and the element structures 206 are etched relative to the one or more etchants, such that additional layers overlying the element structures 206 At least substantially all of the electrical material 212 can be removed by the one or more etchants, and the patterned mask material 232 is not completely etched through.

The patterned mask material 232 can be applied to the component structures 206 and the additional dielectric material 212 exposed through the apertures 234 of the patterned mask material 232 is removed in an etch process. Removed as shown in Figure 2I. In some embodiments, the exposed major surface 214 of the additional dielectric material 212 may have a root mean square (RMS) surface roughness of about one-half nanometer (0.5 nm) or less after the etching process. About two tenths of a nanometer (0.2 nm) or less, or even about one tenth of a nanometer (0.1 nm) or less.

Moreover, in some embodiments, an etch process for overlying the additional dielectric material 212 that is exposed over the element structures 206 and exposed through the apertures 234 of the patterned mask material 232 may result in the etching process. The exposed surface 207 of the component structures 206 is recessed a predetermined distance D ₂ relative to the exposed surface 214 of the surrounding additional dielectric material 212, as shown in FIG. 2I.

In some embodiments, when the element structures comprise polysilicon, an etch process for removing oxides may cause the exposed surface 207 of the element structures 206 to have a shape of a recess or a shallow dish. In other embodiments, the component structures 206 may be recessed or dished because of a chemical mechanical polishing (CMP) process for removing excess conductive material 105 from the semiconductor structure 100 and defining the component structures 106. The shape is as described above with reference to Figure 2A.

As a non-limiting example, the distance D ₂ can be between about one tenth of a nanometer (0.1 nm) and about 10 nanometers (10 nm), between about 1 nanometer (1 nm) and about 10 nm. Between (10 nm), or even between about 2 nm (2 nm) and about 7 nm (7 nm).

In some embodiments, the distance D _{2 of} FIG. 2I can be at least substantially equal to the distance D _{1 of} FIG. 2D. However, in other embodiments, the distance D _{2 of} FIG. 2I may be less than the distance D _{1 of} FIG. 2D. For example, FIG. 2I can be interposed between the distance D ₂ of FIG. 2D of the distance D ₁ between about 80% to about 99%, or, more specifically, between the distance D ₁ of FIG. 2D is about 90% To about 98%.

The exposed surface 207 of the component structures 206 and the exposed major surface 214 of the surrounding additional dielectric material 212 together define a bonding surface of the second semiconductor structure 240 that will abut and bond to Figure 2D. The complementary bonding surface of the first semiconductor structure 130.

With continued reference to FIG. 2I, the element structures 206 and additional dielectric material 212 disposed adjacent to the element structures 206 are exposed on the bonding surface of the second semiconductor structure 240. The exposed primary surface 214 of the additional dielectric material 212 defines a bonding plane 242 of the second semiconductor structure 240. The bonding plane 242 may include the first semiconductor structure 130 and the second semiconductor structure 240 being bonded together, the first semiconductor structure 130 (FIG. 2D) and the second half At least a majority of the bonding interface between conductor structures 240 is along the plane of extension, as described in more detail below with respect to Figures 2J and 2K.

Referring to FIG. 2J, the first semiconductor structure 130 can be aligned with the second semiconductor structure 240. Thus, the component structures 106 of the first semiconductor structure 130 are aligned with the component structures of the second semiconductor structure 240. 206. As described above, the exposed surface of the component structure 106 and the exposed major surface 103 of the surrounding dielectric material 102 together define a bonding surface of the first semiconductor structure 130, and the exposed surface and surrounding of the component structures 206 The exposed primary surface 214 of the additional dielectric material 212 together define a bonding surface of the second semiconductor structure 240. In such a configuration, the top surface of the bonding surface of the first semiconductor structure 130 has a convex (male) configuration, that is, the element structures 106 protrude from the first semiconductor structure 130, and the second semiconductor structure The top surface of the bonding surface of 240 has a concave (female) configuration, that is, the element structures 206 are disposed in recesses extending into the second semiconductor structure 240.

Referring to FIG. 2K, the component structures 106 protruding in the first semiconductor structure 130 are inserted into the recesses of the second semiconductor structures 240 in which the component structures 206 are disposed. The bonding surface of the first semiconductor structures 130 The bonding surface of the second semiconductor structure 240 can be abutted. In this configuration, the component structures 106 of the first semiconductor structure 130 can directly abut the component structures 206 of the second semiconductor structure 240 corresponding thereto. In some embodiments, between the plurality of element structures 106 of the first semiconductor structure 130 and the element structures 206 of the second semiconductor structure 240, no intermediate bonding material (eg, an adhesive) is provided.

Then, the component structures 106 of the first semiconductor structure 130 can be directly bonded to the component structures 206 of the second semiconductor structure 240 to form the bond shown in FIG. 2K. Semiconductor structure 300. The bonding process results in the formation of a bond conductive structure comprising the component structures 106 and 206 that have been bonded together. The component structures 206 of the second semiconductor structure 240 may be directly bonded to the component structures 106 of the first semiconductor structure 130 in an ultra-low temperature direct bonding process of a conductive material to a conductive material, the bonding process being The temperature is about 200 degrees Celsius (200 ° C) or lower, or even at a temperature of about 100 degrees Celsius (100 ° C) or lower. In some embodiments, such an ultra-low temperature direct bonding process can be carried out at an ambient temperature of about room temperature (ie, without applying any additional thermal energy other than the temperature provided by the surrounding environment).

The first semiconductor structure 130 and the second semiconductor structure 240 may be processed to remove surface impurities and unwanted surface compounds prior to bonding the first semiconductor structure 130 to the second semiconductor structure 240.

In some embodiments, the first semiconductor structure 130 can be directly bonded to the second semiconductor structure 240 without applying pressure at the bonding interface between the bonding surfaces of the two. In other embodiments, pressure may be applied to the bonding interface between the bonding surfaces in certain ultra-low temperature direct bonding methods to achieve a suitable bonding strength at the bonding interface. In other words, in some embodiments of the present invention, the direct bonding method for bonding the component structures 106 of the first semiconductor structure 130 to the component structures 206 of the second semiconductor structure 240 may include a surface A bonding method for the auxiliary bond (SAB).

Continuing to refer to FIG. 2K, in some embodiments, between the component structures 106 of the first semiconductor structure 130 and the component structures 206 of the second semiconductor structure 240 that are bonded together, one can be identified. Bonding interface 302. Such a bonding interface 302 can only be seen by amplifying the cross-section prepared by the bonding semiconductor structure 300 in advance. In some embodiments, the bonding interface 302 may not be visible after the bonding process is completed, even with the aid of magnification. However, as shown in FIG. 2K, in some embodiments of the present invention, the keys between the component structures 106 of the first semiconductor structure 130 and the component structures 206 of the second semiconductor structure 240 are bonded. The junction interface 302 can be separated from a reference bonding interface plane 304 between the first semiconductor structure 130 and the second semiconductor structure 240. The reference bonding interface plane 304 is defined as the plane along which the major surface 214 of the dielectric material 212 of the second semiconductor structure 240 abuts the major surface 103 of the dielectric material 102 of the first semiconductor structure 130. The bonding interfaces 302 may be spaced apart from the reference bonding interface plane 304 by a distance at least substantially equal to the distance D _{1 of} FIG. 2D and/or the distance D _{2 of} FIG. 2I.

As previously mentioned, in some embodiments, the distance D _{2 of} FIG. 2I may be substantially equal to the distance D _{1 of} FIG. 2D. The distance D _{2 of} FIG. 2I is substantially equal to the distance D _{1 of} FIG. 2D. During the direct bonding process, the direct physical contact may be performed on the component structures 106 and the second semiconductor structure 240 of the first semiconductor structure 130. These element structures 206 are sufficiently established that [the physical contact] can be strengthened without occurring during subsequent tempering or other heat treatment processes that can improve the bonding between the aforementioned component structures due to material expansion. any problem.

Referring now to Figures 3A through 3K, other embodiments of the invention are described below. Specifically, FIGS. 3A to 3E illustrate the fabrication of one of the first semiconductor structures 450 illustrated in FIG. 3E, and FIGS. 3F to 3I illustrate the fabrication of one of the second semiconductor structures 570 illustrated in FIG. 3I, and FIGS. 3J and 3K present the first A semiconductor structure 450 and the second semiconductor structure 570 are bonded together in a direct bonding process to form a bonded semiconductor structure 600 as shown in FIG. 3K.

Referring to FIG. 3A, a semiconductor structure 400 can be formed via a mask material 418 provided on one of the semiconductor structures 120 of FIG. 2C. As a result, In addition to the presence of the patterned mask material 418, the semiconductor structure 400 is at least substantially similar to the semiconductor structure 120 (FIG. 2C) and includes an element layer 401 (which contains one or more component structures, such as a transistor, vertical An extended conductive via, a horizontally extending conductive trace, etc.), a dielectric material 402 over the component layer 401, and a conductive metal 405 disposed within the recess 404 and containing the conductive metal 405 The component structures 406 are formed or otherwise provided in the dielectric material 402. An additional dielectric material 412 having a planarized surface 114 is provided over the dielectric material 402 such that the additional dielectric material 412 fills any recess 408 in the major surface 403 of the dielectric material 402, and Any depression defined by the concave surface 407 of the element structures 406. The patterned mask material 418 can be disposed over the major surface 414 of the additional dielectric material 412.

The mask material 418 can be carpet deposited on at least substantially the entire major surface 414 of the additional dielectric material 412 and then patterned to form apertures 419 (eg, openings or other openings) through the mask material 418. The apertures 419 can be aligned with the component structures 406, as shown in Figure 3A. In some embodiments, the apertures 419 have a cross-sectional dimension that is small enough to allow two or more apertures 419 to be disposed over and aligned with the single component structure 406, as shown in FIG. 3A. The patterned mask material 418 helps to remove certain areas of the additional dielectric material 412 overlying the component structures 406 without removing other areas of the additional dielectric material 412.

The mask material 418 can comprise, for example, a polymeric photoresist material such as polymethyl methacrylate (PMMA) that can be rotatably deposited on an uncured photoresist material and then passed through One of the patterns is masked such that certain selected areas of the uncured photoresist material are subjected to electromagnetic radiation such that only selected portions of the uncured photoresist material are cured. The uncured regions of the photoresist material can then be removed to form a patterned mask material 418, as shown in Figure 3A. In other embodiments, the mask material 418 may comprise a hard mask material such as tantalum nitride (Si ₃ N ₄ ) and may be deposited using a chemical vapor deposition (CVD) process. A pattern can then be applied to the deposited hard mask material using lithography to form a patterned mask material 418, as shown in Figure 3A. Different masking materials and methods of depositing such masking materials and imparting patterns thereto are known in the art to which the present invention pertains and may be employed in embodiments of the present invention.

After the additional dielectric material 412 is patterned on the planarized major surface 414, the patterned mask material 418 can be removed over the component structures 406 through the apertures 419 of the patterned mask material 418. The additional dielectric material 412 regions are exposed to form the semiconductor structure 420 shown in FIG. 3B. For example, the semiconductor structure 400 of FIG. 3A can be exposed to one or more etchants in a wet chemical etching process or a dry reactive ion etching (RIE) process. The composition of the one or more etchants can be selected to etch the additional dielectric material 412 without removing the patterned mask material 418 and the conductive material 405, or to enable etching at a higher rate The additional dielectric material 412 is etched relative to the rate at which the patterned mask material 418 and the conductive material 405 are etched relative to the one or more etchants, such that the one or more etchants can be removed over the The additional dielectric material 412 is exposed over the component structures 406 and through the apertures 419 without completely etching through the patterned mask material 418.

With continued reference to FIG. 3B, after the etching process described above with reference to FIG. 3A, the patterned mask material 418 can be removed from the semiconductor structure to form the semiconductor structure 420 of FIG. 3B. As shown in the figure, the etching process is used to form a plurality of openings 422, each opening from which additional The exposed primary surface 414 of the dielectric material 412 passes through the additional dielectric material 412 and extends to the surface 407 of the component structures 406. After the recesses 422 are formed, a conductive material may be provided in the recesses 422.

Referring to FIG. 3C, a conductive material 432 may be deposited in the recesses 422 to form the semiconductor structure 430 shown in the figure. In some embodiments, excess conductive material 432 can be deposited such that the major surface 414 of the additional dielectric material 412 is covered with a layer of conductive material 432, as shown in Figure 3C.

In some embodiments, the conductive material 432 has a composition that is at least substantially the same as the composition of the conductive material 405 of the element structures 406. As an example of non-limiting properties, the electrically conductive material 432 may comprise industrial grade pure metal elements such as copper, aluminum, tungsten, tantalum, titanium, chromium, etc., or the electrically conductive material 432 may comprise one or more of the foregoing metallic elements. An alloy or mixture of the master, or the conductive material 432 may comprise a conductive semiconductor material (eg, polysilicon). Additionally, the electrically conductive material 432 can comprise different regions having different compositions. For example, the openings 422 may be lined with one or more layers of relatively thin metal to serve as a diffusion barrier layer, seed layer, etc., while a host conductive metal such as copper or copper alloy may be deposited on the thin layer or the thin layers. On the floor.

The conductive material 432 can be deposited by one or more of an electroless plating process, an electrolytic plating process, a physical deposition process (PVD), a chemical vapor deposition (CVD) process (including a low pressure CVD or LPCVD process).

Referring to FIG. 3D, after depositing additional conductive material 432, one or more of such as a chemical etching process, a mechanical polishing process, or a chemical mechanical polishing (CMP) process may be utilized to configure the additional dielectric material 412. Excess conductive material 432 on major surface 414 Divide to form the semiconductor structure 440 shown in FIG. 3D. For example, the excess conductive material 432 can be removed by performing a chemical mechanical polishing (CMP) process thereon, and the process can be performed until at least the major surface 414 of the additional dielectric material 412 is exposed through the conductive material 432. So far, as shown in FIG. 3D. After the excess conductive material 432 is removed, the conductive material 432 remains partially formed prior to passing through the openings 422 of the additional dielectric material 412. The remaining portions of the electrically conductive material 432 form integral protrusions 442 of the element structures 406. In other words, once the excess conductive material 432 is removed, each of the component structures 406 includes a plurality of constituent protrusions 442 defined by the conductive material 432 in the openings 422, the constituent protrusions 442 being from the recesses. One of the base structures defined by conductive material 405 in trench 404 extends.

A chemical mechanical polishing (CMP) process for removing excess conductive material 432 may also flatten the exposed major surface 414 of the additional dielectric material 412.

Referring to FIG. 3E, after removing the excess conductive material 432, at least a portion of the additional dielectric material 412 surrounding the constituent protrusions 442 may be removed from the side to cause the constituent protrusions 442 to be removed from the dielectric. the exposed surface of material 403 402, and / or the further dielectric material 412, the exposed surface 414 projecting one of the preselected segment distance D _3, as shown in FIG 3E, the first semiconductor structure 450 and the previously mentioned is formed.

In some embodiments, the distance D ₃ can be between about one-half nanometer (0.5 nm) and about 50 nanometers (50 nm), between about 1 nanometer (1 nm) and about 10 nanometers ( Between 10 nm), or even between about 2 nm (2 nm) and about 7 nm (7 nm).

The exposed surface of the component 442, the exposed surface of the protrusion 442, the exposed major surface 403 of the surrounding dielectric material 402, and/or the exposed surface 414 of the additional dielectric material 412 together define a bond of the first semiconductor structure 450. At the junction surface, the bonding surface will abut and bond to the complementary bonding surface of one of the second semiconductor structures 570 shown in FIG.

Continuing to refer to FIG. 3E, the constituent structures 406 of the component structures 406, the dielectric material 402 disposed adjacent to the constituent bumps 442, and the additional dielectrics disposed adjacent to the constituent bumps 442 Electrical material 412 is exposed to the bonding surface of the first semiconductor structure 450. In addition, as shown in FIG. 3E, portions of the additional dielectric material 412 are disposed adjacent to the component structures 406 and cover a portion of the component structures 406 between the constituent bumps 442. The exposed major surface 403 of the dielectric material 402 and the exposed major surface 414 of the additional dielectric material 412 define a bonding plane 452 of the first semiconductor structure 450. The bonding plane 452 can include at least the bonding interface between the first semiconductor structure 450 and the second semiconductor structure 570 (FIG. 3I) after the first semiconductor structure 450 and the second semiconductor structure 570 are bonded together. Most of the plane along the extension is as detailed below with reference to Figures 3J and 3K.

Referring now to Figures 3F through 3I, an exemplary method that can be used to form the second semiconductor structure 570 of Figure 3I is described below.

Referring to FIG. 3F, a semiconductor structure 500 is provided that is at least substantially similar to the semiconductor structure 440 of FIG. 3D. Thus, the semiconductor structure 500 can include an element layer 501 that contains one or more element structures, such as a transistor, vertically extending conductive vias, horizontally extending conductive traces, and the like. The semiconductor structure 500 includes a dielectric material 502 disposed on the element layer 501 and an element structure 506 at least partially surrounded by the dielectric material 502. The conductive metal 505 has a composition as described above with respect to the conductive material 105 of FIG. 2A.

The semiconductor structure 500 further includes an additional dielectric material 512 disposed on a surface 503 of the dielectric material 502. Each of the element structures 506 includes a plurality of constituent protrusions 542 extending from a substrate structure, the substrate structure being formed by a conductive material 505 extending into the recess 504 of the dielectric material 502. definition. The constituent protrusions 542 are defined by conductive material 532 disposed within openings 522 that pass through the additional dielectric material 512. The composition of the conductive material 532 may be the same as or different from the composition of the conductive material 505. As shown in FIG. 3F, one of the main surface 514 of the additional dielectric material 512 and the constituent protrusions 542 of the element structures 506 are exposed on the semiconductor structure 500.

Referring to FIG. 3G, a semiconductor structure 550 can be formed from the semiconductor structure 500 of FIG. 3F by providing an additional dielectric material 552 over the surface 514 of the additional dielectric material 512. As shown in FIG. 3G, another layer of additional dielectric material 552 may be provided on the additional dielectric material 512 to the desired average thickness. The composition and composition (e.g., average thickness) of the additional dielectric material 552 can be as disclosed above with respect to the additional dielectric material 112 portion of FIG. 2B.

After depositing the additional dielectric material 552, the exposed major surface 554 of the additional dielectric material 552 can be selectively planarized. For example, the exposed main surface 554 of the additional dielectric material 552 may be subjected to one or more of a chemical etching process, a mechanical polishing process, or a chemical mechanical polishing (CMP) process to cause the additional dielectric material 552 The exposed major surface 554 becomes flat. In some embodiments, the exposed major surface 554 may have a root mean square (RMS) surface roughness of about one-half nanometer (0.5 nm) after the planarization process or Lower, about two tenths of a nanometer (0.2 nm) or less, or even about one tenth of a nanometer (0.1 nm) or less.

Referring to FIG. 3H, after the exposed main surface 554 of the additional dielectric material 552 is planarized, a patterned mask material 562 may be provided on the planarized exposed main surface 554 to form the semiconductor shown in FIG. 3H. Structure 560. The masking material 562 can be carpet deposited over at least substantially the entire exposed major surface 554 and then patterned to form apertures 564 (eg, openings or other openings) through the masking material 562. The apertures 564 can be aligned with the constituent protrusions 542 of the component structures 506, as shown in Figure 3H. In addition, the apertures 564 have dimensions and shapes that correspond to the size and shape of the constituent protrusions 542 of the component structures 506 beneath them. The patterned mask material 562 facilitates removal of additional dielectric material 552 overlying the constituent bumps 542 of the component structures 506 without removing other regions of the additional dielectric material 552 and These component structures 506.

The mask material 562 can comprise, for example, a polymeric photoresist material such as polymethyl methacrylate (PMMA) that can be rotatably deposited on an uncured photoresist material and then passed through One of the patterns is masked such that certain selected areas of the uncured photoresist material are subjected to electromagnetic radiation such that only selected portions of the uncured photoresist material are cured. The uncured regions of the photoresist material can then be removed to form a patterned mask material 562, as shown in Figure 3H. In other embodiments, the mask material 562 may comprise a hard mask material such as tantalum nitride (Si ₃ N ₄ ) and may be deposited using a chemical vapor deposition (CVD) process. A lithographic technique can then be used to impart a pattern on the deposited hard mask material to form a patterned mask material 562, as shown in Figure 3H. Different masking materials and methods of depositing such masking materials and imparting patterns thereto are known in the art to which the present invention pertains and may be employed in embodiments of the present invention.

After the patterned mask material 562 is formed on the exposed major surface 554 of the additional dielectric material 552, the constituent protrusions 542 overlying the component structures 506 can be removed and transmitted through the patterned mask material 562. The additional dielectric material 552 regions exposed by the voids 564 are shown in the semiconductor structure 570 of FIG. 3I. For example, the semiconductor structure 560 of FIG. 3H can be exposed to one or more etchants in a wet chemical etching process or a dry reactive ion etching (RIE) process. The composition of the one or more etchants can be selected to enable etching of the additional dielectric material 552 without removing the patterned mask material 562 and the component structures 506, or enabling them to be at a higher rate Etching the additional dielectric material 552 in relation to the rate at which the patterned mask material 562 and the element structures 506 are etched relative to the one or more etchants, such that the one or more etchants can be removed and covered. The additional dielectric material 552 on the features 542 of the component structures 506 is not completely etched through the patterned mask material 562.

The patterned mask will be overlaid on the constituent protrusions 542 of the component structures 506, and the additional dielectric material 552 exposed through the apertures 564 of the patterned mask material 562 is removed in an etching process. Material 562 can be removed, as shown in Figure 3I. In some embodiments, the exposed major surface 554 of the additional dielectric material 552 has a root mean square (RMS) surface roughness of about one-half nanometer (0.5 nm) or less after the etching process. About two tenths of a nanometer (0.2 nm) or less, or even about one tenth of a nanometer (0.1 nm) or less.

In addition, an etching process for covering the constituent bumps 542 of the component structures 506 and removing the additional dielectric material 552 exposed through the voids 564 of the patterned mask material 562 may result in the etching process. The exposed surface of the component bump 542 of the component structure 506 is recessed a predetermined distance D ₄ relative to the exposed surface 554 of the surrounding additional dielectric material 552, as shown in FIG. 3I.

As a non-limiting example, the distance D ₄ can be between about one-half nanometer (0.5 nm) and about 50 nanometers (50 nm), between about 1 nanometer (1 nm) and about 10 nm. Between (10 nm), or even between about 2 nm (2 nm) and about 7 nm (7 nm).

In some embodiments, the distance D _{4 of} FIG. 3I can be at least substantially equal to the distance D _{3 of} FIG. 3E. However, in other embodiments, the distance D _{4 of} FIG. 3I may be greater than the distance D _{3 of} FIG. 3E. For example, the distance D in _{FIG. 3} 3E may be interposed between the distance D of FIG. 3I ₄ of about 80% to about 99%, or, more specifically, the distance D between FIG. 3I ₄ of about 90% To about 98%.

The exposed major surface 554 of the additional dielectric material 552 and the exposed surface of the constituent protrusions 542 of the component structures 506 together define a bonding surface of the second semiconductor structure 570, the bonding surface will be close to the bonding key The junction is bonded to the complementary bonding surface of the first semiconductor structure 450 of FIG. 3E.

Continuing to refer to FIG. 3I, the constituent bumps 542 of the element structures 506 and the additional dielectric material 552 are exposed on the bonding surface of the second semiconductor structure 570. The exposed primary surface 554 of the additional dielectric material 552 defines a bonding plane 572 of the second semiconductor structure 570. The bonding plane 572 can include the first semiconductor structure 450 and the second semiconductor structure 570 bonded Together, at least a majority of the bonding interface between the first semiconductor structure 450 (Fig. 3E) and the second semiconductor structure 570 is along the plane of extension, as described in more detail below with respect to Figures 3J and 3K.

Referring to FIG. 3J, the first semiconductor structure 450 can be aligned with the second semiconductor structure 570 such that the constituent protrusions 442 of the element structures 406 in the first semiconductor structure 450 are aligned with the second semiconductor structure 570. The component structures 506 are formed by protrusions 542. As described above, the exposed surface of the component 442 and the exposed main surface 403 of the surrounding dielectric material 402 together form the bonding surface of the first semiconductor structure 450, and the components 506 are formed. The exposed surface of the bump 542 and the exposed major surface 554 of the additional dielectric material 552 together form the bonding surface of the second semiconductor structure 570. In such a configuration, the top surface of the bonding surface of the first semiconductor structure 450 has a convex (male) configuration, that is, the constituent protrusions 442 of the element structures 406 protrude from the first semiconductor structure 450. The top surface of the bonding surface of the second semiconductor structure 570 has a concave (female) configuration, that is, the constituent protrusions 542 of the element structures 506 are disposed in the recesses of the second semiconductor structure 570. .

Referring to FIG. 3K, the protruding features 442 of the element structures 406 in the first semiconductor structure 450 are inserted into the recesses of the second semiconductor structure 570 in which the constituent protrusions 542 of the element structures 506 are disposed. The bonding surface of the first semiconductor structure 450 can abut the bonding surface of the second semiconductor structure 570. In this configuration, the protruding constituent protrusions 442 of the element structures 406 in the first semiconductor structure 450 may directly abut the constituent protrusions 542 of the element structures 506 in the second semiconductor structure 570 corresponding thereto. In some embodiments, the protruding constituents 442 of the component structures 406 in the first semiconductor structure 450 and the constituent bumps 542 of the component structures 506 in the second semiconductor structure 570 are not provided with any intermediate portions. Bonding material (eg adhesive).

Then, the constituent protrusions 442 of the element structures 406 in the first semiconductor structure 450 can be directly bonded to the constituent protrusions 542 of the element structures 506 in the second semiconductor structure 570 to form the structure shown in FIG. 3K. The semiconductor structure 600 is bonded. The bonding process results in the formation of a bond conductive structure comprising the component structures 406 and 506 that have been bonded together. The constituent protrusions 542 of the component structures 506 in the second semiconductor structure 570 can be directly bonded to the components of the component structures 406 in the first semiconductor structure 450 in an ultra-low temperature direct bonding process of conductive materials to conductive materials. The bumps 442 are implemented in an environment having a temperature of about 200 degrees Celsius (200 ° C) or less, or even at a temperature of about 100 degrees Celsius (100 ° C) or less. In some embodiments, such an ultra-low temperature direct bonding process can be carried out at an ambient temperature of about room temperature (ie, without applying any additional thermal energy other than the temperature provided by the surrounding environment).

Prior to bonding the first semiconductor structure 450 to the second semiconductor structure 570, the first semiconductor structure 450 and the second semiconductor structure 570 can be processed to remove surface impurities and unwanted surface compounds.

In some embodiments, the first semiconductor structure 450 can be directly bonded to the second semiconductor structure 570 without applying pressure at the bonding interface between the bonding surfaces of the two. In other embodiments, pressure may be applied to the bonding interface between the bonding surfaces in certain ultra-low temperature direct bonding methods to achieve a suitable bonding strength at the bonding interface. In other words, in some embodiments of the present invention, the constituent protrusions 442 of the element structures 406 in the first semiconductor structure are bonded to the constituent protrusions 542 of the element structures 506 in the second semiconductor structure 570. The direct bonding method may include a surface assist bonding (SAB) bonding method.

With continued reference to FIG. 3K, in some embodiments, the constituent protrusions 442 of the element structures 406 and the element structures 506 of the second semiconductor structure 570 are interposed in the first semiconductor structure 450 that has been bonded together. Between the protrusions 542, a bonding interface 602 can be identified. Such a bonding interface 602 can only be seen by amplifying the cross-section prepared by the bonding semiconductor structure 600 in advance. In some embodiments, the bonding interfaces 602 may not be visible after the bonding process is completed, even with the aid of magnification. However, as shown in FIG. 3K, in some embodiments of the present invention, the constituent protrusions 442 of the element structures 406 and the second semiconductor structures 570 in the first semiconductor structure 450 that have been bonded together The bonding interfaces 602 between the constituent protrusions 542 of the component structure 506 may be separated from the reference bonding interface plane 604 between the first semiconductor structure 450 and the second semiconductor structure 570. The reference bonding interface plane 604 is defined as the plane along which the major surface 554 of the dielectric material 552 of the second semiconductor structure 570 abuts the major surface 403 of the dielectric material 402 of the first semiconductor structure 450. The bonding interfaces 602 can be spaced apart from the reference bonding interface plane 604 by a distance at least substantially equal to the distance D _{3 of} FIG. 3E and/or the distance D _{4 of} FIG. 3I.

In an additional embodiment of the present invention, the bonded interface between the conductive element structures directly bonded together in the first and second semiconductor structures may be at least substantially substantially between the first and second semiconductor structures. The bonding interface is coplanar. 4A and 4B, examples of non-limiting properties of these embodiments are described below. In particular, Figures 4A and 4B present a first semiconductor structure 440 (as previously described with respect to Figure 3D) and a second semiconductor structure 500 (as previously described with respect to Figure 3F, which in some embodiments may be at least The direct bonding is substantially similar to the first semiconductor structure 440) to form the bonded semiconductor structure 700 shown in FIG. 4B.

Referring to FIG. 4A, the first semiconductor structure 440 can be aligned with the second semiconductor structure 500. Thus, the constituent protrusions 442 of the element structures 406 in the first semiconductor structure 440 are aligned with the second semiconductor structure 500. The component structures 506 are formed by protrusions 542. The exposed surface of the component 442 and the exposed major surface 414 of the additional dielectric material 412 together define at least one substantially flat bonding surface of the first semiconductor structure 440, and the component structures The exposed surface of the raised protrusion 542 of 506 and the exposed primary surface 514 of the surrounding additional dielectric material 512 together define at least one substantially flat bonding surface of the second semiconductor structure 500.

Referring to FIG. 4B, the bonding surface of the first semiconductor structure 440 may be in close contact with the bonding surface of the second semiconductor structure 500. Thus, the constituent protrusions 442 of the component structures 406 in the first semiconductor structure 440 will be The constituent protrusions 542 of the element structures 506 in the second semiconductor structure 500 are directly abutted and directly in physical contact without any intermediate bonding material (such as an adhesive) therebetween.

Then, the constituent protrusions 442 of the element structures 406 in the first semiconductor structure 440 can be directly bonded to the constituent protrusions 542 of the element structures 506 in the second semiconductor structure 500 to form the bonding of FIG. 4B. Semiconductor structure 700. The bonding process can be implemented as described above with reference to Figures 2K and 3K.

In the embodiments of FIGS. 4A and 4B, the constituent protrusions 442 of the component structures 406 and the components of the component structures 506 of the second semiconductor structure 500 in the bonded first semiconductor structure 440 The bonding interfaces 702 between the protrusions 542 may be at least substantially coplanar with a reference bonding interface plane 704 between the first semiconductor structure 440 and the second semiconductor structure 500, as shown in FIG. 4B. The reference keying interface plane 704 is defined as the second half The major surface 514 of the dielectric material 512 of the conductor structure 500 abuts the plane along the major surface 414 of the dielectric material 412 of the first semiconductor structure 440.

Exemplary embodiments of other non-limiting properties of the invention are described below:

Embodiment 1 : A method of directly bonding a first semiconductor structure to a second semiconductor structure, comprising: providing a first semiconductor structure including at least one device structure and a dielectric material, the at least one component The structure includes a conductive material and is exposed on a bonding surface of the first semiconductor structure, the dielectric material also being exposed on the bonding surface of the first semiconductor structure and configured to be at least with the first semiconductor structure An element structure is adjacent, on an bonding surface of the first semiconductor structure, an exposed surface of the dielectric material defines a bonding plane of the first semiconductor structure; causing the at least one element in the first semiconductor structure The structure protrudes from the bonding plane of the first semiconductor structure a distance beyond the adjacent dielectric material; providing a second semiconductor structure including at least one component structure and a dielectric material, the at least one component structure including Conductive material and exposed on a bonding surface of the second semiconductor structure, the dielectric material also exposed to the bond of the second semiconductor structure a surface of the junction and configured to be adjacent to the at least one element structure of the second semiconductor structure, on an bonding surface of the second semiconductor structure, an exposed surface of the dielectric material defines the second semiconductor structure a bonding plane; and in the direct bonding process of the conductive material to the conductive material, the at least one element structure in the first semiconductor structure is directly bonded to the at least one element structure in the second semiconductor structure.

Embodiment 2: The method of Embodiment 1, wherein the at least one element structure in the first semiconductor structure is caused to protrude from the bonding plane of the first semiconductor structure by a distance beyond the adjacent dielectric material from the first The semiconductor structure removes a portion of the dielectric material.

Embodiment 3. The method of Embodiment 2 wherein removing a portion of the dielectric material from the first semiconductor structure comprises etching the dielectric material.

The method of any one of embodiments 1 to 3, wherein causing the at least one element structure in the first semiconductor structure to protrude from a bonding plane of the first semiconductor structure a distance comprises causing the first semiconductor structure The at least one component structure protrudes from the bonding plane of the first semiconductor structure by a predetermined distance.

The method of any one of embodiments 1 to 4, further comprising causing the at least one element structure in the second semiconductor structure to be recessed from the bonding plane of the second semiconductor structure by a distance, recessed into One of the adjacent dielectric materials is a groove.

Embodiment 6: The method of Embodiment 5, wherein the at least one element structure in the second semiconductor structure is caused to be recessed from the bonding plane of the second semiconductor structure by a distance, recessed into a recess of the adjacent dielectric material The trench includes: depositing the dielectric material on the at least one component structure in the second semiconductor structure; and etching the dielectric material up to the at least one component structure.

Embodiment 7: The method of Embodiment 5 or Embodiment 6, wherein the at least one element structure in the second semiconductor structure is caused to be recessed from the bonding plane of the second semiconductor structure by a distance, recessed into the adjacent dielectric One of the grooves of the material includes a pre-selected distance of the at least one element structure of the second semiconductor structure from the bonding plane of the second semiconductor structure.

The method of any one of embodiments 5 to 7, wherein the at least one element structure of the first semiconductor structure is directly bonded to the second semiconductor structure, the at least one element structure comprising the first The at least one component structure of the semiconductor structure is inserted into a recess in the dielectric material of the second semiconductor structure.

The method of any one of embodiments 1 to 8, further comprising forming the at least one component of the first semiconductor structure to include a plurality of constituent protrusions, each of the constituent protrusions Both protrude from the bonding plane of the first semiconductor structure a distance beyond the adjacent dielectric material.

Embodiment 10: The method of Embodiment 9, further comprising: providing a dielectric material on the at least one component structure in the second semiconductor structure; and etching through the dielectric material to form a plurality of recesses, A recess extends through the dielectric material to the at least one component structure in the second semiconductor structure.

The method of embodiment 10, wherein the at least one element structure in the first semiconductor structure is directly bonded to the second semiconductor structure, the at least one element structure comprising the at least one of the first semiconductor structures Each of the plurality of constituent protrusions of the component structure is inserted into the second semiconductor structure and extends through the dielectric material to a corresponding complementary recess of the plurality of recesses of the at least one component structure.

The method of any one of embodiments 1 to 11, wherein the at least one component structure of the first semiconductor structure is directly bonded to the first semiconductor structure in a direct bonding process of a conductive material to a conductive material The at least one element structure in the second semiconductor structure includes direct bonding of the at least one element structure in the first semiconductor structure to the at least one element structure in the second semiconductor structure in a direct bonding process that is not hot pressing.

The method of any one of embodiments 1 to 12, wherein the at least one element structure in the first semiconductor structure is directly bonded to the first semiconductor structure in a direct bonding process of a conductive material to a conductive material The at least one component structure in the second semiconductor structure includes direct In the bonding process, the at least one component structure in the first semiconductor structure is directly bonded to the at least one component structure in the second semiconductor structure.

The method of any one of embodiments 1 to 13, wherein the at least one component structure of the first semiconductor structure is directly bonded to the first semiconductor structure in a direct bonding process of a conductive material to a conductive material The at least one element structure in the second semiconductor structure includes direct bonding of the at least one element structure in the first semiconductor structure to the at least one element structure in the second semiconductor structure in a surface assisted direct bonding process.

Embodiment 15: A method of directly bonding a first semiconductor structure to a second semiconductor structure, comprising: providing a first semiconductor structure including at least one component structure and a dielectric material, the at least one component The structure comprises a conductive material and a plurality of constituent protrusions extending from a base structure, the constituent protrusions are exposed on a bonding surface of the first semiconductor structure, and the dielectric material is also exposed on the first semiconductor structure a bonding surface, and the dielectric material is disposed adjacent to the at least one element structure of the first semiconductor structure, and the constituent bumps of the at least one element structure are covered in the first semiconductor structure Holding a portion of the at least one component structure, on an interface surface of the first semiconductor structure, an exposed surface of the dielectric material defines a bonding plane of the first semiconductor structure; providing a second semiconductor structure The method comprises at least one component structure and a dielectric material, the at least one component structure comprising a conductive material and a plurality of extending from a base structure Forming a protrusion, the constituent protrusions are exposed on a bonding surface of the second semiconductor structure, the dielectric material is also exposed on the bonding surface of the second semiconductor structure, and the dielectric material is configured to The at least one element structure of the second semiconductor structure is adjacent, and in the second semiconductor structure, the constituent protrusions of the at least one element structure cover a portion of the at least one element structure, and the second semiconductor structure Bond Surface, the exposed surface of the dielectric material defines a bonding plane of the second semiconductor structure; and the at least one component of the first semiconductor structure in a direct bonding process of the conductive material to the conductive material A plurality of constituent protrusions of the structure are directly bonded to a plurality of constituent protrusions of the at least one element structure in the second semiconductor structure.

The method of embodiment 15, wherein the providing the first semiconductor structure comprises forming a plurality of constituent protrusions extending from a base structure of the at least one element structure in the first semiconductor structure to form the constituent protrusions The method includes: providing the dielectric material on a base structure of the at least one element structure in the first semiconductor structure; etching through the dielectric material to form a plurality of grooves, the grooves passing through the dielectric material and Extending to a base structure of the at least one component structure in the first semiconductor structure; and providing a conductive material within the recesses to form a plurality of regions extending from the base structure of the at least one component structure in the first semiconductor structure Make up the bulge.

The method of embodiment 15 or embodiment 16, wherein the plurality of constituent protrusions of the at least one element structure in the first semiconductor structure are directly bonded in a direct bonding process of the conductive material to the conductive material And constituting the plurality of constituent protrusions of the at least one component structure in the second semiconductor structure, the at least one component in the first semiconductor structure in at least one of an ultra-low temperature direct bonding process and a surface assisted direct bonding process A plurality of constituent protrusions of the structure are directly bonded to a plurality of constituent protrusions of the at least one element structure in the second semiconductor structure.

Embodiment 18: A bonding semiconductor structure comprising a first semiconductor structure and a second semiconductor structure, the first semiconductor structure comprising: at least one conductive element structure on a bonding surface of one of the first semiconductor structures, and Configuring a bonding surface with the first semiconductor structure The at least one conductive element is adjacent to one of the dielectric materials; the second semiconductor structure comprises: at least one conductive element structure on a bonding surface of the second semiconductor structure, the at least one conductive material in the second semiconductor structure An element structure is bonded directly to the at least one conductive element structure of the first semiconductor structure along a bonding interface between the conductive element structures of the two semiconductor structures, and is configured to be bonded to the bonding surface of the second semiconductor structure The at least one conductive element structure is adjacent to a dielectric material, and the dielectric material of the second semiconductor structure abuts a dielectric material of the first semiconductor structure along a bonding plane; in the bonded semiconductor structure, The bonding interface between the at least one conductive element structure and the at least one conductive element structure of the second semiconductor structure is spaced apart from the bonding plane by a distance.

Embodiment 19: The bonded semiconductor structure of Embodiment 18, wherein the at least one conductive element structure of the first semiconductor structure and the at least one conductive element structure of the second semiconductor structure are at least substantially copper or a copper alloy Composition.

Embodiment 20: The bonded semiconductor structure of Embodiment 18 or Embodiment 19, wherein the at least one conductive element structure of the first semiconductor structure comprises a plurality of constituent protrusions extending from a base structure.

Embodiment 21: The bonded semiconductor structure of Embodiment 20, wherein the constituent protrusions of the at least one conductive element structure in the first semiconductor structure pass through a plurality of recesses in a dielectric material of the second semiconductor structure.

Embodiment 22: The bonded semiconductor structure of Embodiment 21, wherein the at least one conductive element structure of the second semiconductor structure comprises a plurality of constituent protrusions extending from a base structure, the at least one of the second semiconductor structures The constituent protrusions of the conductive element structure are directly bonded to the constituent protrusions of the at least one conductive element structure of the first semiconductor structure.

Embodiment 23: A bonding semiconductor structure comprising a first semiconductor structure and a second semiconductor structure; the first semiconductor structure comprising at least one conductive element structure and a dielectric material, wherein the at least one conductive element structure is a plurality of constituent protrusions extending from a surface of a semiconductor structure and extending from a substrate structure, the dielectric material being disposed adjacent to at least one conductive element structure on a bonding surface of the first semiconductor structure And at least a portion of the dielectric material is disposed between the constituent protrusions of the at least one conductive element structure in the first semiconductor structure; the second semiconductor structure includes at least one conductive element structure and a dielectric material, The at least one conductive element structure is on a bonding surface of the second semiconductor structure and includes a plurality of constituent protrusions extending from a substrate structure, the dielectric material being configured to bond surface with the second semiconductor structure At least one of the conductive elements is adjacent, and at least a portion of the dielectric material is disposed in the second semiconductor structure Between the constituent protrusions of one less conductive element structure, the dielectric material of the second semiconductor structure abuts the dielectric material of the first semiconductor structure along a bonding plane; in the bonded semiconductor structure, The constituent protrusions of the at least one conductive element structure in the first semiconductor structure are directly bonded to the at least one of the second semiconductor structures along the bonded interfaces between the constituent bumps of the two semiconductor structures The constituent protrusions of the conductive element structure.

Embodiment 24: The bonded semiconductor structure of Embodiment 23, wherein the constituent protrusions of the at least one conductive element structure in the first semiconductor structure and the at least one conductive element structure of the second semiconductor structure The bonded interfaces between the constituent bumps are separated from the bonding plane.

Embodiment 25: The bonded semiconductor structure of Embodiment 23, wherein the constituent bumps of the at least one conductive element structure and the second semiconductor structure are in the first semiconductor structure The bonded interfaces between the constituent protrusions of the at least one conductive element structure are at least substantially coplanar with the bonding plane.

The exemplified embodiments described above are not intended to limit the scope of the invention, and the invention is intended to be limited by the scope of the accompanying claims. Any equivalent embodiments are within the scope of the invention. In fact, various modifications of the invention, such as a substitute for a useful combination of the elements, in addition to those shown and described herein, will be apparent from the description of the specification. Become obvious. In other words, one or more of the features of any one of the exemplary embodiments described herein may be combined with one or more features of another exemplary embodiment described herein as an additional embodiment of the invention. Such modifications and embodiments are also within the scope of the appended claims.

100, 110, 120, 200, 210, 220, 230, 420, 430, 440, 550, 560‧ ‧ semiconductor structure

201, 401, 501‧‧‧ component layers

104, 204, 404, 504‧‧‧ grooves

105, 205, 405, 505‧‧‧ conductive metal

106, 206, 406, 506‧‧‧ component structure

103, 203, 503‧‧‧ surface

107, 207, 407‧‧‧ surface of component structure

Depression of the surface of the dielectric material below 108, 208, 408‧‧

116, 216‧‧‧ exposure to the main surface of the depression

112, 212, 412, 552‧‧‧ additional dielectric materials

114, 214, 554‧‧‧ exposed main surface

130, 400, 450, 500‧‧‧ first semiconductor structure

132, 242, 452, 572‧‧ ‧ bonding plane

102, 202, 402, 502, 512‧‧‧ dielectric materials

232, 418, 562 ‧ ‧ mask material

234, 419, 564‧‧ ‧ pores of the curtain material

240, 570‧‧‧second semiconductor structure

300, 600, 700‧‧‧bonded semiconductor structure

302, 602, 702‧‧‧ bonding interface

304, 604, 704‧‧‧ benchmark key interface plane

414, 514‧‧‧ main surface

432, 532‧‧‧ conductive materials

442, 542‧‧ ‧ raised

422, 522‧‧ ‧ openings

The invention will be more fully understood from the following detailed description of exemplary embodiments of the invention, which are illustrated in the accompanying drawings in which: FIGS. 1A and 1B are simplified cross-sectional views of a semiconductor structure For presenting dishing and abrading that may occur during preparation of the bonding surface of the semiconductor structure prior to direct bonding processes in which the semiconductor structures are directly bonded together; FIGS. 2A through 2K are simplified cross-sectional views of the semiconductor structure, It presents an embodiment of a direct bonding process in which the semiconductor structures are directly bonded together in the present invention; FIGS. 3A to 3K are simplified cross-sectional views of the semiconductor structure, showing other embodiments of the direct bonding process of the present invention; 4A and 4B are simplified cross-sectional views of a semiconductor structure showing additional embodiments of the direct bonding process of the present invention.

100‧‧‧Semiconductor structure

102‧‧‧ dielectric materials

103‧‧‧ surface

104‧‧‧ Groove

105‧‧‧Conductive metal

106‧‧‧Component structure

108‧‧‧ dent

107‧‧‧ Surface of component structure

Claims (15)

A method of directly bonding a first semiconductor structure to a second semiconductor structure, the method comprising: providing a first semiconductor structure comprising: at least one element structure comprising a conductive material, the at least one element structure being exposed a bonding surface on a bonding surface of the first semiconductor structure; and a dielectric material exposed on a bonding surface of the first semiconductor structure, the dielectric material being configured to be associated with the at least one component structure of the first semiconductor structure Adjacent, an exposed surface of the dielectric material defines a bonding plane of the first semiconductor structure on a bonding surface of the first semiconductor structure; causing the at least one component structure of the first semiconductor structure to be from the first a bonding plane of a semiconductor structure protruding a distance beyond the adjacent dielectric material; providing a second semiconductor structure comprising: at least one component structure including a conductive material, the at least one component structure being exposed to the first semiconductor a bonding surface on one of the structures; and a dielectric material exposed on the bonding surface of the second semiconductor structure, the dielectric A material is disposed adjacent to the at least one element structure of the second semiconductor structure, and an exposed surface of the dielectric material defines a bonding plane of the second semiconductor structure on a bonding surface of the second semiconductor structure Causing the at least one element structure of the second semiconductor structure to be recessed from the bonding plane of the second semiconductor structure by a distance, recessed into a recess of the adjacent dielectric material, comprising: Depositing an additional dielectric material on the at least one component structure in the second semiconductor structure; performing a planarization step on the additional dielectric material; and etching through the additional dielectric material up to the at least one component structure; The at least one element structure of the first semiconductor structure is directly bonded to the at least one element structure of the second semiconductor structure in a direct bonding process of the conductive material to one of the conductive materials. The method of claim 1, wherein the at least one element structure in the first semiconductor structure protrudes from the bonding plane of the first semiconductor structure by a distance beyond the adjacent dielectric material from the first semiconductor The structure removes a portion of the dielectric material. The method of claim 2, wherein removing a portion of the dielectric material from the first semiconductor structure comprises etching the dielectric material. The method of claim 1, wherein causing the at least one element structure in the first semiconductor structure to protrude from the bonding plane of the first semiconductor structure a distance comprises causing the at least one element structure in the first semiconductor structure to The bonding plane of the first semiconductor structure protrudes a predetermined distance of a segment. The method of claim 1, wherein the at least one element structure in the second semiconductor structure is recessed from the bonding plane of the second semiconductor structure by a distance, recessed into a recess of the adjacent dielectric material The method includes causing the at least one element structure in the second semiconductor structure to be pre-selected a distance from the bonding plane of the second semiconductor structure. The method of claim 1, wherein the at least one element structure in the first semiconductor structure is directly bonded to the second semiconductor structure, the at least one element structure comprising the at least one element in the first semiconductor structure A structure is inserted into the recess in the dielectric material of the second semiconductor structure. The method of claim 1, further comprising forming the at least one component of the first semiconductor structure to include a plurality of constituent protrusions, each of the constituent protrusions The bonding plane of the first semiconductor structure protrudes a distance beyond the adjacent dielectric material. The method of claim 7, further comprising: providing a dielectric material on the at least one component structure in the second semiconductor structure; and etching through the dielectric material to form a plurality of recesses, the recesses A trench extends through the dielectric material to the at least one component structure in the second semiconductor structure. The method of claim 8, wherein the at least one element structure of the first semiconductor structure is directly bonded to the second semiconductor structure, the at least one element structure comprising the at least one element of the first semiconductor structure Each of the plurality of constituent protrusions of the structure is inserted into the second semiconductor structure and extends through the dielectric material to a corresponding complementary recess of the plurality of recesses of the at least one component structure. The method of claim 1, wherein the at least one element structure in the first semiconductor structure is directly bonded to the at least one of the second semiconductor structures in a direct bonding process of the conductive material to the conductive material The component structure includes bonding the at least one component structure in the first semiconductor structure directly to the at least one component structure in the second semiconductor structure in a non-thermal compression direct bonding process. The method of claim 1, wherein the at least one element structure in the first semiconductor structure is directly bonded to the at least one of the second semiconductor structures in a direct bonding process of the conductive material to the conductive material The component structure includes bonding the at least one component structure in the first semiconductor structure directly to the at least one component structure in the second semiconductor structure in an ultra-low temperature direct bonding process. The method of claim 1, wherein the at least one element structure in the first semiconductor structure is directly bonded to the at least one of the second semiconductor structures in a direct bonding process of the conductive material to the conductive material The component structure includes direct bonding of the at least one component structure in the first semiconductor structure to the at least one component structure in the second semiconductor structure in a surface assisted direct bonding process. A method of directly bonding a first semiconductor structure to a second semiconductor structure, comprising: providing a first semiconductor structure comprising: at least one element structure including a conductive material, the at least one element structure comprising a plurality of constituent protrusions extending from the base structure, the constituent protrusions being exposed on a bonding surface of the first semiconductor structure; and a dielectric material exposed on the bonding surface of the first semiconductor structure, the A dielectric material is disposed adjacent to the at least one element structure of the first semiconductor structure, and wherein the portion of the at least one element structure of the at least one element structure covers a portion of the at least one element structure An exposed surface of the dielectric material defines a bonding plane of the first semiconductor structure on a bonding surface of the first semiconductor structure; and a second semiconductor structure is provided, comprising: at least one conductive material An element structure, the at least one element structure comprising a plurality of constituent protrusions extending from a base structure, the constituent protrusions being exposed a bonding surface on one of the second semiconductor structures; and a dielectric material exposed on the bonding surface of the second semiconductor structure, the dielectric material being configured to be associated with the at least one component structure of the second semiconductor structure Adjacent, and in the second semiconductor structure, the constituent protrusions of the at least one element structure cover a portion of the at least one element structure, and one of the dielectric materials is exposed on the bonding surface of the second semiconductor structure Defining a bonding plane of the second semiconductor structure; And a plurality of constituent protrusions of the at least one element structure in the first semiconductor structure are directly bonded to the plurality of at least one element structure in the second semiconductor structure in a direct bonding process of the conductive material to the conductive material Make up the bulge. The method of claim 13, wherein the providing the first semiconductor structure comprises forming a plurality of constituent protrusions extending from the base structure of the at least one element structure in the first semiconductor structure, and forming the constituent protrusions comprises Providing the dielectric material on a base structure of the at least one component structure in the first semiconductor structure; etching through the dielectric material to form a plurality of recesses, the recesses extending through the dielectric material and extending to a base structure of the at least one element structure in the first semiconductor structure; and providing a conductive material in the recesses to form a plurality of constituent protrusions extending from a base structure of the at least one element structure in the first semiconductor structure Start. The method of claim 13, wherein the plurality of constituent protrusions of the at least one element structure in the first semiconductor structure are directly bonded to the second semiconductor in a direct bonding process of the conductive material to the conductive material The plurality of constituent protrusions of the at least one component structure in the structure comprise at least one of the at least one component structure in the first semiconductor structure in at least one of the ultra-low temperature direct bonding process and the surface assisted direct bonding process The bumps are directly bonded to the plurality of constituent bumps of the at least one component structure in the second semiconductor structure.