TWI489856B - Dimensional image processing method - Google Patents

Description

Stereo image processing method

The present invention provides a stereoscopic image processing method, in particular, using a timing control signal to enable each image processor and each image source to synchronously output an image signal, and storing and resynchronizing the output image signal through a buffer, and then synthesizing the image signal with a multiplexer. It can be a single stereo image signal, which can reduce production costs by using only a low-cost dual-channel image processor.

With the advancement of technology, the display technology has evolved from black-and-white screens and color screens to LCD screens, and the screens have been gradually expanded from use to televisions to computers, mobile phones, etc., although they are everywhere in life. The trace of the screen, but in order to achieve better results on the display, there are manufacturers to play the screen for the original flat image, and constantly develop a stereo (3D) screen, which can enhance the viewer's visual experience and more The feeling of immersion.

The principle of the 3D screen is based on the pupil distance of about 6.5 cm from the left and right eyes of the average person. The two eyes form an angle with the object, so the objects seen by the left and right eyes will have a difference (parallax), so the two eyes receive After the different images are transmitted to the brain, the brain combines two different images to create a spatial and stereoscopic sense of the distance, and the naked-eye 3D screen produces a stereoscopic effect by allowing the viewer to see different images to form a parallax.

The optical technology used in the naked-eye 3D screen mainly includes twill grating sheets ( Slanted Lenticular Lens and Parallel Barrier (also known as Parallax Barrier); the technique of the twill lenticular sheet is to rotate the columnar plano-convex lens to a predetermined angle and closely adhere to the liquid crystal panel, which is refracted by a convex lens ( The principle of Refraction is the same as that of a general grating, and the purpose of rotating a predetermined angle is to eliminate the interference pattern generated by the Black Matrix between RGB Sub-Pixels; the technique of the parallax barrier is to use the diffraction of light ( Diffraction) principle, the multi-view image is transmitted through a whole row of tiny slits (Slits) and then diffracted to the viewer's eyes to produce stereoscopic vision.

However, no matter which optical technology is used, it is necessary to process the image into a composite image. Please refer to the fourth and fifth figures. The Pixels of the multi-view image at the same level are cut into stripes, and then sequentially. Arranged together, such as red, green, and blue images each containing 10% to 50% of the color, each cut into five equal parts (ie 10%, 20%, 30%, 40% and 50%), and then The images of the same proportion in each color are arranged together. The arrangement of the five groups is the composite image mode of the raster image, and the five groups of colors are arranged to correspond to the five columnar plano-convex lenses of the grating piece to operate; In practice, the images of different angles of view are used to replace the red, green and blue images above, and the level of pixels (Pixels) replaces the color ratio above, and how many pixels in the level position are combined into how many groups Perspective image and Corresponding to the same number of cylindrical plano-convex lenses.

In general, the more images are used to capture images at different angles, the more 3D images are visible in the synthesized 3D image, the more 3D effects they produce, such as large Size LCD TVs require 5 to 7 cameras, and larger displays such as advertising walls require 9 or more cameras. However, most of the image processors that are commercially available can only be processed. Single channel vedio input, with the gradual maturity and promotion of 3D technology, the dual channel video processor has also begun to appear on the market because the image processor is composed of very complicated logic circuits. The two-channel image processor occupies approximately twice the gate count of a single-channel image processor. The data line pins (IO) required for the two-channel image processor are also almost single channel images. Two times the processor, although there are no three-channel or more-channel image processors available, it can be known from the above that the image processor can be processed. The number of channels increases, not only increases the size of the wafer (die size), and increasing the number of pins increases manufacturing costs, and will also become a big problem on the heat sink.

In addition, according to the different Slanted Lenticular film, the pixel or sub-pixel should have a corresponding arrangement to see 3 The effect of D, because the high-resolution image transmission rate is very fast, taking Full HD, 1920x1080x3 resolution image as an example, the transfer rate of each primitive can be as high as 186Mhz, if the input channel of the image is not set in On the same control processor, there is a certain degree of difficulty in synchronization. Therefore, based on factors of synchronization and controllability, multiple channels are placed on the same processor.

However, if all of the multiple image processors are designed on the same wafer, different wafers should be designed and manufactured according to the needs of different users. For example, 3, 4, 5, 7, 9, or 16 channels must have different wafers. Because the development cost of each chip is very high, if there is no certain demand, the manufacturer will not develop and manufacture because it is cost-effective; if you design a processor with a higher number of predetermined channels (such as 16 channels), you can use it. An environment where the number of channels is lower than the number of channels reserved by the processor (such as 3, 5 or 7 channels), which reduces the development cost of the chip, but when the user uses the wafer for an environment lower than the predetermined number of channels of the processor The cost will increase and the user will not want to use it.

Therefore, the above-mentioned multi-channel 3D image processor has many problems and defects in production, manufacture and use, which is the goal that the inventors and those engaged in the industry desire to improve.

Therefore, in view of the above-mentioned shortcomings, the inventors have collected relevant information, evaluated and considered through multiple parties, and have accumulated many years of experience in the industry. The patents of the invention for designing such a low-cost stereo image processing method were designed and modified.

The main purpose of the present invention is to receive image signals of multiple image sources by combining two or more dual channel image processors, and the downstream image processor outputs timing control signals for upstream image processors and images. The source synchronously outputs the image signal, and uses two buffers of each image processor to store the synchronous output so that the state controller of the multiplexer selects one of the buffers to input the signal, and the multiplexer selects the pixel by the register setting. The image signal enables a plurality of low-cost dual-channel image processors to combine multiple image signals into a single stereo image signal, thereby reducing production costs.

The second object of the present invention is that the plurality of dual-channel image processors are combined by only the connection method, so that the number of different image sources can be increased, the number of image processors can be increased or decreased, and the arrangement can be easily changed, and each of them is changed. The register setting of the state controller set in the image processor is also simple and fast in design because the register setting has a fixed rule, which can reduce the production design and production cost.

In order to achieve the above objects and effects, the technical means and the configuration of the present invention will be described in detail with reference to the preferred embodiments of the present invention.

Please refer to the first figure, which is a block diagram of the image processor of the present invention. It can be clearly seen from the figure that it utilizes dual channels (dual The image processor 1 of the input image is provided with a first buffer 11 (Sync Buffer) connected to the first image input port 111 and a second buffer 12 (Sync Buffer) connected to the second image input port 121. The first buffer 11 and the second buffer 12 are electrically connected to the multiplexer 13 (Multiplexer), and the image processor 1 is provided with a front end control signal input port 14, a front end control signal output port 15, and a back end control signal. The input terminal 16 and the multiplexer 13 output the image signal rear end control and image signal output 埠17.

When the image processor 1 is used, the first image input port 111 and the second image input port 121 are respectively connected to two image sources, and the image source may be an image sensor or an image processor. After the output, the input format of the image source can conform to the parallel input port format of 8bits~16bits or the CCIR656/601 format of 8bits/16bits, because the first image input port 111 and the second image input port 121 input images. There may be cases of out-of-synchronization. Therefore, the first buffer 11 and the second buffer 12 are required to store the previously received primitives in order to perform synchronous output, and since the output clamp has a line of signal delay, its buffer At least two lines of signals can be stored.

The multiplexer 13 selects the input source of the signal as the first buffer by using the set value of the internal state controller 131. 11 or second buffer 12, such as: value 00 indicates end selection, value 01 indicates selection of first image input port 111, value 10 indicates selection of second image input port 121, and value 11 indicates that the value is not important, usually 11 Set to zero (output 8bits '0'), because the value 11 will be covered by other signals in the subsequent processing, no matter what the value will not affect the image processing results, its state controller 131 storage space (state control The value of register value storage) depends on the number of supported image sources. For example, if you support 16 image sources with red, blue and green elements, you need 3x16=48 storage space to store the input required for each state. The value of the element.

Furthermore, please refer to the first and second figures, which are block diagrams of the image processor of the present invention, and a block diagram of a preferred embodiment. It can be clearly seen from the figure that since the single image processor 1 can only receive two The image signal of the image source, when encountering three or more image sources, requires two or more image processors 1 to be processed, which is two or more through the connection method. The image processor 1 is connected, but there is a delay in the input time of the image signal, and each image processor 1 has a delay in processing the image signal, so the image processor 1 must be synchronized to perform smoothly. For processing, each image processor 1 uses front-end control signal input 、14, front-end control signal output 埠15, back-end control signal input 埠16, and back-end control and image signal output 来17, and upstream and downstream image processors. 1 is synchronized, so that a plurality of single image processors 1 that can only receive two image sources can perform multi-channel image processing, thereby achieving high-order image processing at low cost.

The general image source is controlled by Horizontal Synchronization (H-sync) and Vertical Synchronization (V-sync) to control its signal output. The arrival of each vertical sync signal represents one frame of image ( The beginning of frame or field), and the arrival of each level sync signal indicates the start of the output of an image line. When the level sync signal and vertical sync signal of all image sources are unified, all image sources can be synchronized. Input signal, but because it is connected by multiple dual-channel image processor 1, not all of the first image input port 111 and the second image input port 121 of the image processor 1 are directly connected to the image source, so the light The level synchronization signal and the vertical sync signal are not able to synchronize all of the image processors 1.

When the two or more image processors 1 are synchronized, the image processor 1 uses the front end control signal input port 14, the front end control signal output port 15 and the back end control signal input port 16 to transmit a synchronization signal (inter module Synchronization; I-sync and o-sync; hereinafter referred to as timing control signals) for image synchronization, front-end control The signal input port 14 is an input timing control signal, and the front end control signal output port 15 controls the first image input port 111 and the second image of the image processor 1 according to the timing control signal of the front end control signal input port 14 to generate an output timing control signal. The input port 121 synchronizes the two input images (such as the image input of the first image input port 111 and the second image input port 121), and the back end control signal input port 16 is the input timing control signal, the back end control and the image. The signal output 埠17 generates an output timing control signal and an image output signal according to the timing control signal of the back-end control signal input ,16, and the input timings of the front-end control signal input 埠14 and the back-end control signal input 埠16 may be different, that is, The first image input port 111 and the second image input port 121 can be out of synchronization with the unique backend control and video signal output port 17, thereby allowing two or more image processor 1 to be connected with each image processor 1 string. The position and signal processing speed are adjusted to synchronously output to the image processor 1 behind it.

Please refer to the first and second figures, which are block diagrams of the image processor of the present invention, and a block diagram of a preferred embodiment. As can be clearly seen from FIG. 2, two image processors 1 and 2 are used. The first processor 2 and the second processor 3 are connected to each other. The first processor 2 is connected to the first image source 21 and the second image source 22, and the second processor 3 is connected to the first processor 2 and the second processor 3. A third image source 31 is connected, and the front end control signal output port 15 of the first processor 2 supplies the same level synchronization signal and vertical synchronization signal to the first image source 21, the second image source 22, and the third image source 31. , so three images The source image is synchronously outputted, because the first image input port 111 and the second image input port 121 of the first processor 2 can simultaneously receive the image signals transmitted by the first image source 21 and the second image source 22, Synchronization is achieved, but the first image input port 111 of the second processor 3 is the image signal outputted by the first processor 2, because the first processor 2 takes time to process the image signal, so the first image input 埠111 The time when the image signal is received is later than the time when the second image input port 121 receives the image signal of the third image source 31, and the two image signals are not synchronized. However, all the image signals must be synchronized to acquire the correct 3D image, so The second processor 3 needs to store the image signal to which the third image source 31 is first transmitted by using the second buffer 12, and wait for the image signal of the first processor 2 to be received, and then fetch and synthesize.

When the first processor 2 is actually used, after receiving the image signals of the first image source 21 and the second image source 22, the first processor 2 is synthesized according to the setting of the state controller 131; and then input according to the backend control signal input 埠16. Timing, the backend control and video signal output 埠17 output signals to the first image input port 111 of the second processor 3, because the front end control signal input port 14 and the back end control signal input port 16 of the first processor 2 are simultaneously Receiving the front end control signal output 埠15 of the second processor 3, that is, the timing control signals of the first image input port 111 and the second image input port 121 of the second processor 3 are all from the second processor 3 The front end control signal output 埠15, and the first image input 埠111 data of the second processor 3 is smaller than the second image The data of the input port 121 is delayed by one line. In this way, the first processor 2 and the second processor 3 can synchronously process the image signals of the three image sources and synthesize them into 3D images, so when it is necessary to process 3D images of n channels When the processor is used, n-1 image processors 1 can be used as a construction block to perform a combination of connections.

Please refer to the first, second and third figures, which are block diagrams of the image processor of the present invention, a block diagram of a preferred embodiment, and a block diagram of another embodiment, which can be clearly seen from the figure. When the image source 21, the second image source 22, the third image source 31, the fourth image source 41, and the fifth image source 42 are provided, the first processor 2, the second processor 3, and the third processor may be disposed. 4 and 4 processors 5 and the like are used to synthesize 3D images, and the first image input port 111 and the second image input port 121 of the first processor 2 are respectively connected to the first image source 21 and the second image source 22 The first image input port 111 and the second image input port 121 of the second processor 3 are respectively connected to the back end control and image signal output port 17 of the first processor 2 and the third image source 31, and the third processor 4, the first image input port 111 and the second image input port 121 are respectively connected to the fourth image source 41 and the fifth image source 42, and the first image input port 111 and the second image input port 121 of the fourth processor 5 are Connected to the second processor 3 and the rear end control and video signal output port 17 and the third processor 4 rear end respectively Control and video signal output 埠17.

The fourth processor 5 is configured to output a video synchronization timing control signal to the second processor 3 and the third processor 4 by using the front end control signal output 埠15. The second processor 3 outputs the timing control signal for synchronizing the image to the first processor 2 by using the front-end control signal output 埠15, and the first processor 2 makes the first image source 21 and the second image in the above manner. The source 22 and the third image source 31 synchronously output image signals, and the third processor 4 also outputs the image synchronization timing control signals to the fourth image source 41 and the fifth image source 42 by using the front end control signal output 埠15. The image input is synchronized, and the first processor 2, the second processor 3, and the third processor 4 both output the rear end control and the image signal output 埠17 output signals to the downstream processor, so that the image signals can be synchronously processed and synthesized. For 3D images.

Since the actual 3D optical technology is not used (such as a lenticular sheet film, a twill grating film or a slit parallax), the image element output thereof also changes, and the following has a first image source 21 and a second image source 22, For the third image source 31, the fourth image source 41, and the fifth image source 42, the output of the primitive is illustrated, and the order of output of the primitives is:

The first image source 21 is A1r, A1g, A1b, A2r...

The second image source 22 is B1r, B1g, B1b, B2r...

The third image source 31 is C1r, C1g, C1b, C2r...

The fourth image source 41 is D1r, D1g, D1b, D2r...

The fifth image source 42 is E1r, E1g, E1b, E2r...

According to the design of the lenticular film, the output arrangement of our primitives should be adjusted accordingly. The output order may be A1r, B1g, C1b, D2r... or A1r, C1g, E1b, B2r...etc. Type, if the twill grating film is used, the output of the primitives will be different, such as: A1r, C1g, E1b, B2r... In this case, four image processors 1 can be used to meet the requirements of synchronous processing and output. However, when four image processor 1 are used, since the image signal synthesizing action to be processed by the original single image processor 1 is distributed to each image processor 1, it is necessary to control the image element synthesis of each image processor 1 to conform to the use. The output arrangement required by the person.

Therefore, the first register 20 of the internal state controller 131 of the first processor 2 needs to be set as follows. For the setting values, please refer to the above:

The register 00={01, 11, 11, 10} indicates that the output signals of the first to fourth points are sequentially outputted by the first image source 21, are not output, are not output, and the second image source 22 is output.

Register 01={11,01,11,11}, indicating that the output signals of the 5th to 8th points are not outputted, and the first image source 21 outputs, does not output, and does not output.

Register 02={10,11,01,11}, indicating that the output signal sequence of the 9th to 12th points is the output of the second image source 22, and is not output, and the first image source 21 outputs, and does not output.

Register 03={11,10,11,00}, indicating that the output signal of the 13th to 16th points is not output, the second image source 22 outputs, does not output, the first loop ends, so when it reaches the 16th point The next point will start from the beginning, and the output order of register 00 will be performed again.

It can be known from the above that the output signals of the first processor 2 are {A1r, X, X, B2r, X, A2b, X, X, B3b, X, A4g, X, X, B5g, X}, {A6r , X, X, B7r, X, A7b, X, X, B8b, X, A9g, X, X, B10g, X}, which are the image signals provided by the first image source 21 and the second image source 22 The desired pixel is captured in the preset data block.

The second register 30 of the second processor 3 needs to be set as follows: register 00={01,10,11,01}, indicating that the output signals of the first to fourth points are in the order of the first processor 2, and the third The image source 31 outputs, does not output, and the first processor 2 outputs.

Register 01={11,01,10,11}, indicating that the output signals of the 5th to 8th points are not outputted, the first processor 2 outputs, and the third image source 31 outputs, and does not output.

The register 02={01,11,01,10} indicates that the output signals of the 9th to 12th points are the output of the first processor 2, are not output, the output of the first processor 2, and the output of the third image source 31.

Register 03={11,01,11,00}, indicating that the output signals of the 13th to 16th points are not outputted, the first processor 2 outputs, does not output, the first loop ends, so when it reaches the 16th point The next point will start from the beginning, and the output order of register 00 will be performed again.

It can be known from the above that the output signal of the second processor 3 is {A 1r, C1g, X, B2r, X, A2b, C3r, X, B3b, X, A4g, C4b, X, B5g, X}, {A6r, C6g, X, B7r, X, A7b, C8r, X, B8b, X, A9g, C9b, X, B10g, X}, as can be seen from the above output signal, the second processor 3 is to take the desired pixel from the image signal provided by the third image source 31. The preset data block in the image signal output by the first processor 2 is included.

The third register 40 of the third processor 4 needs to be set as follows: register 00={11,11,10,11}, register 01={01,11,11,10}, register 02={11,01 , 11, 11}, register 03 = {10, 11, 01, 00}, 01 indicates the output of the fourth image source 41, 10 indicates the output of the fifth image source 42, 11 indicates no output, and 00 indicates the end of the first loop. It can be known from the above that the output signals of the third processor 4 are {X, X, E1b, X, D2g, X, X, E3g, X, D4r, X, X, E5r, X, D5b}, {X , X, E6b, X, D7g, X, X, E8g, X, D9r, X, X, E10r, X, D10b}, which are the image signals provided by the fourth image source 41 and the fifth image source 42 The desired pixel is captured in the preset data block.

The fourth register 50 of the fourth processor 5 needs to be set as follows: register 00={01,01,10,01}, register 01={10,01,01,10}, register 02={01, 10, 01, 01}, register 03 = {10, 01, 10, 00}, 01 indicates the output of the second processor 3, 10 indicates the output of the third processor 4, and 00 indicates the end of the first loop, from the above content It is known that the output signals of the fourth processor 5 are {A1r, C1g, E1b, B2r, D2g, A2b, C3r, E3g, B3b, D4r, A4g, C4b, E5r, B5g, D5b}, {A6r, C6g, E6b , B7r, D7g, A7b, C8r, E8g, B8b, D9r, A9g, C9b, E10r, B10g, D10b}, which are required for the image signals provided by the second processor 3 and the third processor 4 The first image source 21, the second image source 22, the third image source 31, the fourth image source 41, and the first image source 21 have been selected by the fourth processor 5 The image signals output by the five image sources 42 are processed and synthesized. Therefore, according to the actual 3D optical technology and the number of image sources, the registers in each image processor 1 can be set, thereby achieving multiple low cost. The dual-channel image processor 1 synchronously processes and synthesizes image signals of three or more image sources, and generates a 3D image signal, and the chip size does not increase because the number of pins does not need to be increased. In addition, the production cost can be reduced. Furthermore, since only a plurality of dual-channel image processor 1 combinations are used, it is only necessary to perform a plurality of image processor 1 arrangement combinations for different number of image sources, because the combination manner Simple and only need to change the register setting of the state controller. The register setting has a fixed rule setting, and the development cost can be reduced. low.

The above example is the register setting of each image processor 1 in the first image line, and the register settings of the image processor 1 in the second, third, fourth, fifth, and sixth image lines are also processed in the same manner, but The order of the second image line is like the first image line, but skips the first point and turns the first point to the last point (rotate to last point), while the sixth image line The register setting is the same as the order of the first image line. Therefore, all image lines are repeated based on every five image lines.

In addition, since the relative order of each image line is controlled, the image processor 1 needs to have a line rotation register (Line Rotate Register), thereby controlling the relative order between each image line, such as a line rotation register [ 〕={1,1,1,1,1}, 1 is a positive value. Positive values indicate that the next order is rotated to the left, and negative values indicate that the next order is rotated to the right, the line rotation register The value of only five, representing the five lines will return to the original order to form a loop.

The state controller 131 and the control register of the image processor 1 are exemplified. The number and detailed setting values are only a single example, so they can be added or subtracted according to the actual use state, and only have multiple image sources. The function of processing and synthesizing the video signal is not limited to the scope of the patent of the present invention, and other modifications and equivalent structural changes are equally included in the present invention. Within the scope of the patent, it is given to Chen Ming.

Therefore, the present invention is mainly directed to a stereoscopic image processing method, and two or more dual-channel image processors can be connected to receive image signals of a plurality of image sources, and the image processing signals are respectively used by the image processing signals. The image source synchronously outputs the image signal, and each image processor stores and resynchronizes the output image signal to the multiplexer by using two buffers, and the multiplexer can synthesize the image signal, thereby allowing the most downstream image processor to synthesize and output the stereo image. The signal, because only the low-cost dual-channel image processor is utilized, the production cost can be reduced as the main protection point, and only the plurality of image processors 1 need only change the register settings of the combined design and state controller 131. It can be applied to different numbers of image sources, and thus has the advantage of reducing the development cost. However, the above description is only the preferred embodiment of the present invention, and thus does not limit the scope of the patent of the present invention. The simple modifications and equivalent structural changes of the drawings are included in the scope of the patent of the present invention. Bright.

In summary, the above-described three-dimensional image processing method of the present invention can achieve its efficacy and purpose during implementation and operation, so the present invention is an invention with excellent practicability, and is an application for conforming to the invention patent, To file an application, I hope that the trial committee will grant the case as soon as possible to protect the intensive research and development of the inventor. If there is any doubt in the audit committee, please do not hesitate to give instructions to the inventor, and the inventor will try his best to cooperate with him.

1‧‧‧Image Processor

11‧‧‧First buffer

111‧‧‧First image input埠

12‧‧‧Second buffer

121‧‧‧Second image input埠

13‧‧‧Multiplexer

131‧‧‧State Controller

14‧‧‧ Front-end control signal input埠

15‧‧‧ Front-end control signal output埠

16‧‧‧ Backend Control Signal Input埠

17‧‧‧ Backend Control and Video Signal Output埠

2‧‧‧First processor

20‧‧‧First register

21‧‧‧ First image source

22‧‧‧Second image source

3‧‧‧second processor

30‧‧‧Second register

31‧‧‧ Third image source

4‧‧‧ third processor

40‧‧‧ third register

41‧‧‧Fourth image source

42‧‧‧ Fifth image source

5‧‧‧ fourth processor

50‧‧‧ fourth register

The first figure is a block diagram of the image processor of the present invention.

The second drawing is a block diagram of a preferred embodiment of the invention.

The third figure is a block diagram of another embodiment of the present invention.

The fourth picture is a schematic diagram of a conventional raster image (1).

The fifth picture is a schematic diagram of a conventional raster image (2).

2‧‧‧First processor

20‧‧‧First register

21‧‧‧ First image source

22‧‧‧Second image source

3‧‧‧second processor

30‧‧‧Second register

31‧‧‧ Third image source

Claims (6)

A stereo image processing method is connected by using two or more two-channel image processors to receive image signals of three or more image sources, and processing and synthesizing the image signals to output stereo (3D) The image processor has a first buffer connected to the first image input port and a second buffer connected to the second image input port, and the first buffer and the second buffer are electrically connected to the multiplexer. The image processor has a front-end control signal input port, a front-end control signal output port, a back-end control signal input port, and a multiplexer output image signal rear-end control and image signal output port, and the processing method includes: The image processor front-end control signal input 接收 is a receiving input timing control signal, and each downstream image processor front-end control signal output 埠 outputs a timing control signal for synchronizing the image input to each of the upstream image processors, and the most upstream image processor Then, the front-end control signal output/output timing control signal allows the image source of the image processor and the downstream image processor to simultaneously output the image. The image processor and the upstream image processor use the back end control and the image signal output to output the timing control signal and the image output signal to the downstream image processors, and each image processor uses the first buffer and the second buffer to store and receive the signal. The picture element is synchronously outputted to the multiplexer, and the multiplexer selects the input source of the signal as the first buffer or the second buffer by using the set value of the internal state controller, and the register settings of each internal state controller will be two images. The required pixel in the signal is placed in the preset data block for stereo image synthesis, and then the rear control and image signal output. 埠 Output image signal. The method of processing a stereoscopic image according to claim 1, wherein the image processor is provided with a linear rotation register for controlling the relative order between each image line, and the relative order includes rotating to the left and right and the order. Loop. The stereoscopic image processing method of claim 1, wherein the first buffer and the second buffer of each image processor can store at least two lines of signals. The stereoscopic image processing method of claim 1, wherein the state controller storage space is three times larger than the number of image sources. The method of processing a stereoscopic image according to the first aspect of the invention, wherein the front end control signal output port is a timing control signal for generating an output according to an input timing control signal of the front end control signal input port. The method of processing a stereoscopic image according to claim 1, wherein the backend control and the image signal output generate an output timing control signal and an image output signal according to a timing control signal of the backend control signal input.