TWI489448B - Apparatus and computer-implemented method for low power voice detection, computer readable storage medium thereof, and system with the same - Google Patents

Description

Device and system for low-power voice detection and computer implementation method, and computer readable storage medium

Embodiments of the invention are generally associated with audio processing. More particularly, embodiments relate to speech recognition.

Voice commands and continuous speech recognition are important for mobile computing devices with limited keyboard functions. However, continuous listening to possible speech in the environment can result in considerable power consumption, so most systems require the user to enter commands before starting to listen. This approach can be inconvenient and limits the feasibility of many potential applications.

The device mentioned in the embodiment of the present invention includes logic for storing the time domain audio signal in a memory set to operate according to a first clock frequency and a first voltage, and according to a second time The pulse frequency and a second voltage are used to perform a Fast Fourier Transform (FFT) operation on the time domain audio signal to generate a frequency domain audio signal.

The computer implemented method mentioned in the embodiments of the present invention includes a time domain audio signal recorded at a first clock frequency and a first voltage. Performing a fast Fourier transform (FFT) operation on the time domain audio signal of the second clock frequency to generate a frequency domain audio signal, wherein the first clock frequency is faster than the second clock frequency.

Embodiments of the invention may include a computer readable computer having a set of instructions Taking the storage medium, if executed by the processor, causing a computer to record the time domain audio signal of the first clock frequency and the first voltage; and performing the fast Fourier transform on the time domain audio signal of the second clock frequency ( FFT) to generate a frequency domain audio signal, wherein the first clock frequency is faster than the second clock frequency.

Referring now to FIG. 1, an example of a block diagram of an embodiment of a speech recognition system 100 is shown. The system can include a pre-processing module 101 configured to capture audio signals, a frontend processing module 102 configured to process audio signals and detect any The vocal information within the audio signal, and a backend processing module 103, are configured to analyze vocal information and perform operations related to vocal information. It should be noted that the audio signal can include background noise and vocal information.

The pre-processing module 101 can include a recorder 105 (eg, a microphone) for capturing audio signals such as Pulse Density Modulation (PDM) information streams. The PDM information stream can include time domain audio signals in a digital format. The pre-processing module 101 can include a pulse density modulation (PDM) to pulse-code modulation (PCM) converter 110 configured to receive the PDM information stream and generate a PCM information stream. The PCM stream can be viewed as a digital representation of the PDM stream. The PCM stream includes unencoded or raw information. The PCM information stream can be received directly in some embodiments. For example, the recorder 105 can include an integrated function that produces a stream of PCM information.

The front end processing module 102 (also referred to as a voice activity detection (VAD) module) may include a framing and windowing module 115 configured to receive PDM-PCM The information flow of the converter 110 is divided into sub-windows. The sub-frame and sub-window module 115 can frame and divide the information into a plurality of frames according to a sampling rate and a frame size (as shown in FIG. 2). For example, the sample rate can be set to 16 kHz and the frame size can be set to 32 ms (milliseconds). Depending on the implementation, different sampling rates and different frame sizes can be used. For some embodiments, frames may overlap each other, but with non-overlapping windows. For example, two consecutive frames of 32 ms size can have 22 ms overlap, while 10 ms are non-overlapping windows. Taking the 16 kHz sampling rate and the 32 ms frame size as an example, the number of samples per frame can be 16 × 32 = 512.

A fast Fourier transform module (FFT module) 120 can be configured to receive frames of the PCM information stream and perform conversions that convert the frames from the time domain representation to the frequency domain representation. The frequency domain representation of the audio signal can show the energy or signal level for each given frequency band in a range of frequencies (as shown in Figure 2). After the FFT module 120 performs the conversion operation, the noise estimation and suppression module 125 can analyze the audio signal represented by the frequency domain and filter out any noise information that is not in the same frequency band as the vocal information. . For some embodiments, the noise estimation and suppression module 125 can be a programmable band-pass filter. In general, the frequency band of a human voice is between approximately 20 Hz and 7 KHz (referred to herein as the human voice band). Noise estimation and suppression mode Group 125 can be configured to detect any energy or signal level outside of the human voice band and to suppress it as out-of-band energy.

The numerical nature between vocals and background noise may vary. For some embodiments, the noise estimation and suppression module 125 can assume that the usual form of the human voice is a short burst followed by a pause, which can generally be expressed as a short burst of high amplitude energy, followed by a low amplitude energy, This is used to distinguish between vocals and background noise. The vocal energy type is different from the background noise. The average energy amplitude of the latter will remain similar, or it will change slowly from time to time. Therefore, it is possible to track and estimate background noise for a period of time.

A human voice detection module 130 can be configured to use background noise estimation to determine if a human voice is present in the human voice band. For some embodiments, the vocal detection module 130 can determine the total energy in the frame represented by the frequency domain, compare it to the estimated noise energy, and determine if a human voice is present within the frame. For example, when the total energy is greater than the background noise energy multiplied by a threshold, there may be a human voice information 135. When the total energy is less than or equal to the background noise energy, the vocal information 135 may not exist. When the vocal information 135 does not exist, the operation of the front-end processing module 102 can continue to perform noise estimation and suppression of the next frame by the noise estimation and suppression module 125.

The backend processing module 103 can include a voice processing module 140 configured to receive the vocal information 135 from the front end processing module 102 and determine possible packets in the vocal information 135. Commands or instructions. The speech processing module 140 can operate in accordance with the determined command or instruction.

Next, please refer to Figure 2, which is used to represent the energy and frame examples associated with audio signals. The chart 200 includes the energy of the audio signal captured by the recorder 105 (as shown in Figure 1) for a period of time. The vertical axis 205 of the graph 200 may represent the amplitude of the energy, while the horizontal axis 210 may represent time. For some embodiments, the audio signal can be split into a number of overlapping frames, for example, frames 215, 220, and 225. In this example, each of the frames 215, 220, and 225 has a length of 32 ms, which is different from each other by a 10 ms non-overlapping window 230. The FFT module 120 of FIG. 1 may first process a frame 215 covering a window of 0 ms to 31 ms. After 10 ms, the FFT module 120 can process the frame 220 covering the window of 10 ms to 41 ms. Then, after 10 ms, the FFT module 120 can process the frame 225 of the window covering 20 ms to 51 ms.

If a sampling rate of 16 kHz is employed, each frame 215, 220, and 225 can include 512 samples. Depending on the sampling rate and frame size selected, there may be a different number of samples, but usually a multiplier of two. For some embodiments, the FFT module 120 (Fig. 1) should be able to perform each frame conversion operation (from time domain representation to frequency domain representation) in a time similar to a non-overlapping window, such as 10 ms. . In other embodiments, the FFT module should be able to perform the conversion operation for a short period of time in a non-overlapping window. For example, an FFT module may only require 10% (or 1 ms) of 10 ms to complete processing. The operation of the FFT module can be as follows: Show: X(k)=FFT(X(t)) Equation 1

Where X(k) is the frequency domain representation of the audio signal, X(t) is the time domain representation of the audio signal, and the value of k varies from 1 to the total number of bands (eg, 512), and t represents time. The result of Equation 1 may be a 512-point FFT (according to an example of 512 samples). The result of the FFT operation is then filtered by the noise estimation and suppression module 125 (Fig. 1) to remove any extraneous noise. The filtering operation of the noise estimation and suppression module 125 can be expressed by the following equation: Y(k)=H(k)*X(k) Equation 2

Where Y(k) is the result of the filtering operation, H(k) is the filtering function, X(k) is the frequency domain representation of the audio signal, and the value of k varies from 1 to the total number of bands (for example, 512). The filtering operation is to pass the frequency domain representation X(k) of the audio signal through the filter to remove any extra-frequency noise.

Referring to Figure 3, which is a block diagram showing an exemplary embodiment of noise suppression. Once the operation is complete, one or more noise suppression operations can be applied to remove or suppress any non-speech noise. For some embodiments, each noise suppression operation may be associated with a different noise suppression technique. A number of different techniques can be combined to perform noise suppression operations. Referring to FIG. 3, the filtered information 305 is transmitted to the first noise suppression module 310. It should be understood that a series of frames having the same size can be used to transmit the filtered information 305 to the first noise suppression module 310, and the result information generated by the first noise suppression module 310 can be transmitted to the first Two noise suppression module 315, and so on, until the Nth noise suppression module 320 generates an enhanced audio signal (referred to herein as enhanced audio information) 325. For example, the first noise suppression module 310 can employ a delay and sum beam former with a fixed coefficient, and the second noise suppression module 315 can employ spectral tracking and Sub-band domain Wiener filtering technology. After the noise suppression operation process of FIG. 3 is utilized, the enhanced audio signal 325 may have a higher signal to noise ratio than the received audio signal.

The enhanced audio signal 325 can include a string of frames of the same size. The vocal detection module 130 in FIG. 1 can process the enhanced audio signal 325 to detect the presence of a human voice. Depending on the implementation, the manner in which the enhanced audio signal 325 is processed may vary. The following is an example of a pseudo code of the first algorithm that the vocal detection module 130 can use when processing the enhanced audio signal 325:

Task 1: For each frame of the enhanced audio signal 325, determine the total energy L(n) as: L(n) = (abs(FFT Output)* H) ² where "abs" is an absolute function (absolute function) "FFT Output" is the operation result of the FFT module 120, and H is a filter function.

Task 2: For each frame of the enhanced audio signal 325, estimate the background noise (or noise minimum energy) Lmin(n) as: If (L(n) > Lmin(n-1)) Lmin(n)=(1-A) * Lmin(n-1)+A * L(n); Else Lmin(n)=(1-B) * Lmin(n-1)+B * L(n); End where A and B are constant parameters, Lmin(n) is the background noise energy of the current frame, and Lmin(n-1) is the previous The background noise energy of the frame.

Task 3: Determine the presence of the human voice V(n) for each frame of the enhanced audio signal 325. When there is a human voice, set V(n)=1, and when there is no human voice, set V(n)=0. The decision can be made by comparing the total energy L(n) of task 1 of the first algorithm with the lowest energy of background noise Lmin(n) of task 2 of the first algorithm. If (L(n) < Lmin(n) * Tdown) V(n)=0; Elseif (L(n) > Lmin(n) * Tup OR silentframe < 4) V(n)=1; Else V(n )=V(n-1); If (L(n) < Lmin(n) * Tdown) silentframe++; speechframe=0; Elseif (L(n) > Lmin(n) * Tup) silentframe=0; speechframe++; Tup and Tdown are parameters with fixed values.

The following is the vocal detection module 130 can be used to process enhanced audio signals. An example of a virtual code for the second algorithm of 325. The second algorithm is similar to the first algorithm, except that additional functions for filtering and contour tracking operations are added.

Task 1: For each frame of the enhanced audio signal 325, determine the total energy L(n) as: L(n) = (abs(FFT Output)* H) ² where "abs" is an absolute function (absolute function) "FFT Output" is the frequency domain representation of the FFT module 120, and H is the filter function.

Task 2: For each frame of the enhanced audio signal 325, apply a median filtering function H(n) to remove any high frequency noise, with a contour tracking function CT(n) Remove any bursts of noise and determine the average energy of each frame. H(n)=medianfilter(L(n-S):L(n)) CT(n)=mean(H(n-4):H(n))

Task 3: Determine the presence of the human voice V(n) for each frame of the enhanced audio signal 325. When there is a human voice, set V(n)=1, and when there is no human voice, set V(n)=0. A decision can be made by comparing the total energy L(n) of task 1 of the second algorithm with the result of the contour tracking operation CT(n) of task 2 of the second algorithm. If (L(n) < CT(n) * DB) V(n)=0; Elseif (L(n) > CT(n) * DB OR silentframe < 4) V(n)=1; If (L( n) < Lmin(n) * Tdown)silentframe++; speechframe=0; Elseif (L(n) > Lmin(n) * Tup) Silentframe=0; speechframe++; where Tup and Tdown are parameters with fixed values, and Tup and The value of Tdown will vary depending on the implementation.

It should be noted that the efficiency of the first and second algorithms may depend on the context of the background noise. The first algorithm performs better in the presence of uniform background noise. The second algorithm performs better in the case where background noise includes false high frequency noise including non-human voice.

Reference is now made to Fig. 4, which is a graph 400 demonstrating the false acceptance rate and false rejection rate associated with vocal detection operations. There are two possible types of errors when processing the enhanced audio signal 325 to determine if there is a human voice. The first type of error (called a false rejection error) rejects an audio signal that may include a human voice. The second type of error (called a false acceptance error) is to receive the noise as a human voice, and the noise may not include a human voice. For some embodiments, one or more threshold parameters may be used to control the error rejection rate and the error acceptance rate. For example, when the threshold parameter is set to a low value, all noise may be used as an adult sound. When the threshold parameter is set to a high value, all noises that do not include vocals may be rejected. Absolutely. Different operating points can be achieved by stylizing one or more threshold parameters. Referring to the first and second algorithm examples described above, the threshold parameters may include "A", "B", "DB", "Tup", and "Tdown".

The exemplary chart 400 includes a vertical axis 405 representing the error acceptance rate of a frame of the enhanced audio signal 325 and a horizontal axis 410 representing the error rejection rate. Curve 420 may represent an operating point associated with the first algorithm described above, and curve 425 may represent an operating point associated with the first algorithm described above. Each point on curves 420 and 425 can represent an operating point. In this example, the background noise can be 5dB. It is to be noted that the error acceptance rate and error rejection rate of curve 425 are generally lower than the first algorithm, which may be due to the use of additional median filtering and contour tracking functions.

Figure 5 shows an example of a hardware architecture implementation of a voice activity detection module. The illustration 500 can include elements included with some front end processing modules 102 (shown in Figure 1). For some embodiments, the sub-frame and split window module 115 of FIG. 1 can be implemented in a software manner and is therefore not included in the illustration 500. The components of the front end processing module 102 that may appear in the diagram 500 include an FFT module 120, a noise estimation and suppression module 125, and a vocal detection module 130.

It is to be noted that there are 2 segments in the diagram 500. The first section includes elements within the dashed block 505. The second section includes elements that are outside of the dashed block 505. For some embodiments, the components within the dashed block 505 can be configured to operate at low voltages (low Vcc) while they can be configured to operate at low clock frequencies (herein referred to as Pulse 1) operation. Dotted area The components outside block 505 can be configured to operate at high voltages (high Vcc), while they can be configured to operate at high clock frequencies (referred to herein as clock 16, as is 16 times) . Elements within dashed block 505 may include FFT module 525 and multiplication and filtering module 520, as well as voice activity detection modules 550 and 555. The FFT module 525 can correspond to the FFT module 120 of FIG. 1 , the multiplication and filtering module 520 can correspond to the noise estimation and suppression module 125 of FIG. 1 , and the voice activity detection modules 550 and 555 can correspond to the first figure. The vocal detection module 130.

Information related to the audio signal in the time domain can be stored in memory modules 510 and 515. In this example, each of the memory modules 510, 515 can include 512 48-bit lines. Therefore, the total memory size is 2 x 512 x 48 bits. When reading the information of the memory modules 510 and 515, the information can be transferred to the frame buffer 540 via the multiplexers 511, 516, and then to the frame buffer 545. It is noted that the frame buffer 540 is located outside of the dashed block 505 and the frame buffer 545 is located within the dashed block 505. Thus, frame buffer 540 can operate at higher voltages and clock frequencies (e.g., clock 16) than frame buffer 545.

The FFT module 525 can be configured as a 32-point FFT or a 16-point FFT module, wherein the configuration of the FFT module 525 can be controlled by a control module 560. The FFT module 525 can convert information from the memory modules 510, 515 from a time domain representation to a frequency domain representation. The multiplication and filtering module 520 can receive the results from the FFT module 525 and perform noise filtering The wave and noise suppression operations are performed to produce an enhanced audio signal 325 (as shown in Figure 3). The enhanced audio signal 325 can then be stored in the frame buffer 535, wherein the enhanced audio signal 325 can be processed by the voice activity detection module 550 or 555. Depending on the implementation, there may be multiple voice activity modules operating in parallel. Each of the voice activity detection modules 550 and 555 can employ a different algorithm (such as the first or second algorithm described above). As before, the components located within the dashed block 505 can be configured to operate at low frequencies (or clocks 1) and low voltages (or low Vccs). Elements located outside of the dashed block 505 can be configured to operate at high frequency (or clock 16) and high voltage (or high Vcc). A significant advantage of this is that the components located within the dashed block 505 consume less power.

Referring to Figure 6 below, it is an exemplary block diagram of a 512-point fast Fourier transform. The illustration 600 includes four planes. X plane 610, Y plane 620, Z plane 630, and W plane 640. The X-plane 610 can have 16 columns and 32 rows for a total of 16 x 32 = 512 information points. The information points of the X-plane 610 can correspond to the information received by the FFT module 525 of FIG. 5 from the memory modules 510, 515.

For some embodiments, 512 information points of the X-plane 610 can be converted using a 32-point FFT operation. Since there are 16 columns in the X-plane 610, the 32-point FFT operation conversion is performed 16 times. The result of each 32-point FFT operation performed on the information points of each column of the X-plane 610 is displayed in the corresponding column of the Y-plane 620. For example, the result of the 32-point FFT operation of the information points (X(0), X(16), ..., X(495)) of the first column of the X-plane 610 is reflected in the first of the Y-plane 620. Column (Y(0), Y(16),..., Y(495)).

The FFT operation is dominated by complex numbers, each of which has a real and imaginary part. The information points of the X-plane 610 may include real information without any imaginary information because they represent actual audio input signals. The X-plane 610 can be a real number plane. However, the information points within the Y-plane 620 may include real and imaginary parts. Y plane 620 can be referred to as a complex plane. The information point of the Y plane 620 can then be multiplied by a set of imaginary twiddle factors 625. This conversion factor 625 can correspond to the multiplication operation performed by the multiplication and filtering module 520 of FIG. For some embodiments, the conversion factor 625 can include 4 complex multipliers of parallel operations. Since the Y plane 620 has 512 information points, there are 128 multiplication periods to calculate the 512 information points used by the Z plane 630. Z plane 630 can be referred to as a complex plane.

For some embodiments, the information points of the Z-plane 630 can be converted using a 16-point FFT operation. This operation is a 16-point FFT operation on information points (e.g., Z(0), Z(1), ..., Z(15)) of each column of the Z-plane 630. Since there are 32 columns in the Z plane 630, the 16 point FFT operation needs to be performed 32 times. The result of each 16-point FFT operation performed on the information points of each column of the Z-plane 630 is reflected in the corresponding column of the W-plane 640. For example, the result of the 16-point FFT operation of the information points (Z(0), Z(1), ..., Z(15)) of the first column of the Z-plane 630 is reflected in the first of the W-plane 640. Columns (W(0), W(32), ..., W(480)).

Figure 7 is a block diagram showing an example of a hardware implementation of a fast Fourier transform module in accordance with an embodiment. The FFT module 700 can be referred to as a hybrid FFT module because it can be used to perform 32-point FFT and 16-point FFT operations. FFT The module 700 can correspond to the FFT module 525 of FIG. The decomposition of the 512 information points in Figure 5 applies to audio, speech, or conversation processing. Because these applications are suitable for the operations performed in tandem. For example, a decomposition of 512 information points may include a 32-point FFT operation (16 times) followed by 512 complex multiplications and a final 16-point FFT operation (32 times). This may be slower than performing a 512-point FFT operation parallel to all information points on the X-plane 610.

In order to be able to operate at low power (eg 4 MHz) at low power, it may be necessary to reduce the hardware architecture as much as possible. It should be noted that most of the power at such low frequencies is leakage power, so performing the same hardware serial operation can strike a balance between active and leakage power. For some embodiments, instead of using two different FFT modules, one for a 32-point FFT operation and one for a 16-point FFT operation, the FFT module 700 can be used to perform both 32-point and 16-point FFT operations. The FFT module 700 can include two 16 point FFTs 710, 720. The 16 point FFTs 710, 720 are configured for parallel operation.

The first 16-point FFT 710 can be connected to the 16-point FFT input 705 and its signals Y(0) to Y(15), or it can be connected to the 16 first input signals X(0) to X(15) of the 32-point FFT input 715. ). The second 16-point FFT 720 can be connected to the next 16 input signals X(16) through X(31) of the 32-point FFT input 715.

One of the 16-point FFTs 710, 720 within the FFT module 700 can be coupled to a control signal 725. Control signal 725 can be coupled to multiplexer 730. When the control signal 725 is At a first setting (e.g., 0), it may cause multiplexer 730 to accept input signal 705 and then cause FFT module 700 to operate as a 16 point FFT module. When the control signal 725 is at the second setting (e.g., 1), it may cause the multiplexer 730 to accept the input signal 715 and then cause the FFT module 700 to operate as a 32-point FFT module.

By using the FFT module 700 instead of the independent 32-point FFT module and the 16-point FFT module, the total number of adders can be reduced from about 9500 to about 8300, and the total number of multipliers can be reduced from about 312 to about 56. This can significantly save power and area, but there may be potential time within the acceptance range.

Figure 8 shows a hardware implementation example of a multiplication and filtering module. The multiply and filter module 800 can be configured to perform complex multiplication operations and filtering operations. For some embodiments, the complex multiplication of Figure 8 can be used as part of the conversion factor shown in Figure 6. For some embodiments, the filtering operation of Figure 8 can be performed after the FFT operation. The multiplication and filtering module 800 can correspond to the multiplication and filtering module 520 shown in FIG.

The multiplication and filtering module 800 can be configured to perform multiplication of two complex numbers (a+jb) and (c+jd). In general, the multiplication of these two complex numbers is as follows: X = a + jb

Y=c+jd

Z=X * Y=(ac+bd)+j(ad+bc)

X and Y are input signals, and Z is an output signal. In order to In the above multiplication, the conventional method requires four multipliers and two adders. Complex multiplication can be implemented using a complex multiplier of four parallel operations. The following are some examples of hardware-related information needed to implement the above operations using traditional techniques: Logic level = 52

Branch cell (Leaf cell) = 3264

For some embodiments, after correction, the same two complex numbers can be multiplied as follows: X = a + jb

Y=c+jd

(ac-bd)=a(c+d)-a(d+b) (where "ad" items are offset each other)

(ad+bc)=a(c+d)-a(c-b) (where “ac” items are offset from each other)

Z=X * Y=(ac+bd)+j(ad+bc).

In order to perform the above multiplication, three multipliers and five adders are required. It should be noted that compared to the conventional technology, the number of multipliers required in the modified practice is small, but the number of adders is relatively large. This is acceptable because the multiplier consumes more power or area than the adder. The following are some examples of hardware-related information needed to use the correction technique to perform the above operations: Logic level = 53

Branch cell = 2848 (the number of cells in this cell is less than the traditional technology)

Referring to Figure 8, three multipliers include multipliers 810, 820, and 850. Five adders include 860, 865, 870, and are used at the input. Two of "c-b" and "b+d". The input signals of the multiplication and filtering module 800 can be transmitted to a set of multiplexers 802, 804, 806, and 808. When these multiplexers are set to a value (eg, 0), the multiply and filter module 800 can be configured to perform complex multiplication operations. For example, at the first multiplexer 802, the signal "c-b" can be transmitted to the multiplexer 810. At the second multiplexer 804, the signal "a" can be transmitted to the multiplexer 810, causing the multiplexer 810 to produce a "a(c-b)" result. At the third multiplexer 806, the signal "b+d" can be transmitted to the multiplexer 820. At the fourth multiplexer 808, the signal "a" can be transmitted to the multiplexer 820, causing the multiplexer 820 to produce a "a(b+d)" result. The results of multiplexers 810 and 820 can be used for adders 860, 865, and 870 to produce the result of Z, that is, X*Y = (ac + bd) + j (ad + bc).

The multiply and filter module 800 can be configured to perform a filtering operation when the multiplexers 802, 804, 806, and 808 are set to a value (e.g., 1). In this case, the multiplication and filtering module 800 can be configured to filter the absolute square of the representation of the FFT operation "Coff*abs(xR+jxI)*abs(xR+jxI))", where "xR+ jxI" is a complex number, "abs" is an absolute value function, and "Coff" is a coefficient. The equality mathematical expression of this expression is "Coff(xR ² + xI ² )". This expression is shown on the right side of Figure 8. Inputs xR and xI are inputs to multiplexers 802, 804, 806, and 808. The first multiplexer 810 can then produce a result of "xR ² ", while the second multiplexer 820 can produce a result of "xI ² ". These results are then passed through a coefficient 848, a multiplexer 840, and a multiplexer 850 to produce a value representing the expression "Coff(xR ² + xI ² )".

Figure 9 shows a demonstration of processing audio signals to detect human audio signals. Flow chart of the method. This method can correspond to the hardware architecture shown in Figure 5. The method can be implemented with a set of logic instructions stored in a machine or computer readable medium such as RAM, ROM, PROM, and flash memory, with configurable logic such as PLA, FPGA, and CPLD Fixed-function logic hardware implemented in ASIC, CMOS or TTL technology, or a combination of the above. For example, a computer code for performing the operations of the present invention can be written in any combination of one or more stylized languages, including an object oriented stylized language such as C++ or the like, or a conventional program type. A stylized language, such as a "C" programming language or a similar programming language.

Block 905 stores the audio signal in memory. As mentioned above, the audio signal can include vocals and other noise, such as background noise. Audio signals can be recorded by the recorder and stored in the time domain. The memory can be configured to operate at a first clock frequency (eg, a high frequency). The memory can be configured to operate at a first voltage (eg, high Vcc).

Block 910 is used to perform an FFT operation on the audio signal to convert from the time domain to the frequency domain. The FFT operation can be performed based on the frame of the audio signal. As mentioned above, the frame can be determined by using a sub-frame and a windowing operation. The FFT operation can be configured with configurable FFT modules that can be configured as different types of FFT modules (eg, a 32-point FFT module or a 16-point FFT module). The configurable FFT module operates at a second clock frequency, such as a low frequency. The configurable FFT module can also operate at a second voltage (eg, low Vcc).

Block 915 is the frequency obtained after the FFT operation of block 910. The domain result is subjected to noise suppression and filtering operations, and is dominated by the second voltage. The filtering operation can use the configurable multiplication and filtering hardware shown in Figure 8. The noise suppression operation can utilize one or more of the noise suppression techniques shown in FIG. The noise suppression and filtering operations of block 915 can operate at a second clock frequency (e.g., low frequency). The noise suppression and filtering operations can also operate at a second voltage (eg, low Vcc).

Block 920 performs voice detection after the noise suppression and filtering operations of block 915 are completed. As shown in Figure 5, one or more speech detection algorithms may be employed. The total energy and background noise in a frame can be used to determine the presence of a human voice. The speech detection operation of block 920 can be performed at a second clock frequency (e.g., low frequency). The speech detection operation can also be performed at a second voltage (eg, a low voltage).

Embodiments of the present invention are applicable to various types of semiconductor integrated circuit (IC) wafers. Examples of IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoC), SSD/ NAND controller ASIC, and the like. Moreover, in some of the illustrations, the signal conducting lines are represented by line segments. Some may be represented in different ways to display more constituent signal paths, with labels to indicate a number of constituent signal paths, and/or one or more endpoints with arrows to indicate the primary message flow direction. However, the above is not intended to limit the invention. Rather, the added details may be used in one or more exemplary embodiments to facilitate an understanding of the function of the circuitry. The signal lines shown in any of the figures, whether or not they have additional resources The signal may actually contain one or more signals that can be transmitted in multiple directions and may be implemented using any suitable signal type, such as digital or analog lines implemented with differential pairs, fiber optic lines, and/or single-ended lines. .

Exemplary sizes/models/values/ranges are set forth in this specification, although embodiments of the invention are not limited thereto. As manufacturing techniques (such as lithography techniques) continue to advance, device sizes will become smaller and smaller. In addition, known IC chip power/ground connections and other components may not be shown in the figures to simplify the illustration and discussion, and are not intended to confuse particular embodiments of the invention. In addition, the configuration is shown in a block diagram format to avoid obscuring the embodiments of the present invention, and it should be noted that such a block diagram configuration is highly correlated with the implemented platform, that is, those skilled in the art should be fully aware of this. Specific details of the invention. Since the specification has been described in detail with reference to the exemplary embodiments of the present invention, it should be understood that The examples presented herein are intended to be illustrative and not limiting.

The term "coupled" is used herein to refer to any type of component in question, whether direct or indirect, and may be applied to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other on. In addition, "first" and "second" are for convenience of discussion and do not represent any particular time or chronological meaning unless otherwise indicated.

Those skilled in the art will appreciate that the embodiments of the present invention can be implemented in a variety of different forms. Therefore, although the embodiments of the present invention have been described by the above specific examples, the actual scope thereof It should not be limited to this, and those skilled in the art should be able to understand other modifications after reading the above diagram, the description of the embodiments, and the scope of the subsequent patent application.

100‧‧‧Voice Identification System

101‧‧‧Pre-processing module

102‧‧‧ front-end processing module

103‧‧‧Back-end processing module

105‧‧‧recorder

110‧‧‧ Pulse Density Modulation to Pulse Code Modulation Converter

115‧‧‧Sub-frame and split window module

120‧‧‧Fast Fourier Transform Module

125‧‧‧ Noise Estimation and Suppression Module

130‧‧‧Sound detection module

135‧‧‧ vocal information

140‧‧‧Voice Processing Module

200‧‧‧ chart

205‧‧‧ vertical axis

210‧‧‧ horizontal axis

215‧‧‧ frame

220‧‧‧ frames

225‧‧‧ frame

230‧‧‧ non-overlapping windows

305‧‧‧Filtered information

310‧‧‧First Noise Suppression Module

315‧‧‧Second noise suppression module

320‧‧‧Nth noise suppression module

325‧‧‧Enhanced audio signal

400‧‧‧ Chart

405‧‧‧ vertical axis

410‧‧‧ horizontal axis

420‧‧‧ Curve

425‧‧‧ Curve

500‧‧‧ icon

505‧‧‧dotted block

510‧‧‧ memory module

511‧‧‧Multiplexer

515‧‧‧ memory module

516‧‧‧Multiplexer

520‧‧‧Multiplication and Filter Module

525‧‧‧FFT Module

535‧‧‧ frame buffer

540‧‧‧ frame buffer

545‧‧‧ frame buffer

550‧‧‧Voice Activity Detection Module

555‧‧‧Voice Activity Detection Module

560‧‧‧Control Module

600‧‧‧ icon

610‧‧‧X plane

620‧‧‧Y plane

625‧‧‧ imaginary conversion factor

630‧‧‧Z plane

700‧‧‧FFT Module

705‧‧16-point FFT input

710‧‧16 point FFT

715‧‧‧FFT input

720‧‧16 point FFT

725‧‧‧Control signal

730‧‧‧Multiplexer

800‧‧‧Multiplication and Filter Module

802‧‧‧Multiplexer

804‧‧‧Multiplexer

806‧‧‧Multiplexer

808‧‧‧Multiplexer

810‧‧‧Multiplier

820‧‧‧Multiplier

848‧‧ coefficient

850‧‧‧Multiplier

860‧‧‧Adder

865‧‧‧Adder

870‧‧‧Adder

Those skilled in the art will be able to better understand the various advantages of the present invention through the following description and accompanying patent examples, together with the accompanying drawings, wherein: FIG. 1 is a block diagram illustration of an embodiment of a speech recognition system; The graph shown in FIG. 2 is an example of related energy and frame of an audio signal according to an embodiment; FIG. 3 is a block diagram of an exemplary embodiment of noise suppression; and FIG. 4 is a diagram of operation with human voice detection. An exemplary diagram of the associated error acceptance rate and error rejection rate; Figure 5 shows an example of a hardware architecture implementation of a voice activity detection module; and Figure 6 shows an exemplary 512-point fast Fourier transform according to an embodiment. FIG. 7 is a block diagram showing a hardware implementation example of a fast Fourier transform module according to an embodiment; FIG. 8 is a hardware example diagram of a multiplication and filtering module according to an embodiment. And Figure 9 shows a demonstration of processing audio signals to detect audio signals. Flow chart of the law.

100‧‧‧Voice Identification System

101‧‧‧Pre-processing module

102‧‧‧ front-end processing module

103‧‧‧Back-end processing module

105‧‧‧recorder

110‧‧‧ Pulse Density Modulation to Pulse Code Modulation Converter

115‧‧‧Sub-frame and split window module

120‧‧‧Fast Fourier Transform Module

125‧‧‧ Noise Estimation and Suppression Module

130‧‧‧Sound detection module

135‧‧‧ vocal information

140‧‧‧Voice Processing Module

Claims (25)

An apparatus for low-power speech detection, comprising: logic means for storing a time domain audio signal in a memory set to operate according to a first clock frequency and a first voltage, and according to a first The second clock frequency and a second voltage are used to perform a Fast Fourier Transform (FFT) operation on the time domain audio signal to generate a frequency domain audio signal. The apparatus of claim 1, wherein the logic means: performing a first set of FFT operations; performing a complex multiplication operation; and concatenating the first set of FFT operations to perform a second set of FFT operations. The device of claim 2, wherein the second clock frequency is slower than the first clock frequency, and wherein the second voltage is lower than the first voltage. The device of claim 3, wherein the logic means is: performing a noise suppression operation; performing a filtering operation on the frequency domain audio signal according to the second clock frequency and the second voltage, An enhanced audio signal is generated. The apparatus of claim 4, wherein the complex product operation and the filtering operation are performed in a same hardware component. Such as the device described in claim 4, wherein the logic The means is configured to perform a voice detection operation on the enhanced audio signal according to the second clock frequency and the second voltage. The device of claim 6, wherein the logic is used to determine a total energy in a frame of the enhanced audio signal and to determine background noise in the frame of the enhanced audio signal. The apparatus of claim 7, wherein the logic means is to perform a median filtering operation and perform a contour tracking operation. The device of claim 7, wherein the logic means is configured to execute a command related to the detected human voice according to the first clock frequency and the first voltage. A computer implemented method for low power speech detection, comprising: recording a time domain audio signal at a first clock frequency and a first voltage; and performing fast Fourier transform (FFT) on the time domain audio signal of the second clock frequency An operation to generate a frequency domain audio signal, wherein the first clock frequency is faster than the second clock signal. The method of claim 10, wherein the FFT operations are performed at a second voltage that is lower than the first voltage. The method of claim 11, further comprising: performing a noise suppression operation on the second clock frequency and the frequency domain audio signal of the second voltage to generate an enhanced audio signal. The method of claim 12, further comprising: the enhanced audio signal for the second clock frequency and the second voltage No. Performs a vocal detection operation to detect vocals. The method of claim 13, wherein the step of performing the vocal detection operation comprises: determining a total energy in a frame of the enhanced audio signal; determining a frame within the frame with the enhanced audio signal Background noise related energy; and detecting the vocal sound by subtracting the energy associated with the background noise from the total energy in the frame of the enhanced audio signal. The method of claim 13, further comprising: executing a command related to the human voice at the first clock frequency and the first voltage. The method of claim 15, wherein the time domain audio signal is continuously recorded at the first clock frequency and the first voltage is converted from pulse density modulation (PDM) to pulse code modulation. (PCM). The method of claim 16, wherein the FFT operations are performed in series. A computer readable storage medium comprising a set of instructions for low power speech detection, if executed by a processor, causing a computer to: record a time domain audio signal at a first clock frequency and a first voltage; The time domain audio signal of the second clock frequency performs a fast Fourier transform (FFT) operation to generate a frequency domain audio signal, wherein the first clock frequency is faster than the second clock signal. Such as the media described in claim 18, wherein such The FFT operation is performed at a second voltage that is lower than the first voltage. The medium of claim 19, further comprising a set of instructions, if executed by the processor, to cause the computer to: perform noise on the frequency domain audio signal at the second clock frequency and the second voltage Suppressing an operation to generate an enhanced audio signal; performing a vocal detection operation on the enhanced audio signal at the second clock frequency and the second voltage to detect a human voice; and performing the first clock frequency and the first voltage A command related to the vocal. The medium of claim 20, wherein the vocal sound detection operation is: determining a total energy in a frame of the enhanced audio signal; determining a background in the frame with the enhanced audio signal The noise associated with the noise; and detecting the vocal by subtracting the energy associated with the background noise from the total energy in the frame of the enhanced audio signal. The medium of claim 21, wherein the time domain audio signal is continuously recorded at the first clock frequency and the first voltage. A system for low-power speech detection, comprising: a pre-processing module configured to extract an audio signal as a pulse density modulation (PDM) information stream according to a first clock frequency and a first voltage, and Converting the PDM information stream into a pulse code modulation (PCM) information stream; the front end processing module is coupled to the preprocessing module and configured to use the PCM information flow frame and the interval as multiple signals a frame; and a fast Fourier transform (FFT) module coupled to the front end processing mode a group configured to receive a frame of the PCM information stream according to the second clock frequency and the second voltage and perform a conversion of the frames from the time domain representation to the frequency domain representation, wherein the second The clock frequency is different from the first clock frequency, and the second voltage is different from the first voltage. The system of claim 23, wherein the first clock frequency is faster than the second clock frequency, and wherein the second voltage is lower than the first voltage. The system of claim 24, further comprising: a noise estimation and suppression module coupled to the FFT module, configured to analyze the frames in the frequency domain representation and to filter The noise information is not in the same frequency band as the human voice; the vocal detection module is coupled to the noise estimation and suppression module, and is configured to determine according to a human voice frequency band and using a background noise estimate Whether a voice is present in the frame; and a voice processing module coupled to the voice detection module configured to determine a command associated with the voice and to perform an operation associated with the voice command .