TWI489375B - Carryless multiplication apparatus and method - Google Patents

Description

Carry-free multiplication device and processing method thereof

This invention relates to a microelectronic, and more particularly to a technique for performing a carry-free multiplication operation.

In most current communications, communication data can be encrypted. Efficient encryption methods can be used from simple authentication to hashed enciphered messages using symmetric key cryptography. In the symmetric key encryption technology, the more common operation mode is Galois Counter Mode (GCM). GCM can encrypt and authenticate a message.

It is well known in the art that GCM is combined with a counter mode encryption technique and a recently developed Galois mode authentication technology. In GCM, the multiplication of the Galois field is used for authentication. Although the multiplication of the Galloway field is not the scope of the case, the multiplication of the Garowa field is a carry-free multiplication.

In general, the carry-free multiplication is a binary polynomial multiplication, and is also a mathematical operation that estimates the product of the two operands, and does not produce or add more carry bits. In fact, INTEL has provided an instruction (such as PCLMULQDQ) that can control x86 compatible microprocessors to perform this function.

Therefore, when the designer of the microprocessor modifies the original design to provide more functionality, the multiply-free multiplication must be considered together. This is a simple operation, but those skilled in the art are well aware that it is necessary to utilize a large number of hardware in order to achieve a carry-free multiplication operation. For example, at 64 In the carry-less multiplication operation of the bit, 64 partial products will be produced. After the 64 partial products are mutually exclusive or (XOR), a final result of 128 bits is obtained. In most current microprocessor designs, there is no unit or logic that can perform such operations. However, in most microprocessors, there are at least one multiplication unit for performing general multiplication operations.

In recent years, many improvements have been developed to make current multiplication units more executable. For example, Booth encoding is a common technique. In multiplication, Booth coding reduces the partial product by half. The Wallace tree is also a common technique used to sum up the partial product produced by the Booth code.

Although with better performance, the above techniques will produce or increase carry. Therefore, the current multiplication unit is completely unsuitable for a carry-free multiplication operation.

In order to solve the above disadvantages, the inventors of the present invention found that it is preferable to use the original hardware as much as possible to avoid an increase in power loss and the number of components. In addition, from the point of view of debugging and testing, it is best to use the original hardware architecture to achieve different functions.

Therefore, it is necessary to provide an apparatus and method for performing a carry-free multiplication operation in a processor or other device and using a large amount of original hardware components.

In addition, a multiply unit capable of binary carry-less multiplication is required, and there is no need to make too many modifications to the original multiply unit.

The present invention solves the above problems and can satisfy other problems, disadvantages and limitations of the prior art. The present invention provides a prioritized technique for performing a carry-free multiplication operation using a conventional Booth hardware in a processor or other device. In a possible embodiment, the present invention provides a carry-free multiply device for performing a carry-free multiplication operation, comprising a carry-free preformat unit, a Booth encoder, a compressor, a left shifter, and a Mutually exclusive or gate. The carry-free preformat unit receives a multiplier operand and formats the multiplier operand into a complex part. The Booth encoder receives and determines the portions and selects the complex first partial product of a multiplicand operand. With these parts, it is avoided that the complex second partial product of the multiplicand operand is selected. The second part of the product will cause a carry phenomenon. The compressor is coupled to the Buss encoder to store the adder through the complex carry and add the first partial product. The carry store adder generates a complex sum bit and a complex carry bit. The carry storage adders are arranged in a Wallace tree architecture. The carry bit is not enabled when performing a carry-free multiplication operation. The left shifter is coupled to the compressor to shift the output of the compressor to the left by at least one bit. The mutex or gate is coupled to the compressor and the left shifter for performing a mutually exclusive OR operation and producing a carry-free multiplication result.

The present invention further provides a method for performing a carry-free multiplication operation, comprising: formatting a multiplier operation element into a complex part in a multiplication unit in a processor; determining the And selecting a multiplicative first partial product of a multiplicand operator, wherein by means of the portions, the second partial product of the multiplicand operator is prevented from being selected, and the second partial product causes a carry phenomenon Processing the first partial product through a complex carry storage adder to generate a complex total a bit and a complex carry bit, wherein the carry store adders are arranged in a Wallace tree architecture, and the carry bit is not enabled when performing the carry-less multiplication operation; the output of the Wallace tree Shifting at least one bit to the left; and performing a mutually exclusive OR operation on the output of the Wallace tree to produce a carry-free multiplication result.

In the industrial field, the present invention can be implemented in a microprocessor, and the microprocessor can be applied to a computer device of a general function or a special function.

The present invention solves the above problems and can satisfy other problems, disadvantages and limitations of the prior art. The present invention provides a prioritized technique for performing a carry-free multiplication operation using a conventional Booth hardware in a processor or other device. In a possible embodiment, the present invention provides a carry-free multiply device for performing a carry-free multiplication operation, including a first operand register, a second operand register, and an opcode detection. , a carry-free preformat unit, a compressor, a left shifter, and a mutex or gate. The first and second operand registers respectively receive a first operand and a second operand for performing a carry-free multiplication operation. The opcode detector receives a carry-free multiply instruction and enables a carry-free signal based on the carry-free multiply instruction. When no carry signal is enabled, the no pre-format unit formats the first operand into a complex portion. With a portion of the Buss encoder, the selection of the complex second partial product of the second operand is avoided. The second part of the product will cause a carry phenomenon. The compressor stores the adder of the first operand of the second operand through a complex carry store adder. The carry store adder generates a complex sum bit and a complex carry bit. The carry storage adders are arranged in a Wallace tree architecture. When no carry signal is enabled, The carry bit is not enabled. The left shifter is coupled to the compressor to shift the output of the compressor to the left by at least one bit. The mutex or gate is coupled to the compressor and the left shifter for performing a mutually exclusive OR operation and producing a carry-free multiplication result.

The present invention provides a method for performing a carry-free multiplication operation, comprising: receiving, in a multiplication unit in a processor, a first operation element and a second operation element for performing a carry-free multiplication operation; A carry-free multiply instruction enables a carry-free signal; when no carry signal is enabled, the first operand is formatted into a complex portion, wherein a Booth encoder avoids selecting the second by the portions The second partial product of the operands, the second partial product causing a carry phenomenon; the complex first load storage adder adds the first partial product of the second operational element, and the carry storage adder generates a complex addition a total bit and a plurality of carry bits, wherein the carry store adders are arranged in a Wallace tree structure, and when the carry signal is enabled, the carry bits are not enabled; the Wallace is enabled The output of the tree, shifted to the left by at least one element; and a mutually exclusive OR operation on the output of the Wallace tree to produce a carry-free multiplication result.

In the industrial field, the present invention can be implemented in a microprocessor, and the microprocessor can be applied to a computer device of a general function or a special function.

The present invention solves the above problems and can satisfy other problems, disadvantages and limitations of the prior art. The present invention provides a prioritized technique for performing a carry-free multiplication operation using a conventional Booth hardware in a processor or other device. In a possible embodiment, the present invention provides an apparatus for performing a carry-free multiplication operation. The apparatus of the present invention includes an opcode detector and a carry-free preformat unit. Opcode detector A no carry multiplication instruction is received, and according to the no carry multiplication instruction, a carry signal is enabled. When no carry signal is enabled, the no pre-format unit formats the first operand into a complex portion. A Booth encoder can select a complex first partial product of a second operational element by means of the portions and avoid selecting a complex second partial product of the second operational element, the second partial product causing a carry phenomenon. The first partial products are subjected to a mutually exclusive OR operation to produce a carry-free multiplication result.

The present invention provides a method for performing a carry-free multiplication operation. The method of the present invention includes receiving a carry-in multiplication instruction in a multiplication unit in a processor, and performing a carry-free multiplication operation together with a first operation element and a second operation element; according to the carry-free multiplication instruction , enabling a carry-free signal; and when the no-carry signal is enabled, formatting the first operand into a complex portion, wherein a Buss encoder selects a complex first partial product of the second operand by the portions And avoiding selecting a complex second partial product of the second operand, the second partial product causing a carry phenomenon; the first partial products undergoing a mutually exclusive OR operation to produce a carryless multiplication result.

In the industrial field, the present invention can be implemented in a microprocessor, and the microprocessor can be applied to a computer device of a general function or a special function.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Those skilled in the art can use the following content in a specific application. The invention is manufactured and used under the scope and requirements. In addition, those skilled in the art can make minor modifications according to the following contents, and further introduce other embodiments. Therefore, the present invention is not limited to the specific embodiments described below, but the maximum scope of the invention is in accordance with the principles and novel features.

In view of the background discussion of the above multiplication and carry-less multiplication operations, and the technique by which the processor produces multiplication results, the limitations of the apparatus will be illustrated by Figures 1-3. Next, how the present invention solves the shortcomings and limitations of the conventional multiplying apparatus will be explained in Figs. 4-7, and how the present invention performs a carry-less multiplication operation using the hardware architecture originally performing the general multiplication operation.

Figure 1 is a possible embodiment of a 64-bit multiplying unit. The 64-bit multiplying unit 100 can be applied to a microprocessor or other device. The multiplication unit 100 has a first operand register 101. The first operand register 101 is coupled to a Boots encoder 104. The multiplication unit 100 has a second operand register 102. The second operand register 102 is coupled to a portion of the product generator 103. Both the Buss encoder 104 and the partial product generator 103 are coupled to the Buss multiplexer 105. The Buss multiplexer 105 is coupled to the compressor 106 via a bus bar PARTPROD. Compressor 106 has a carry-save adder (CSA) 108. The carry storage adder 108 is arranged in a conventional Wallace Tree architecture to reduce the propagation delay when summing a plurality of partial products. The compressor 106 is coupled to a full adder 109 via the bus bars CARRIES and SUMS. The full adder 109 outputs a multiplication result through the bus bar RESULT, the multiplication result being a 2's complement and having 128 bits. In order for the multiplication unit 100 to produce the final 128-bit product, a product synchronizer 107 generates a synchronization signal CLK. In order to synchronize the operations within the multiplying unit 100, the multiplying unit 100 is caused to produce the final 128-bit product, and the synchronization signal CLK is transmitted to the Buss encoder 104 and the compressor 106.

In operation, an instruction (not shown) is transmitted to the multiplication unit 100 either directly or indirectly, or in two operands. Therefore, a multiplier operand OP A having 64 bits is supplied to the first operand register 101, and a multiplicand operand OP B having 64 bits is supplied to the second operand. The memory 102. The multiplier operand OP A and the multiplicand operand OP B are both 2 complement formats. In general, 64-bit operands are more common, so registers 101 and 102 are 64-bit scratchpads. However, in other multiplying cell architectures, other bit number registers can also be used. For example, it is well known in the art that in 64-bit multiplication, two 64-bit operands can be divided into four 32-bit operands, and multiplication unit 100 processes using known techniques and devices. Four 32-bit operands to get a product result.

It is well known in the art that the multiplication unit 100 mostly uses the Booth coding technique to reduce the number of partial products and add all the partial products together to obtain a final product. In general, the Booth encoder 104 is a 3-bit Buss encoder. By continuously operating the Buss encoder 104, a plurality of partial products can be generated. These partial products are the result of multiplication of substrate-4 (radix-4). Therefore, the number of partial products can be reduced. Adding these partial products together will give you a final result. Therefore, by synchronizing the synchronization signal CLK, the Boots encoder 104 determines the value of the continuous 3-bit data segment of the multiplier operand OP A and controls the Buss multiplexer 105 through the bus bar PPSEL for Of the selection signals, one is selected. Signal on busbar PPSEL The Buss multiplexer 105 is controlled to select one of the five partial products, wherein the five partial products are related to the multiplicand operand OP B . These five partial products are all produced by the partial product generator 103. The partial product generator 103 multiplies the multiplicand operand OP B by 0 to generate a partial product 0. The partial product generator 103 multiplies the multiplicand operand OP B by +1 to generate a partial product B. The partial product generator 103 multiplies the multiplicand operand OP B by -1 to generate a partial product -B. The partial product generator 103 multiplies the multiplicand operand OP B by +2 to generate a partial product 2B. The partial product generator 103 multiplies the multiplied operand OP B by -2 to generate a partial product -2B. It is well known in the art that as long as the partial product generator 103 finds the complement of the multiplicand operand OP B , or shifts the multiplicand operand OP B to the left, or takes the multiplicand operand OP B first. The complement of the complement, and then shift the result of the complement to the left, you can get the above five partial products (-2B, -B, 0, B, 2B).

In addition to controlling the Buss encoder 104, the sync signal CLK can check the value of the consecutive 3-bit data segments of the multiplier operand OP A, and can further control the compressor 106 to store the corresponding partial product until the multiplier The values of all consecutive 3-bit data segments of operand OP A have been checked. These partial products are assigned to inputs A, B, and C of the carry store adder 108 for generating a carry bit on the bus bar CARRIES and summing bits in the bus bar SUMS, followed by full addition. The 109 finds the sum of the carry bit and the total bit, and outputs a final product having 128 bits through the bus RESULT, wherein the final product is a 2's complement.

Figure 2 is a diagram showing how the multiplication unit 100 of Fig. 1 uses Booth. The encoder reduces the number of partial products. As mentioned above, many multiplication units in microprocessors or other devices use Booth coding techniques. The Booth coding technique produces a partial product based on a plurality of bits of one of the two operands. This technique primarily encodes a substrate-2 multiplier into a higher substrate. In the 3-bit Booth coding technique, the multiplier of the substrate-2 is encoded into a multiplier of the base-4, so that the number of partial products can be reduced by about half. The Booth coding technique has been disclosed in U.S. Patent No. 5,691,930, issued toK. Figure 2 shows the correspondence between the value of the 3-bit data segment of the multiplier (OP A) and a plurality of multiplication coefficients, wherein the multiplicand (OP B) is multiplied by the multiplication coefficient to obtain the corresponding Partial product. For example, when the value of the 3-bit data segment of the multiplier is 000 and 111, the multiplication coefficient 0 can be corresponding. When the value of the 3-bit data segment of the multiplier is 001 and 010, the multiplication coefficient +1 can be used. When the value of the 3-bit data segment of the multiplier is 101 and 110, the multiplication coefficient -1 can be matched. When the value of the 3-bit data segment of the multiplier is 011, the multiplication coefficient +2 can be matched. When the value of the 3-bit data segment of the multiplier is 100, the multiplication coefficient -2 can be matched. The partial product generator 103 multiplies the multiplicand operator OP B by the corresponding multiplication coefficient to generate a plurality of partial products, and inputs the partial products to the multiplexer 105. The Boots encoder 104 judges the value of each 3-bit data segment of the multiplier operand OP A and selects a corresponding partial product through the bus bar PPSEL according to the judgment result.

Figure 3 illustrates how the Buss coding technique reduces the number of partial products under multiplication operations. In Fig. 3, a 4-bit multiplication is taken as an example. Figure 3 shows a multiplicand operand 301 with 4 bits. The multiplicand operand 301 may be provided to the partial product generator described above. Figure 3 also shows A multiplier operand 302 having 4 bits. The multiplier operand 302 may be provided to the Booth encoder described above. It is well known in the art that in order to perform 3-bit Booth coding, it is necessary to arrange a bit 303 having a value of 0 after the last significant bit (LSB) of the multiplier operation element 302. Based on the value of the first 3-bit data segment 304, a multiplication coefficient can be known from the table 200 presented in FIG. According to the multiplication coefficient, a partial product having 4 bits can be selected. As shown in Fig. 3, the value of the first 3-bit data segment 304 is 110, so it can correspond to the multiplication coefficient -1. Therefore, the multiplicand operation unit 301 takes the 2's complement and then expands its bit number, so that the expanded partial product 307 can be obtained, and its value is 11111001. The next 3-bit data segment 305 overlaps the data segment 304 by one bit. According to the table 200 of FIG. 2, it can be known that the data segment 305 corresponds to the multiplication coefficient +1. Therefore, the multiplicand operand 301 can be directly used as the partial product 308. Since the substrate-4 is taken as an example, the partial product 308 is shifted to the left by 2 bits. That is, the last significant bit of the partial product 308 is aligned to the bit 2 of the partial product 307 (if the last significant bit of the partial product 307 is referred to as bit 0). According to the table of Fig. 2, it can be known that the last 3-bit data segment 306 corresponds to the multiplication coefficient 0. Therefore, the partial product 309 is 0000, and the partial product 309 is shifted to the left by 2 bits. That is, the last significant bit of the partial product 309 is aligned to the bit 2 of the partial product 308 (if the last significant bit of the partial product 308 is referred to as bit 0).

By summing the partial products 307~309, the multiplication result 310 of the 8-bit is obtained, and its value is 00010101.

The invention relates to Booth coding. The performance that Booth code can achieve is quite high when performing multiplication operations. However, the Booth code cannot perform a carry-free multiplication operation. When judging the value of the 3-bit data segment, it may correspond To the multiplication factor +2 or -2, a carry occurs after the product of the total is added. In order to perform a multiplication operation without carry in a processor or other device, the Booth coding technique cannot be used. In addition, the carry phenomenon also occurs in the compressor that calculates the total, so compression cannot be used.

Therefore, in order to perform a carry-free multiplication operation, the present invention provides a completely independent carry-less multiplication unit, that is, at least one independent multi-carrier multiplication hardware is provided in a multiplication unit. Those skilled in the art are well aware that adding new hardware will increase power consumption, reduce reliability, and increase the complexity of testing and debugging of the device.

It is well known in the art that the best method is to use the original multiplication hardware in a processor or other device to make the most efficient use. However, due to the characteristics of Booth coding and compression hardware, it is impossible to achieve a carry-free multiplication operation by using Buss coding and compression hardware.

The present invention provides an apparatus and method for achieving a carry-free multiplication operation in a processor or other device. The invention utilizes the original Booth coding element and the compression element with minor modifications. Therefore, the carry-free multiplication operation disclosed in the present invention is the least necessary modification in the original multiplication unit and does not affect the speed of the original multiplication unit. The invention will be described below with reference to Figures 4-7.

In summary, according to the value of the bit data segment of the multiplier, a corresponding multiplication coefficient can be obtained. Since this multiplication factor may be +2 or -2, a carry may occur in the multiplication operation. In addition, carry storage adders (CSAs) that originally have a Wallace tree structure also generate carry. Accordingly, the present invention provides a carry-free multiplication technique that splits a single operation into two operations to avoid a carry occurring when a partial product is added. The invention also provides a A modified compressor that selectively enables or disables the resulting carry.

Fig. 4 is a Boots code coefficient of the present invention which does not generate a carry. Figure 4 is similar to Figure 2, except that Figure 4 has only two multiplication coefficients, 0 and +1, corresponding to the values 000 and 010, respectively. By the multiplier operation element formatted by the present invention, the value deleted by the strikethrough as shown in Fig. 4 (e.g., 001, 011 to 111) can be avoided. The present invention formats the multiplier and then uses the Booth encoding device based on the formatted result. Since the multiplication factor that will generate the carry is avoided, a carry-less multiplication operation can be performed.

Figure 5 shows how the present invention formats the operands and then uses the Booth code to perform a multiply-free multiplication operation. Figure 5 shows three representations 501, 511 and 521. The expression 501 has an 8-bit operand 502 and a bit 503. The value of bit 503 is zero and is arranged after the last significant bit (LSB) of operand 502. In general, the last significant bit of operand 502 is referred to as bit 0 (bit 0). If the value of the odd-numbered bits (i.e., bit 1, bit 3, bit 5, and bit 7) of the operand 502 is modified to 0, the modified result is as shown by the even portion 512 of the expression 511. To perform the calculation of the Booth code for the even portion 512, the bit 513 can be arranged after the last significant bit of the operand 512, where the value of the bit 513 is zero. The values of the odd-numbered bits (ie, bit 1, bit 3, bit 5, and bit 7) of the operand 502 are shifted to the right (ie, as bit 0, bit 2, bit 4, and bit 6), and then the operation element 502 is The odd-numbered bits are filled with 0 to obtain the odd-numbered portion 522 of the expression 521. In order to perform the Bussian coding calculation on the odd portion 522, the bit 523 is arranged after the last significant bit of the odd portion 522, where the value of the bit 523 is zero.

The even part 512 and the odd part 522 completely represent the original operation element 502, and can replace the operand 502 for multiplication. The result of adding the total of the partial products of the odd portion 522 to the left by one bit, and then adding the total of the partial products of the even portion 512, produces the final multiplication result.

In the present embodiment, the operand 502 is preformatted to generate the even portion 512 and the odd portion 522, and the even portion 512 and the odd portion 522 are checked by the Booth encoder to obtain a multiplication result. For a generally formatted operand 502, if the multiplication operation is performed in this way, all steps of the multiplication unit are repeated twice. However, the present invention can use the Booth coding technique by pre-formatting the operand 502 into an even part 512 and an odd part 522 without generating a carry because in the expressions 511 and 521, all 3 The values of the bit data segments 514~518 and 524~528 are not 000 or 010. Therefore, the corresponding multiplication coefficient is not 0 or 1. Since the present invention can perform a multiplication operation without carry by the conventional Booth code structure, the complexity of the carry-free multiplying device in the microprocessor or other device is not increased. In the original expression 501, if the value of the data segments 504 to 508 is checked, the multiplication coefficient corresponding to the data segment 505 is -2, and the multiplication operation is carried out. However, in the present embodiment, the values of the data segments 514-518 and 524-528 generated by the pre-formatting do not cause a carry.

Figure 6 is a carry-only multiplication unit of the present invention. The multiplication unit 600 is similar to the multiplication unit 100 of Fig. 1. The multiplication unit 600 has a first operand register 601. The first operation register 601 is coupled to a carry-free pre-format unit 612. The carry-free pre-format unit 612 is coupled to a Booth encoder 604. Multiplication unit 600 has a second operand register 602. The second operand register 602 is coupled to a portion of the product generator 603. Booth Both the encoder 604 and the partial product generator 603 are coupled to a Buss multiplexer 605. The Buss multiplexer 605 is coupled to a compressor 606 via a bus bar PARTPROD. Compressor 606 has a number of carry-free compression coefficients. Compressor 606 has a carry-free enable input signal and includes complex carry storage adders (CSAs) 608. The carry storage adder 608 is arranged in a Wallace tree architecture. The compressor 606 is coupled to a left shifter 609 through a bus bar SSUM and coupled to a full adder 610 via a bus bar CARRIES. The left shifter 609 is coupled to the full adder 610. In a possible embodiment, the full adder 610 outputs a multiplication result of 128 bits through a bus RESULT. The full adder 610 is coupled to a register 613 via a bus bar RESULT. In addition, a product synchronizer 607 generates a synchronization signal CLK. In order for the multiplication unit 600 to produce the final 128-bit product, the carry-free preformat unit 612, the compressor 606, the left shifter 609, and the full adder 610 receive the synchronization signal CLK for synchronous operation. In addition, the multiplication unit 600 of the present invention has an opcode detector 611. The opcode detector 611 generates a carry-free signal CARRYLESS. The carry-free preformat unit 612, the compressor 606, and the left shifter 609 receive the carry-free signal CARRYLESS.

In a conventional multiplication operation or a carry-less multiplication operation, an instruction (not shown) is transferred to the multiplication unit 600 directly or indirectly, or into two operands. In one possible embodiment, a multiplier operand OP A is provided to the first operand register 601, and a multiplicand operand OP B is provided to the second operand register 602. Both the multiplier operand OP A and the multiplicand operand OP B are 2's complement. In this embodiment, both the multiplier operand OP A and the multiplicand operand OP B have 64 bits, but not It is used to limit the invention. In other embodiments, the multiplier operand OP A and the multiplicand operand OP B have other numbers of bits. In another embodiment, in 64-bit multiplication, two 64-bit operands can be divided into four 32-bit operands and multiplied by multiplying unit 600.

To generate a final product, the multiplication unit 600 uses the Booth code of the multiplication unit 100 of Fig. 1 to reduce the number of summed partial products. In an embodiment, a 3-bit Booth encoder 604 is used. When the Booth encoder 604 is in operation, the Buss multiplexer 605 can continuously output the corresponding partial product, wherein the partial products are the multiplication results of the substrate-4. Therefore, the total number of partial products can be reduced. By summing up the partial product and a coefficient, a final result can be produced. For Booth coding of other different substrates, in the case of carry-free multiplication, the same amount of modification must be performed for the no-preset preset formatting, post-formatting, and partial product to eliminate the possible carry. Therefore, by the synchronization signal CLK, the Buss encoder 604 calculates the continuous 3-bit data segment itself, and controls the Buss multiplexer 605 through the bus bar PPSEL. The signal on the bus PPSEL causes the Buss multiplexer 105 to select one of the five partial products ((-2B, -B, 0, B, 2B), wherein the five partial product and the multiplicand operand OP B. These partial products are all generated by the partial product generator 603. The partial product generator 603 multiplies the multiplicand operand OP B by 0, so that a partial product 0 can be generated; the partial product generator 603 will be multiplied The number operand OP B is multiplied by 1, so that a partial product B can be generated. The partial product generator 603 multiplies the multiplicand operand OP B by -1, so that a partial product -B can be generated. The partial product generator 603 will be multiplied The number operand OP B is multiplied by 2, so that a partial product 2B can be generated. The partial product generator 603 multiplies the multiplied operand OP B At -2, a partial product -2B can be generated. For those skilled in the art, the partial product generator 603 can be used to obtain the complement of the multiplicand operand OP B or to shift the multiplicand operand OP B to the left or to take the multiplicand operator first. The complement of OP B, and then shift the result of the complement to the left, you can get the product of these five parts.

If the opcode detector 611 detects a normal multiply instruction, the signal CARRLESS is not enabled. Therefore, the carry-free preformat unit 612 simply transfers the multiplier operand OP A received by the first operand register 601 to the Booth encoder 604. If the opcode detector 611 detects a carry-free multiply instruction, it activates the signal CARRLESS. Therefore, the carry-free preformat unit 612 formats the multiplier into an even portion and an odd portion (as shown by the even portion 512 and the odd portion 522 of FIG. 5), and sequentially checks the Booth code.

The sync signal CLK causes the Buss encoder 604 to check the consecutive 3-bit data segments it has received, and causes the compressor 606 to store the corresponding partial product until all data segments have been checked. If the carry signal CARRYLESS is not enabled (ie, a normal multiply instruction is detected), the partial product is assigned to the inputs A, B, and C of the carry storage adder 608 for generating a bus on the CARRIES. The carry bit, and on the bus SUMS, produces a total bit. The full adder 610 adds the bits on the bus SSUM to generate a final result of 128 bits on the bus RESULT, where the final result is a 2's complement. For example, if the signal CARYLESS is not enabled, the left shifter 609 will pass the value on the bus line SUMS directly to the full adder 610. If the signal CARYLESS is enabled (that is, when a carry-free multiply instruction is detected), The carry bits output by all carry store adders 608 are invalidated (i.e., set to zero). Only the summing bits output by the carry storage adder 608 are valid. In a possible embodiment, the even portion of the multiplier operand OP A is assigned to the inputs A, B, and C of the carry store adder 608 for generating the even bits of the even portion on the bus SUMS. . The summing bits of these even parts are stored in the register 613. Next, the odd portion of the multiplier operand OP A is assigned to the inputs A, B, and C of the carry store adder 608 for generating the odd majority of the sum bits on the bus SUMS. The summing bits of these odd parts are shifted left by one bit by the left shifter 609. In both embodiments, the full adder 610 receives a value of zero through the bus bar CARRIES. After the bus line SUMS generates the odd-numbered partial sum bits, by mutually exclusive or (XOR) the data (even part) stored in the register 613 and the data (odd part) on the bus RESULT, A final no-carry result is obtained. In a possible embodiment, a mutual exclusion or operation may be performed using a XOR gate.

The multiplication unit 600 of the present invention can perform general multiplication operations and carry-less multiplication operations. The multiplication unit 600 has logic, circuitry, means or microcode, such as microinstructions or native instructions, or a combination of logic, circuitry, devices or microcode, or other executable Other equivalent components of operation. In a possible embodiment, the elements used to perform the above operations may be used by other circuits, microcodes, and the like. These circuits or microcode are used for other operations of the processor or other device. In this embodiment, the microcode is a noun associated with a plurality of microinstructions. A microinstruction (also known as a native instruction) is an instruction that consists of a single Yuan executed. For example, the microinstructions can be directly executed by a reduced instruction set computer (RISC). For a Complex Instruction Set Computer (CISC), such as an x86 compatible microprocessor, x86 instructions are converted to microinstructions and executed by at least one unit within the CISC microprocessor. Microinstructions.

Those skilled in the art will appreciate that the opcode detector 611, the carry-free pre-format unit 612, and the left shifter 609 are combined with the compressor 606 and the full adder 610, with minor modifications, and do not cause the processor. The hardware has become very complicated. However, the benefits of the present invention (e.g., low power loss, high reliability, debug and short test time) are much greater than the performance characteristics of the present invention.

Figure 7 is a carry-only multiplication method of the present invention. In method 701, a processor, microprocessor or other device executes a general multiply instruction or a carry-free multiply instruction. Then, the flow proceeds to step 702.

In step 702, the next multiplication instruction is retrieved and executed, and the captured result is provided to a multiplication unit. Next, the flow proceeds to step 703.

In step 703, a calculation is performed to determine whether the multiply unit has received a carry-free multiply instruction. If the multiply unit does not receive a carry-free multiply instruction, step 705 is performed. If the multiply unit receives a carry-free multiply instruction, then step 704 is performed.

In step 705, the multiplication unit performs a general multiplication operation. The multiplication unit uses Booth coding and compression techniques to reduce the number of partial products and produce a final result. Next, step 713 is performed.

In step 704, the even-numbered bits of the multiplier are checked, and based on the result of the check, a partial score of the multiplicand is obtained. The detailed explanation is that a multiplier will be shipped. The value of the odd-numbered bits of the operator is modified to 0, and then according to the Booth coding technique, in the modified result, the continuous 3-bit data segment is used to obtain the product of the complex part, and the total of the partial products The merge does not occur in the carry. Since the value of the odd-numbered bits of the multiplier operator is 0, all carry-over phenomena that may be caused by the Bussian code are excluded. Next, step 706 is performed.

In step 706, by the Wallace tree structure in the compressor, the value of the carry bit is set to zero, that is, the carry bit in the Wallace tree is not enabled. Next, step 707 is performed.

In step 707, the product of the headquarters is added according to the even part to obtain the first carry-free total result SUM1. The detailed description is that all partial products are mutually exclusive or (XOR) operated to generate a first carry-free summed result SUM1. Next, step 708 is performed.

In step 708, the multiplier operand is shifted right by 1 bit. Next, step 709 is performed.

In step 709, the even-numbered bits of the shifted multiplier are checked, and based on the result of the check, a partial product of the multiplicand is obtained. In detail, the value of the odd-numbered bits of the right-shifted multiplier operator is set to 0 to generate an odd-numbered portion of the multiplier operand. According to the Booth coding technique, a continuous 3-bit data segment of the odd-numbered portion is determined to select a complex partial product. Based on these partial products, a result of a carry-free multiplication can be obtained. Then, step 710 is performed.

In step 710, the partial product of the multiplicand is summed to obtain a second carry-free sum result SUM2. The detailed description is that the partial product obtained by the odd part is mutually exclusive ORed to obtain a second non-carrying addition. The total result is SUM2. Then, step 711 is performed.

In step 711, the second carry-free addition result SUM2 is shifted left by 1 bit. Next, step 712 is performed.

In step 712, the second carry-free sum result SUM2 after the left shift is added to the first carry-free sum result SUM1 to generate a final carry-free multiplication result. Next, step 713 is performed.

In step 713, this process is completed.

While the foregoing has been described in detail, the preferred embodiments of the invention For example, since the 64-bit non-carry multiplication is a relatively common size in current processors and other devices, in the above, the 64-bit non-carry multiplication is described in more detail. However, the invention is also applicable to other processors or devices having different numbers of bits. Therefore, the present invention is not limited to 64 bits.

In addition, many multiplying units utilize a multi-channel device. For example, a 64-bit operand is divided into four 32-bit operands. The multiplication unit produces a number of product results based on the four operands. These product results are summed together to produce a final result. One of the objects of the present invention is to generate hardware by using the Booth code and partial product used in general multiplication.

Finally, although the above is based on the Booth coding technique of the substrate-4, it is not intended to limit the invention. In order to use the existing Booth coded hardware architecture, in other embodiments, a substrate greater than 4 can be used. To use the Booth code, but do not want to generate a carry, you can select a specific bit of an input operand and set the value of the unselected bit to zero. Therefore, the input operand can be formatted into a complex portion.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 600‧‧‧ multiplication unit

101, 601‧‧‧ first operand register

102, 602‧‧‧ second operand register

103, 603‧‧‧ partial product generator

104, 604‧‧‧ Booth encoder

105, 605‧‧‧Bus multiplexer

106, 606‧‧‧ Compressor

107, 607‧‧‧ Product Synchronizer

108, 608‧‧‧ Carry Storage Adder

109, 610‧‧‧Full adder

301, 302, 502‧‧‧Operating elements

303, 503, 513, 523‧‧ ‧ bits

304~306, 504~508, 514~518, 524~528‧‧‧ data segment

307~309‧‧‧ partial product

310‧‧‧Multiplication results

501, 511, 521‧‧‧ expression

512‧‧‧ even part

522‧‧‧odd parts

609‧‧‧ Left shifter

611‧‧‧Operation Code Detector

612‧‧‧No carry preformat unit

613‧‧‧ register

Figure 1 is a block diagram of a 64-bit multiplying unit in a microprocessor or similar device.

Figure 2 is a table illustrating how the multiplication unit of Figure 1 uses the Booth code to reduce the number of partial products.

Figure 3 illustrates how to use the Booth coding technique to reduce the number of partial products in a 4-bit multiplication operation.

Figure 4 shows the Booth coding coefficients of the present invention which can perform a carry-free multiplication.

Figure 5 is a diagram of how the present invention formats an operand.

Figure 6 is a block diagram of a carry-free multiplication unit of the present invention.

Figure 7 is a flow chart of the carry-in multiplication of the present invention.

600‧‧‧multiplication unit

601‧‧‧First operand register

602‧‧‧Second operand register

603‧‧‧Partial product generator

604‧‧‧ Booth encoder

605‧‧‧Bus multiplexer

606‧‧‧Compressor

607‧‧‧Product Synchronizer

608‧‧‧ Carry Storage Adder

609‧‧‧ Left shifter

610‧‧‧Full adder

611‧‧‧Operation Code Detector

612‧‧‧No carry preformat unit

613‧‧‧ register

Claims (45)

A carry-free multiply device for performing a carry-free multiplication operation, comprising: a carry-free pre-format unit for receiving a multiplier operand, and formatting the multiplier operand into a complex part, wherein the parts include An even-numbered portion and an odd-numbered portion; a Buss multiplexer that receives a first partial product of a multiplicand operation element and a complex second partial product; a Booth encoder that receives and determines the portions and causes the The Buss multiplexer selects the first partial products, wherein by means of the portions, the second partial product is prevented from being selected, and the second partial product causes a carry phenomenon; a compressor passes through the Booth The multiplexer is coupled to the Buss encoder for summing the first partial products through a complex carry storage adder, the carry storage adder generating a complex total bit and a complex carry bit, wherein the carry The storage adder is arranged in a Wallace tree structure. When the carry-in multiplication operation is performed, the carry bit is not enabled; a left shifter coupled to the compressor is used to Performing the carry-in multiplication operation shifting the output of the summed bits corresponding to the odd portion to the left by at least one bit; and a mutually exclusive or gate coupled to the output of the compressor and the output of the left shifter And performing, in performing the carry-in multiplication operation, the summed bits corresponding to the left shift corresponding to the odd portion and the summed bits of the even portion are mutually exclusive OR operations. The non-carrying multiplying device of claim 1, wherein The format of the multiplier operand is a 2's complement. The non-carrying multiplying device of claim 1, wherein the even portion has a value of an even bit of the multiplier, and a value of an odd bit of the multiplier, wherein the even portion The value of the odd bit having the multiplier operand is set to 0; and the odd portion has the value of the odd bit of the multiplier operand, and the value of the even bit of the multiplier operand, where The odd-numbered portion has the value of the even-numbered bit of the multiplier operand set to 0, and the odd-numbered portion has a value shifted to the right by 1 bit; wherein the even-numbered bits of the multiplier operand are included The last significant bit of the multiplier operand. The carry-in multiplication device of claim 1, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The non-carrying multiplying apparatus of claim 1, wherein the first partial product comprises a complex first multiplication of the multiplicanded operand, the first multiplication comprising: multiplying the multiplicanded operation element 0; and multiply the multiplicand operand by 1. The non-carrying multiplying apparatus of claim 5, wherein the second partial product comprises a complex second multiplication of the multiplicanded operand, the second multiplications comprising: multiplying the multiplicanded operation element Upper 2; and multiply the multiplicand operator by -2. The non-carrying multiplying device of claim 1, wherein the non-carrying multiplying device is a multiplying unit or a set in a processor A multiplication unit in the device. The carry-in multiplication device of claim 7, wherein the multiplication unit is configured to perform a carry-free multiplication operation and a normal multiplication operation. A method for performing a carry-free multiplication operation, comprising: formatting a multiplier operation element into a complex part in a multiplication unit in a processor; determining the parts through a Booth encoder, and selecting a complex first partial product of a multiplicand operation element, wherein by means of the portions, the complex second partial product of the multiplicanded operation element is prevented from being selected, and the second partial product causes a carry phenomenon; a carry storage adder processing the first partial product for generating a complex sum bit and a plurality of carry bits, wherein the carry storage adders are arranged in a Wallace tree architecture and performing the carry-less multiplication The carry bit is not enabled; the output of the Wallace tree is shifted to the left by at least one bit; and the output of the Wallace tree is mutually exclusive ORed to produce a carry-free multiplication result . The method of claim 9, wherein the multiplier operand is in the form of a 2's complement. The method of claim 9, wherein the portion comprises: an even portion, a value having an even bit of the multiplier, and a value of an odd bit of the multiplier, wherein The value of the odd bit of the multiplier operand that the even part has is set to 0; An odd-numbered portion having a value of an odd-numbered bit of the multiplier operation element and a value of an even-numbered bit of the multiplier operation element, wherein the odd-numbered portion has an even-numbered bit of the multiplier operation element set 0, and the value of the odd portion is shifted to the right by 1 bit; wherein the even bit of the multiplier is included in the even bit of the multiplier. The method of claim 9, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The method of claim 9, wherein the first partial product comprises a complex first multiplication of the multiplicanded operand, the first multiplication comprising: multiplying the multiplicand operator by 0; Multiply the multiplicand operand by 1. The method of claim 13, wherein the second partial product comprises a complex second multiplication of the multiplicand operand, the second multiplications comprising: multiplying the multiplicand operator by 2; And multiplying the multiplicand operator by -2. The method of claim 9, wherein the operands are all operands having 64 bits. A carry-free multiply device for performing a carry-free multiplication operation, comprising: a first operand register, receiving a first operand for performing the carry-free multiplication operation; and a second operand register Receiving a second operand for performing The non-carry multiplication operation; an opcode detector, receiving a carry-free multiplication instruction, and enabling a carry-free signal according to the non-carry multiplication instruction; and a non-carry pre-format unit coupled to the first operation element a memory, when the carry-free signal is enabled, the non-carry pre-format unit formats the first operand into a complex portion, wherein the portions include an even portion and an odd portion, wherein a Buss multiplexer Receiving a complex first partial product of the second operand and a complex second partial product, and a Buss encoder, by means of the portions, causes the Buss multiplexer to avoid selecting the second partial product, the The two-part product causes a carry phenomenon; a compressor passes through the complex carry storage adder to add the first partial product of the second operand, and the carry storage adder generates a complex total bit and a complex carry bit The carry storage adders are arranged in a Wallace tree architecture, and when the non-carry signal is enabled, the carry bits are not enabled; a left shifter is coupled a compressor for shifting an output of the summed bits corresponding to the odd portion to the left by at least one bit when performing the carry-less multiplication operation; and a mutually exclusive or gate coupled to the output of the compressor and An output of the left shifter for mutually exclusive repulsing the left-shifted corresponding bit corresponding to the odd-numbered portion and the even-numbered portion of the even-numbered portion when performing the carry-less multiplication operation Operation. The non-carrying multiplying device of claim 16, wherein the format of the first and second operands is a complement of two. A carry-free multiplying device as described in claim 16 of the patent application, The even number portion has a value of an even bit of the first operand, and a value of the odd bit of the first operand, wherein the even bit portion has a value of an odd bit of the first operand set And the odd portion has a value of an odd bit of the first operand, and a value of an even bit of the first operand, wherein the odd portion has an even bit of the first operand The value is set to 0, and the value of the odd portion is shifted to the right by 1 bit; wherein the even bit of the first operand includes the last significant bit of the first operand. The carry-less multiplying device of claim 16, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The non-carrying multiplying device of claim 16, wherein the first partial product comprises a complex first multiplication of the second operational element, the first multiplications comprising: multiplying the second operational element by 0; And multiplying the second operand by one. The non-carrying multiplying device of claim 20, wherein the second partial product comprises a complex second multiplication of the second operand, the second multiplications comprising: multiplying the second operand by 2 And multiplying the second operand by -2. A carry-less multiply device as described in claim 16, wherein the carry-in multiply device is a multiplying unit in a processor or a multiplying unit in a device. If there is a carry-in multiplication device as described in claim 22, The multiplication unit is configured to perform a carry-free multiplication operation and a normal multiplication operation. A method for performing a carry-free multiplication operation, comprising: receiving, in a multiplication unit in a processor, a first operation element and a second operation element for performing the carry-less multiplication operation; a carry multiplication instruction enabling a carry signal; when the carry signal is enabled, the first operand is formatted into a complex portion, wherein a Booth encoder avoids selecting the second by using the portion The second partial product of the operands, the second partial product causing a carry phenomenon; the complex first load storage adder adds the first partial product of the second operational element, and the carry storage adder generates a complex addition a total bit and a plurality of carry bits, wherein the carry store adders are arranged in a Wallace tree structure, and when the carry signal is enabled, the carry bits are not enabled; the Wallace is enabled The output of the tree, shifted to the left by at least one element; and a mutually exclusive OR operation on the output of the Wallace tree to produce a carry-free multiplication result. The method of claim 24, wherein the format of the first and second operands is a complement of two. The method of claim 24, wherein the portion comprises: an even portion having a value of an even bit of the first operand, and a value of an odd bit of the first operand, wherein the The even-numbered portion has the value of the odd-numbered bit of the first operand set to 0; An odd-numbered portion having a value of an odd-numbered bit of the first operational element and a value of an even-numbered bit of the first operational element, wherein a value of an even-numbered bit of the first operational element having the odd-numbered portion is set 0, and the value of the odd portion is shifted to the right by 1 bit; wherein the even bit of the first operand includes the last significant bit of the first operand. The method of claim 24, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The method of claim 24, wherein the first partial product comprises a complex first multiplication of the second operational element, the first multiplications comprising: multiplying the second operational element by 0; The second operand is multiplied by 1. The method of claim 28, wherein the second partial product comprises a complex second multiplication of the second operand, the second multiplications comprising: multiplying the second operand by 2; The second operand is multiplied by -2. The method of claim 24, wherein the operands are all operands having 64 bits. A carry-free multiply device that formats a first operand for performing a carry-free multiplication operation, comprising: an opcode detector, receiving a carry-free multiply instruction, and enabling one according to the carry-free multiply instruction No carry signal; and a carry-free pre-format unit, when the carry-free signal is enabled, The non-carry pre-format unit formats the first operand into a complex portion, wherein a Booth encoder enables the one multiplexer to select a complex first partial product of a second operand, and Preventing the Boots multiplexer from selecting a complex second partial product of the second operand, the second partial product causing a carry phenomenon; wherein the first partial product performs a mutual exclusion operation to generate a No carry multiplication result. The non-carrying multiplying device of claim 31, wherein the format of the first and second operands is a complement of two. The non-carrying multiplying device of claim 31, wherein the portion comprises: an even portion, a value having an even bit of the first operand, and a value of an odd bit of the first operand The value of the odd bit of the first operand having the even portion is set to 0; and an odd portion having the value of the odd bit of the first operand, and the even bit of the first operand a value of a digit, wherein the odd-numbered portion has a value of an even-numbered bit of the first operand set to 0, and the odd-numbered portion has a value shifted to the right by 1 bit; wherein the first operand The even bit of the first bit includes the last significant bit of the first operand. A carry-less multiply device as described in claim 31, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The non-carrying multiplying device of claim 31, wherein the first partial product comprises a complex first multiplication of the second operational element, the first multiplications comprising: Multiplying the second operand by 0; and multiplying the second operand by 1. The non-carrying multiplying device of claim 35, wherein the second partial product comprises a complex second multiplication of the second operand, the second multiplication comprising: multiplying the second operand by 2 And multiplying the second operand by -2. The non-carrying multiplying device of claim 31, wherein the non-carrying multiplying device is a multiplying unit in a processor or a multiplying unit in a device. The carry-in multiplication device of claim 37, wherein the multiplication unit is configured to perform a carry-free multiplication operation and a normal multiplication operation. A method for performing a carry-free multiplication operation, comprising: receiving a carry-free multiplication instruction in a multiplication unit in a processor, and performing the absence with a first operation element and a second operation element a carry-multiplication operation; according to the carry-in multiplication instruction, enabling a carry-free signal; and when the carry-free signal is enabled, formatting the first operand into a complex portion, wherein a Buss encoder uses the Part, causing a Buss multiplexer to select a complex first partial product of the second operand, and avoiding having the Buss multiplexer select a complex second partial product of the second operand, the second partial product A carry-in phenomenon is caused; wherein the first partial products are subjected to a mutual exclusion operation to generate a carry-free multiplication result. The method of claim 39, wherein the format of the first and second operands is a complement of two. The method of claim 39, wherein the portion comprises: an even portion having a value of an even bit of the first operand, and a value of an odd bit of the first operand, wherein the The even-numbered portion has the value of the odd-numbered bit of the first operand set to 0; and an odd-numbered portion having the value of the odd-numbered bit of the first operand, and the even-numbered bit of the first operand a value, wherein a value of an even bit of the first operand having the odd portion is set to 0, and a value of the odd portion is shifted to the right by 1 bit; wherein an even bit of the first operand In the element, the last significant bit of the first operand is included. The method of claim 39, wherein the Booth encoder comprises a substrate-4 encoder for selecting a partial product. The method of claim 39, wherein the first partial product comprises a complex first multiplication of the second operational element, the first multiplications comprising: multiplying the second operational element by 0; The second operand is multiplied by 1. The method of claim 43, wherein the second partial product comprises a complex second multiplication of the second operand, the second multiplications comprising: multiplying the second operand by 2; The second operand is multiplied by -2. The method of claim 39, wherein the operands are all operands having 64 bits.