TWI488142B - An operation method of a hierarchical buffer for application of vector graphics rasterization - Google Patents

Description

Operation method of hierarchical buffer applied to vector graphics lattice

The invention relates to an operation method, in particular to an operation method of a hierarchical buffer applied to a vector graphics dot matrix and a structure of a hierarchical buffer.

The conventional operation method applied to vector graphics dot matrixization is to find the intersection point intersecting a vector figure with a single scan line, and then sort the horizontal coordinate positions of the intersection points from left to right to find all the scan lines. The Winding Count of the pixel, however, the operation method requires an additional sorting step, which will greatly increase the drawing time of the vector graphics.

The main object of the present invention is to provide an operation method for a hierarchical buffer applied to a vector graphics dot matrix, which can accelerate the winding count operation process of a pixel in a vector graphics dot matrix, and includes the following steps. First, providing a display; providing a hierarchical buffer, the hierarchical buffer includes a first hierarchical buffer, a second hierarchical buffer, and a third hierarchical buffer, the first hierarchical buffer having a first buffer group, a second buffer group, and a third buffer group, the number of addresses of the first level buffer is greater than the number of addresses of the second level buffer, the second level buffer The number of addresses is greater than the number of addresses of the third level buffer; the first level buffer, the second level buffer, and the third level buffer are cleared, and all addresses of the first level buffer correspond to The value is set to 0, the flag of the second level buffer and the third level buffer is set to a reset state; the display of the display is displayed with a vector graphic, the display is at least A scan line scans the vector pattern. If the vector pattern intersects the scan line to generate at least one intersection, the value of the address of the first level buffer corresponding to the intersection may be updated, and the updated The flag corresponding to the address of the second level buffer and the third level buffer corresponding to the value is updated to a set state; the third level buffer is read and the flag is determined to be a set or reset state, If the flag is in the reset state, reading a flag below the third-level buffer, and if the flag is in the set state, sequentially reading each of the second-level buffers corresponding to the flag. a flag of the address and determining whether the flag is a set or reset state; if it is a set state, reading the first level buffer corresponding to the flag; outputting at least one first from the first buffer group And a second value, the at least one third value and the fourth value are output from the second buffer group, and at least a fifth value and a sixth value are output from the third buffer group, the first value, The second value, the third value, the fourth The value, the fifth value, and the sixth value are the number of windings corresponding to the pixel position of the screen, and the first hierarchical buffer, the second hierarchical buffer, and the third hierarchical buffer are used in the present invention. Constructing the hierarchical buffer, when the third-level buffer reads the state of its flag, if the scan line scans the vector graphic, and the pixels of the scan line do not intersect the vector graphic, The flag corresponding to the third-level buffer is reset, and the step of accessing the data to the second-level buffer and the first-level buffer may be omitted, thereby effectively reducing the drawing of the graphic. time.

Referring to FIG. 1 , which is a preferred embodiment of the present invention, a method for computing a hierarchical buffer applied to a vector graphics dot matrix includes the following steps. First, refer to the step of FIG. 1 (a) And FIG. 2A, a display 200 is provided. The screen 210 of the display 200 has a width W, which is the number of pixels representing the width of the screen 210. Then, refer to step (b) of FIG. 1 and FIG. 3, a hierarchical buffer 100 is provided. The hierarchical buffer 100 includes a first hierarchical buffer 110, a second hierarchical buffer 120, and a third hierarchical buffer 130. The first hierarchical buffer The number of addresses in the area 110 is greater than the number of addresses in the second level buffer 120. The number of addresses in the second level buffer 120 is greater than the number of addresses in the third level buffer 130, in this embodiment. The number of addresses of the first level buffer 110 is 32, the number of addresses of the second level buffer 120 is 8, and the number of addresses of the third level buffer 130 is 2. The first level buffer 110 There are eight buffer groups 111, each of which has a buffer group 111 Four addresses, the eight addresses of the second level buffer 120 are all corresponding to each of the buffer groups 111 of the first level buffer 110, and two of the third level buffers 130 The address points correspond to the four addresses of the second level buffer 120, and the width W of the screen 210 of the display 200 is the width of the first level buffer 110; after that, please refer to the steps of FIG. (c) and FIG. 4, the first level buffer 110, the second level buffer 120, and the third level buffer 130 are cleared, and the data type of the address of the first buffer 110 is a numerical value. The data type of the second buffer 120 and the third buffer 130 may be a flag, which may be represented as a set or a reset state, or may be a positive integer or a negative integer. Preferably, the setting state of the embodiment is represented by 1, and the reset state is represented by 0. In step (c), the values corresponding to all the addresses of the first hierarchical buffer 110 are set to 0. The flag of the second level buffer 120 and the third level buffer 130 is set to a reset state, and further, the first level is slowed down. Relations, region 110 and the second class generated between the buffer 120 represented by the following formula:

Wherein SB _L2 represents the second level buffer 120, SB _L1 represents the first level buffer 110, and HF _{L1_L2} is the number of addresses of the second level buffer corresponding to the address of the first level buffer 110. The relationship between the second level buffer 120 and the third level buffer 130 can be expressed as:

Wherein the third layer SB _L3 representing the buffer 130, SB _L2 representing the second level buffer 120, HF _{L2 _ L3} third layer buffers corresponding to the flag 130 to the second level address for the buffer 120 Preferably, the relationship between the second level buffer 120 and the third level buffer 130 can be expanded into a general formula of the M-1th level buffer and an Mth level buffer, which are expressed as follows:

Where SB _LM represents the Mth level buffer, SB _LM-1 represents the M-1th level buffer, M>2, HF _{LM-1 _ LM} is an Mth level buffer flag corresponding to the M-1 The number of addresses in the hierarchy buffer.

Next, referring to steps (d), 2B, and 5 of FIG. 1, the screen 210 of the display 200 is displayed with a vector graphics G, and the display 200 scans the at least one scan line. The vector graphic G, or, in another embodiment, the display 200 may scan the vector graphic G by a plurality of scan lines, and if the vector graphic G intersects the scan line to generate one or more intersection points, the display The value of the address of the first-level buffer 110 corresponding to the intersection point can be updated by a program, and the equation is as follows: SB [ ]= SB [ ] + direct ( E ), where α is the horizontal coordinate address of the intersection, and direct ( E ) is the direction of the effective edge of the vector graph G. If the direction is clockwise, it is represented by the value 1, if the direction is counterclockwise, the value is -1 indicates that the flag of the second-level buffer 120 and the address of the third-level buffer 130 corresponding to the value after the status update is updated to the set state, as shown in FIG. 5; Referring to step (e) of FIG. 1, the third-level buffer 130 is sequentially read from left to right and judged whether the flag is set or reset. If the flag is reset, the read is read. The third level buffer 130 is below a flag. If the flag is in the set state, the flag of the address of the second level buffer 120 corresponding to the flag is read and the flag is determined to be set or The reset state, if the flag is in the reset state, the next flag of the second level buffer 120 is read, and if it is the set state, the first level buffer 110 corresponding to the flag is read. For the value in the buffer group 111, refer to step (f) of FIG. 1 in reading the hierarchical buffer. In the process, if the state of the flag of the third-level buffer 130 and the second-level buffer 120 or the values of the buffer groups 111 of the first-level buffer 110 are known, the buffer may be The known state or known value is cleared; finally, please refer to step (g) of FIG. 1 , taking the three buffer groups of the buffer group 111 as an example, if each buffer group has only two bits And outputting a first value and a second value from the first buffer group, outputting a third value and a fourth value from the second buffer group, and outputting a fifth value from the third buffer group a value and a sixth value, the first value, the second value, the third value, the fourth value, the fifth value, and the sixth value are windings corresponding to pixel positions of the screen 210 Winding Count, and so on. If each buffer group has four addresses, a first value, a second value, a third value, and a fourth value are output from the first buffer group. Outputting a fifth value, a sixth value, a seventh value, and an eighth number from the second buffer group a value, a ninth value, a tenth value, an eleventh value, and a twelfth value are outputted from the third buffer group, the first value to the twelfth value being corresponding to the screen 210 The number of windings of the pixel position, since the vector pattern G needs to determine the pixel area to be filled in the dot matrix stage, and each pixel of the vector pattern G has its corresponding winding number, each pixel Whether the coloring is determined by the number of windings of the pixel and the coloring rule of the vector graphic G, so that each of the buffer groups 111 of the present invention can effectively output the number of windings required for the vector graphic G, in this implementation In the example, step (e) and step (f) can be completed by the following program:

Where K is the product of the hierarchical correlation parameters of the first level buffer 110 to the Mth level buffer, that is, HF _{LM-1_LM} × HF _{LM-2_LM-1} × ... × HF _{L2_L1} .

In the present invention, the hierarchical buffer 100 is constructed by the first hierarchical buffer 110, the second hierarchical buffer 120, and the third hierarchical buffer 130. When the third hierarchical buffer 130 reads the state of its flag. If the scan line scans the vector graphic G, and the pixels of the scan line do not intersect the vector graphic G, the flags corresponding to the third level buffer 130 are reset. At this time, the step of accessing the second-level buffer 120 and the first-level buffer 110 can be omitted, so that the drawing time of the vector graphics can be effectively reduced.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100. . . Hierarchical buffer

110. . . First level buffer

111. . . Buffer group

120. . . Second level buffer

130. . . Third level buffer

(a) providing a display

(b) providing a hierarchical buffer, the hierarchical buffer comprising a first level buffer, a second level buffer and a third level buffer, the first level buffer having a first buffer Group, a second buffer group, and a third buffer group

(c) clearing the first level buffer, the second level buffer, and the third level buffer

(d) causing the screen of the display to display a vector graphic. If the vector graphic intersects with a scan line to generate an intersection, the value of the first level buffer corresponding to the intersection can be updated, and the updated The flag corresponding to the address of the second level buffer and the third level buffer corresponding to the value is updated to the set state

(e) sequentially reading the third-level buffer and determining whether the flag is set or reset. If the flag is reset, reading a flag below the third-level buffer, if the flag When the flag is set, the flag of the second-level buffer corresponding to the flag is read and the flag is determined to be a set or reset state. If the flag is set, the corresponding flag is read. The first level buffer

(f) ‧‧‧ If the state of the third-level buffer and the flag of the second-level buffer or the buffer group of the first-level buffer are known, the buffer Known state or known value clear

(g) ‧ ‧ output at least a first value and a second value from the first buffer group, and output at least a third value and a fourth value from the second buffer group, from the third buffer group The group outputs at least a fifth value and a sixth value, the values being the number of windings corresponding to the pixel position of the screen

Figure 1 is a flow chart showing an operation method applied to vector graphics dot matrixing in accordance with a preferred embodiment of the present invention.

2A is a schematic diagram of a display applied to a method of computing a vector graphics dot matrix in accordance with a preferred embodiment of the present invention.

FIG. 2B is a schematic diagram showing the operation of the vector graphics dot matrix on the screen of the display with a vector graphic according to a preferred embodiment of the present invention.

Figure 3 is a schematic diagram of a hierarchical buffer applied to a method of vector graphics dot matrixization in accordance with a preferred embodiment of the present invention.

Figure 4 is a schematic diagram of a clear hierarchical buffer applied to a method of vector graphics dot matrixization in accordance with a preferred embodiment of the present invention.

Figure 5 is a schematic diagram of a hierarchical buffer applied to a method of vector graphics dot matrixization in accordance with a preferred embodiment of the present invention.

100‧‧‧Strategy buffer

110‧‧‧First level buffer zone

111‧‧‧Buffering group

120‧‧‧Second level buffer zone

130‧‧‧third-tier buffer zone

Claims (10)

An operation method for vector graphics dot matrixization, comprising: providing a display; providing a hierarchical buffer, the hierarchical buffer comprising a first hierarchical buffer, a second hierarchical buffer, and a third a first level buffer group having at least a first buffer group, a second buffer group, and a third buffer group, the first buffer group, the second buffer group, and the first The three buffer groups each have at least two addresses, and the number of addresses of the first level buffer is greater than the number of addresses of the second level buffer, and the number of addresses of the second level buffer is greater than the number of addresses. The number of addresses of the three-level buffer, the value of each of the first buffer group, the second buffer group, and the third buffer group may be 0, a positive integer, or a negative integer; The first level buffer, the second level buffer, and the third level buffer, the values corresponding to all the addresses of the first level buffer are set to 0, the second level buffer and the third level buffer The flag of the zone is set to the reset state. So that the display screen of a vector graphics display, the display system at least one of the scan lines scanned vector graphics, vector graphics if the scan line intersects the generating the at least one intersection is The value of the address of the first-level buffer corresponding to the intersection may be updated, and the flag of the second-level buffer and the address of the third-level buffer corresponding to the updated value is Update to the set state; read the third-level buffer and determine whether the flag is set or reset state, if the flag is reset, read a flag below the third-level buffer, if the flag When the flag is set, the flag of the address of the second-level buffer corresponding to the flag is read and the flag is determined to be a set or reset state. If the flag is set, the flag is read. Corresponding to the first level buffer; and outputting at least a first value and a second value from the first buffer group, and outputting at least a third value and a fourth value from the second buffer group, The third buffer group outputs at least a fifth value and a sixth value, the first value, the second value, the third value, the fourth value, the fifth value, and the sixth value are corresponding to The number of turns of the pixel position of the screen. The method for applying a vector graphics dot matrix as described in claim 1 wherein the relationship between the first level buffer and the second level buffer is expressed by: Where SB _L2 represents the second level buffer, SN _L1 represents the first level buffer, and HF _{L1_L2} is the number of addresses of the second level buffer corresponding to the address of the first level buffer. The method for applying the vector graphics dot matrixization according to the first aspect of the patent application, wherein the relationship between the second hierarchical buffer and the third hierarchical buffer can be expressed by a general formula: Where SB _LM represents the Mth level buffer, the Mth level buffer may be the third level buffer, and SB _LM-1 represents the M-1th level buffer, and the M-1th level buffer is For the second level buffer, M>2, HF _{LM-1_LM} is the number of addresses of the Mth level buffer corresponding to the address of the M _-1th level buffer. An operation method for vector graphics dot matrixization according to claim 1, wherein in the step of causing the display of the display to display a vector graphic, the display is to scan the vector graphic with at least one scan line, The value of the address of the first-level buffer corresponding to the intersection is updated by the following equation: The method for calculating a vector graphics dot matrix as described in claim 1, wherein the screen width of the display is the width of the first level buffer. Applied to vector graphics as described in claim 1 a matrixing operation method, wherein in the step of reading the third-level buffer, the method further includes a state of the flag of the third-level buffer and the second-level buffer or the first-level buffer If the values of the buffer groups are known, the known state or known value in the buffer can be cleared. A hierarchical buffer includes: a first level buffer having at least a first buffer group and a second buffer group, wherein the first buffer group and the second buffer group are each Having at least two addresses; a second level buffer having at least one first address and a second address, the first address being corresponding to the first buffer group of the first level buffer All addresses, the second address is all addresses corresponding to the second buffer group of the first level buffer; and a third level buffer having at least one address, the address corresponding to The first address of the second level buffer and the second address. The hierarchical buffer of claim 7, wherein the relationship between the first level buffer and the second level buffer is expressed by: Where SB _L2 represents the second level buffer, SB _L1 represents the first level buffer, and HF _{L1_L2} is the number of addresses of the second level buffer corresponding to the address of the first level buffer. The hierarchical buffer of claim 7, wherein the relationship between the second hierarchical buffer and the third hierarchical buffer is expressed by a general formula: Where SB _Lm represents the Mth level buffer, the Mth level buffer may be the third level buffer, SB _Lm-1 represents the M-1 level buffer, and the M-1 level buffer is For the second level buffer, M>2, HF _{LM-1_LM} is the number of addresses of the Mth level buffer corresponding to the address of the M _-1th level buffer. The hierarchical buffer of claim 7, wherein the value of each of the first buffer group and the second buffer group of the first level buffer may be 0, a positive integer or A negative integer.