TWI486583B - Method of testing semiconductor substrate - Google Patents

Description

Method for detecting semiconductor substrate

The invention relates to a detection method, in particular to a method for detecting a semiconductor substrate.

Since the flip chip technology has the advantages of reducing the chip package area and shortening the signal transmission path, it has been widely used in the field of chip packaging, for example, Direct Chip Attached (DCA), Chip Scale Package (Chip Scale Package, CSP) and multi-chip module (MCM) and other types of package modules can use the flip chip technology to achieve the purpose of packaging.

In the flip chip packaging process, since the thermal expansion coefficient of the wafer and the circuit substrate is very different, the conductive bumps on the periphery of the wafer cannot form a good joint with the corresponding contacts on the circuit substrate, so that the conductive bumps may be peeled off from the circuit substrate. . On the other hand, with the increase in the integration of the integrated circuit, the thermal expansion coefficient and the warpage caused by the thermal expansion coefficient between the wafer and the circuit substrate are also mismatched. Increasingly, the result is a decrease in the reliability of the electrical connection between the wafer and the circuit substrate, and the reliability test fails.

In order to solve the above problem of the difference in thermal expansion coefficient, a process for fabricating a circuit substrate using a semiconductor substrate has been developed. As shown in FIG. 1A, a splicing interposer 7 is added to a package substrate 9 and a semiconductor wafer 8. Between The interposer 7 has a through-silicon via (TSV) 71 and a redistribution layer (RDL) 72 disposed on the via 71 71. Since the semiconductor substrate (that is, the germanium interposer 7) is close to the material of the wafer, the problem caused by the mismatch in the thermal expansion coefficient can be effectively avoided.

Moreover, the conventional semiconductor package connects the semiconductor wafer 8 to the germanium interposer 7, so that the area of the lengthwise direction of the conventional semiconductor package can be further reduced compared with the conventional flip chip package. For example, the minimum line width/line spacing of a flip-chip package substrate can only be 12/12 μm, and when the number of electrode pads (I/O) of a semiconductor wafer is increased, the line width of the existing flip chip package substrate is The line pitch can no longer be reduced, so the area of the flip chip package substrate must be increased to increase the wiring density, and the semiconductor wafer with high I/O number can be connected. In contrast, in the semiconductor package of FIG. 1A, since the germanium interposer 7 can use a semiconductor process to make a line width/line pitch of 3/3 μm or less, when the semiconductor wafer 8 has a high I/O number, the germanium interposer The area of the length and width direction of the 7 is sufficient to connect the semiconductor wafer 8 having a high I/O number, so that the area of the package substrate 9 is not required to be increased, and the semiconductor wafer 8 is electrically connected via the 矽 interposer 7 as an interposer. Up to the package substrate 9.

Moreover, the thin line/wide line spacing characteristic of the tantalum interposer 7 makes the electrical transmission distance short, so that the electrical transmission speed (efficiency) of the semiconductor wafer directly bonded to the package substrate is set in the medium. The electrical transmission speed (efficiency) of the semiconductor wafer 8 on the board 7 is faster (higher).

Further, in the conventional interposer 7, since the number of I/Os of the semiconductor wafer 8 is large, it is necessary to arrange a plurality of layers of the line redistribution structure 72 on the surface of the semiconductor interposer 7 on the surface of the semiconductor interposer 7, for example, at least a three-layer circuit layer electrically connecting the semiconductor wafer 8 and the conductive germanium via 71, and if the plurality of semiconductor wafers 8 are combined, the circuit The redistribution structure 72 can also provide electrical connection between the semiconductor wafers 8. For example, a single semiconductor wafer 8 has 1000 contacts. After the fan out design of the line redistribution structure 72, only 800 contacts are connected to the conductive turns 71, while the other 200 are connected. The dots are used for electrical interconnection between a plurality of semiconductor wafers.

On the other hand, the line width and the line spacing of the package substrate 9 are much larger than the contact pitch of the semiconductor wafer 8. Therefore, the surface of the package substrate 9 is not disposed on the surface of the package substrate 9 (or the number of circuit layers is laid) There is less, such as a layer, so that the conductive germanium vias 71 are directly electrically connected to the contact pads of the package substrate 9 (or electrically connected to the conductive vias 71 and the package substrate 9 by wires).

Since the electrical test of the conventional semiconductor package is the key to mass production, the electrical test of the interposer 7 with the conductive vias 71 is more critical. Specifically, the conductive germanium via 71 is a conductive path electrically connecting the semiconductor wafer 8 and the package substrate 9. If the conductive via 71 is defective, signal transmission between the semiconductor wafer 8 and the package substrate 9 may cause a problem. Therefore, the testing of general semiconductor packages is divided into pre-package chip probe (CP) and post-package functional test (FT).

As shown in FIG. 1B, the pre-package wafer testing method is to place a device under test 6 (ie, the interposer 7 and the semiconductor wafer 8) on a detecting device 1. The detecting device 1 has a pedestal. 10 and an upper cover 11, and the base 10, the component to be tested 6 and the upper cover 11 are brought into close contact with each other, so that the pogo pin 110 of the upper cover 11 is electrically connected to the cymbal intermediate plate 7 The upper side of the electrical contact 70a, and the line 100 of the pedestal 10 and the conductive bump 101 are electrically connected to the electrical contact 70b on the lower side of the 矽 interposer 7 to be replaced by another set of pogo pins )carry out testing.

However, the upper side of the cymbal interposer 7 has a protective layer (not shown) to cover the upper electrical contact 70a, and after the semiconductor wafer 8 is bonded to the lower side of the cymbal interposer 7, The protective layer is removed, so that the pre-package wafer inspection system needs to be combined with the semiconductor wafer 8 to perform electrical and functional detection. Therefore, in the plurality of conductive germanium vias 71, as long as one of the conductive germanium vias 71 detects an abnormality (such as a void or an open circuit), the entire semiconductor package will be scrapped, thereby greatly increasing the manufacturing cost.

Moreover, if the general detection is performed only on the cymbal interposer 7, since the aperture of the conductive cymbal hole 71 is extremely small, so that the spring pin used at present is difficult to align, the line re-laying structure 72 needs to be formed on the cymbal interposer 7. After that, a large area of the electrical contacts 70a, 70b on the line re-wiring structure 72 can be contacted by the spring pin to electrically detect the conductive boring hole 71, but if an abnormality is found, the 矽 interposer 7 needs to be scrapped, thereby wasting the manufacturing material and production time of the line redistribution structure 72, so as to greatly increase the manufacturing cost.

Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for detecting a semiconductor substrate, comprising: providing a semiconductor substrate having a first surface and a second surface opposite to each other, wherein the semiconductor substrate has a plurality of conductive vias penetrating therethrough, The conductive perforation defines a first end surface and a second end surface corresponding to the first and second surfaces; forming a reaction material on the first end surface of the conductive perforation; and heating the second end surface of the conductive perforation to make the conductive perforation The reaction material on the first end face reacts.

In the above detection method, the reaction material is a liquid crystal material, and for example, the liquid crystal material to be formed is in a state of 29 ° C to 35 ° C. Furthermore, the reaction material is formed on the first surface of the semiconductor substrate.

In the above detection method, the heating method is a laser irradiation method. Furthermore, The range of heating includes a second surface of the semiconductor substrate.

In the above detection method, the heat-generating reaction portion of the reaction material becomes a change portion, and the internal essence or appearance of the change portion is different from the internal essence or appearance of the unheated portion of the reaction material.

In the above detection method, the plurality of identical semiconductor substrates are detected, and the coordinates of each of the conductive vias are marked at the time of detection.

As can be seen from the above, the method for detecting a semiconductor substrate of the present invention is to form a reaction material at one end of the conductive via and then heat the other end, and if the conductive via is in a normal state, heat energy is transferred to the reaction material, so that The reaction material is heated to produce a proper change, so as to know whether the conductive perforation is defective (open circuit or cavity), so the method for detecting the conductive perforation of the present invention does not require the use of a conventional spring pin guiding method, and thus is fabricated. Before the line is re-wired, the yield of the conductive perforation can be detected to avoid wasting the material and time for fabricating the re-wiring structure, thereby effectively reducing the manufacturing cost.

1‧‧‧Detection device

10‧‧‧ Pedestal

100‧‧‧ lines

101‧‧‧Electrical bumps

11‧‧‧Upper cover

110‧‧ ‧ spring needle

2‧‧‧Reagents

20, 20’ ‧ ‧ Change Department

21‧‧‧Laser light

22‧‧‧ Observatory

3‧‧‧Semiconductor substrate

3a‧‧‧ first surface

3b‧‧‧ second surface

30,30’,30”‧‧‧Electrical perforation

30a‧‧‧ first end face

30b‧‧‧second end face

6‧‧‧Device under test

7‧‧‧矽Intermediary board

70a, 70b‧‧‧Electrical contacts

71‧‧‧ Conductive boring

72‧‧‧Line redistribution structure

8‧‧‧Semiconductor wafer

9‧‧‧Package substrate

w, s‧‧‧ volume (or area)

1A is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1B is a cross-sectional view showing a conventional method for detecting an interposer and a semiconductor wafer; and FIGS. 2 and 3 are a method for detecting a semiconductor substrate of the present invention; FIG. 4 is a schematic top view showing a method of detecting a semiconductor substrate of the present invention.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other aspects of the present invention from the disclosure herein. Advantages and effects.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2 and 3 are schematic cross-sectional views showing a method of detecting the semiconductor substrate 3 of the present invention.

As shown in FIGS. 2 and 3, a semiconductor substrate 3 having a first surface 3a and a second surface 3b opposite to each other is provided, and the semiconductor substrate 3 has a plurality of conductive vias 30 extending therethrough, that is, the conductive vias 30 communicate with the first a surface 3a and a second surface 3b, and the conductive via 30 defines an opposite first end surface 30a and a second end surface 30b. The first end surface 30a corresponds to the first surface 3a, and the second end surface 30b corresponds to the first surface 30a. Two surfaces 3b.

In the embodiment, the semiconductor substrate 3 is a germanium interposer, and the conductive via 30 is a conductive germanium via (TSV), and the semiconductor substrate 3 has not yet formed a line redistribution structure (RDL).

Next, the reaction material 2 is uniformly formed on the first surface 3a of the semiconductor substrate 3 and the first end surface 30a of the conductive via 30.

In the present embodiment, the reaction material 2 is made of a liquid crystal material, and the liquid crystal material is in a state of 29 ° C to 35 ° C. However, the state of the liquid crystal material may be selected according to its chemical composition or ratio, and is not limited to the above.

Thereafter, the second surface 3b of the semiconductor substrate 3 and the second end surface 30b of the conductive via 30 are heated, and the thermal energy received by the second end surface 30b of the conductive via 30 is conducted to the first end surface 30a, so that the conductive via 30 is The reaction material 2 on the first end face 30a is reacted by heat, that is, the heated portion of the reaction material 2 becomes the changing portion 20, and the machine (or human eye) from the observation portion 22 above the first surface 3a of the semiconductor substrate 3 A judgment is made in which the internal essence or appearance of the changing portion 20 is different from the internal essence or appearance of the unheated portion of the reactive material 2 for the machine (or human eye) to judge.

For example, if the conductive via 30' is in an open state, as shown in FIG. 2, the thermal energy received by the second end face 30b of the conductive via 30' cannot be conducted to the first end face 30a. The reaction material 2 on the first end face 30a of the open conductive via 30' does not form the change portion 20. Thereby, it can be judged whether or not the conductive perforation exhibits a bad state of disconnection.

Alternatively, if the conductive via 30" is in a defective state with a void or a metal unevenness, as shown in FIG. 3, the thermal energy received by the second end face 30b is transmitted to the thermal energy of the first end face 30a. The volume (or area) w of the varying portion 20' on the poor conductive via 30" is less than the volume (or area) s (w < s) of the varying portion 20 on the good conductive via 30. Thereby, it can be judged whether or not the conductive perforation has a void or a defective state in which the metal material is uneven.

In this embodiment, the second surface 3b of the semiconductor substrate 3 and the second end surface 30b of the conductive via 30 are irradiated with the laser light 21 as a heating mode. When the laser is irradiated to a certain position and locally heated, the object itself There will be changes, the heat will begin to pass. guide. Wherein, the energy of the laser light 21 can be controlled according to requirements, so that the resolution of the changing portion 20, 20' meets the requirements, so as to facilitate the judgment of the machine (or the human eye) of the observation point 22, the magnitude of the laser light energy can be utilized. The Pulse method enhances the contrast between normal and abnormal.

The invention adopts the heat conduction mode as the detection mode without using the conventional spring pin guiding method, so the detection of the conductive via 30 can be performed before the line redistribution structure (RDL) is fabricated. Therefore, before the circuit redistribution structure (RDL) is fabricated, whether the conductive via 30 is abnormal or not can be avoided, so that the manufacturing materials and production time of the circuit redistribution structure can be avoided, thereby effectively reducing the manufacturing cost.

Furthermore, since it is possible to effectively determine whether the conductive via 30 is normal, when an abnormality occurs in the wafer before the package, if an abnormality occurs, it is clear that the wafer is from the wafer, and thus only the wafer needs to be removed, without The entire semiconductor package is scrapped, and therefore, the manufacturing cost can be reduced.

As shown in FIG. 4, when detecting a plurality of the same semiconductor substrate 3, the coordinates of each of the conductive vias 30, 30', 30" may be marked, such as (A, a), so that each laser light is in the order of coordinates. For the test, such as (A, a), (A, b).. (A, j), to record the coordinates of the abnormal conductive perforations 30', 30'', and then count all the conductive perforations 30', 30" Whether it is the same coordinate. Thereby, the coordinate position of the abnormal conductive perforations 30', 30" can be analyzed more frequently to narrow the detection range or to facilitate maintenance of the machine for making conductive perforations.

In summary, the method for detecting a semiconductor substrate of the present invention mainly uses a thermal reaction of laser light and a liquid crystal material as a detection method to know whether the conductive via is defective, so that the line can be detected before the line redistribution structure is produced. The conductive perforation can avoid wasting the material and time for fabricating the rewiring structure of the circuit, thereby effectively reducing the manufacturing cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Reagents

20‧‧‧Change Department

21‧‧‧Laser light

22‧‧‧ Observatory

3‧‧‧Semiconductor substrate

3a‧‧‧ first surface

3b‧‧‧ second surface

30,30’‧‧‧Electrical perforation

30a‧‧‧ first end face

30b‧‧‧second end face

Claims (8)

A method for detecting a semiconductor substrate, comprising: providing a semiconductor substrate having a first surface and a second surface opposite to each other, wherein the semiconductor substrate has a plurality of conductive vias defined to correspond to the first and second surfaces a first end surface and a second end surface; forming a reaction material on the first end surface of the conductive via; and heating the second end surface of the conductive via to react the reaction material on the first end surface of the conductive via. The detection method according to claim 1, wherein the reaction material is a liquid crystal material. The detection method according to claim 2, wherein the liquid crystal material to be formed is in a state of 29 ° C to 35 ° C. The detection method of claim 1, wherein the reaction material is formed on the first surface of the semiconductor substrate. The detection method according to claim 1, wherein the heating method is a laser irradiation method. The detection method of claim 1, wherein the heating range includes a second surface of the semiconductor substrate. The detection method according to claim 1, wherein the reaction material is subjected to a heat generation reaction portion, and the internal essence or appearance of the change portion is different from the internal essence or appearance of the unheated portion of the reaction material. The detecting method according to claim 1, further comprising detecting a plurality of the same semiconductor substrates, and marking the coordinates of each of the conductive vias at the time of detection.