TWI485978B - Line driver with tuned on-chip termination - Google Patents

Description

Tuned on-chip terminal line driver

The present invention relates to a line (output) driver for an integrated circuit (IC), and more particularly to a line driver having an on-chip termination.

The line (output) driver circuit that provides the on-chip termination (ie, with its output impedance as the termination) is capable of delivering the same voltage swing with half the power when compared to a line driver using an external resistor termination. This power advantage is due to the fact that the on-chip termination line driver does not need to drive external termination resistors.

Figure 9 shows a basic conventional line driver circuit 30 that utilizes voltage and current feedback to produce a controlled termination resistor _ROUT . The line driver 30 is disclosed in U.S. Patent No. 5,121,080, the disclosure of which is incorporated herein by reference. Line driver 30 includes an amplifier 31 having an inverting input terminal coupled to ground (or a common mode voltage), a non-inverting input terminal coupled to a current driver 32, and an output terminal coupled to a node 34. The current driver 32 includes a digital-to-analog converter (DAC) that generates a current signal I _DAC derived from an input signal that is logic from one of the integrated circuits (not shown) incorporated into the line driver 30. Partially received. Node 34 is coupled to drive a gate terminal of a first P-channel transistor 36 and a second P-channel transistor 37. The source-drain path of the first P-channel transistor 36 is connected between the voltage source V _DD and an internal node 38, and the source-drain path of the P-channel transistor 37 is connected to the voltage source V _DD and an output. Between the nodes 39, an output voltage _VOUT is generated at the output node 39. Input node 38 is coupled to the non-inverting input terminal of amplifier 31 and to current driver 32, and a feedback resistor _{Rf is} coupled between nodes 38 and 39.

In operation, the line driver 30 based implementation of the data signal to a selected signal destination, the transmission line in FIG. 9 are connected by one via a transmission line 39 _L represents the load resistor R between the ground output node. The first transistor 36 forms a first stage of a current drive circuit, and generates a current I _{1 in} response to an output signal generated by the amplifier 31; and the transistor 37 forms a second stage which is a replica of the first stage ", since it was also drives an output signal from the amplifier 31, and generates a first stage of the current I ₁ is proportional to the current I _2. The ratio between the two currents I ₁ and I ₂ produced by the two driver stages corresponds to the aspect ratio between the transistors 36 and 37, which is set such that the first transistor 36 is given a value of 〝1 and a second The transistor 37 is given a value of N〞. The output impedance of amplifier 31 is a function of the current ratio between transistors 36 and 37 and the value of feedback resistor _Rf . This relationship provides a fixed ratio between current drive and output current. Essentially, the current drive is applied to the summing node using a replica of the first output stage, wherein the output impedance is dependent on the on-chip feedback resistor R _f such that adjustment of the feedback resistor R _f or 〝N 会 allows for adjustment of the output impedance , as shown in the following Equation 1: R _OUT = R _f / (1 + N) Equation 1 At the same time, the mutual impedance of the driver circuit 30 is expressed by the following Equation 2: V _OUT = I _DAC × (N × RL) / 2 Note that Equation 2 is true only when Rf=(1+N)×RL and Equation 1 is satisfied.

One problem with the line driver 30 is that the on-chip resistor _{Rf is subject} to process variations, and thus the output resistance _ROUT will vary from wafer to wafer. To avoid this problem, a mechanism for adjusting the output resistance R _OUT after production is required to make the output resistance R _OUT conform to the load resistance R _L . It can be seen from Equation 1 that in order to adapt the output resistance R _OUT , those skilled in the art will understand that the best way is to control (adjust) the value of R _f or N or both.

Figure 10 illustrates another conventional line driver 40 that achieves a uniform output resistance by adjusting the value of N in Equation 1 using a variable replica stage 47. The output driver circuit 40 is disclosed in U.S. Patent No. 7,119,611, issued Oct. 10, 2006, the entire disclosure of which is incorporated herein by reference. Similar to the aforementioned line driver 30, the line driver 40 includes an amplifier 41 having an inverting input terminal connected to the ground, a non-inverting input terminal connected to a current driver 42, and a connection for driving a first stage P. The output terminal of the gate terminal of the channel transistor 46. The source-drain path of the first P-channel transistor 46 is coupled to an internal node 48. The variable replica stage 47 includes a plurality of transistors that are programmably connected in parallel such that their source-drain paths are selectively coupled between the V _DD and the output node 49, the output node being in operation The middle is connected to the transmission line shown in FIG. 10 by a load resistor R _L . Internal node 48 is coupled to the non-inverting input terminal of amplifier 41 and is coupled to current driver 42 via a feedback resistor R _F , and a series resistor R _{S is} coupled between internal node 48 and output node 49. The current through the variable replica stage 47 is a function of the number of transistors connected in parallel, which is controlled by a value stored in a calibration register (not shown). This value is determined by an analog engine during a calibration operation which determines the value of the output impedance R _OUT as a function of the series resistance R _S and the ratio of the ratio of the transistor 46 to the parallel transistor in the variable replica stage 47. The ratio of the transistor 46 to the parallel transistor in the variable replica stage 47 is defined as assigning a 〝1〞 value to the transistor 46 and assigning a 〞N〞 value to the selected transistor in the variable replica stage 47, it being understood The value of 〝N〞 can be varied by selecting different combinations of transistors in the variable replica stage 47.

Although line driver 40 provides advantages over line driver 30 (see Figure 9), it presents some problems. First, the variable replica stage arrangement provides a transimpedance gain as defined in Equation 3: V _OUT = I _DAC × [(R _F + N × R _L )] / 2 Equation 3 at R _F >> N × R _L Under the conditions described, as described in U.S. Patent No. 7,119,611, V _OUT = I _DAC × R _F /2. Second, the current I generated by the transistor 46 must flow through the series resistor R _S , which not only forms a voltage divider but also causes V _DS (dip to source voltage) between the transistor 46 and the variable replica stage 47. A mismatch causes the line driver 40 to produce a nonlinear gain and a distortion of the matching ratio N.

The problems associated with the line driver 40 will be described with reference to Figures 11(A) and 11(B). Figure 11(A) is a simplified circuit showing portions of the line driver 40 and plotting the cause of the 1/2 gain problem. For a unit current I of the first-class over-transistor 46, there will be an N x I copy of the variable replica stage 47, such that the total current flowing through the load resistor RL is equal to (N + 1) x I. This current gives an equivalent resistor of (N+1) x R _L . Note that the series resistor RS is also equivalent to (N+1) x R _L and thus forms a voltage divider that divides the gain by two. Therefore, the output voltage V _OUT is half of the amplifier output, as shown in Figure 11(B) and Equation 4: V _OUT = 1/2 V _DAC = 1/2 I _DAC × R _F Equation 4

There is a need for an on-chip termination line driver that overcomes the gain issues associated with conventional line drivers and other problems.

The invention relates to a line driver with an on-chip terminal, which utilizes a bridge resistor The booster gain is increased twice as much as the conventional line driver, and an adjustable series resistor is used to facilitate adjusting the output resistance of the line driver in an efficient manner.

According to a first embodiment, an IC includes a line driver for generating a predetermined output voltage at an output node in response to a digital data signal. When implemented in a system, the output node is coupled to a transmission line having a known load resistance R _L (e.g., 75 ohms (ohms)). The line driver utilizes a current driver and an amplifier to generate an output control signal in response to the digital data signal. The output control signal is coupled to a gate terminal of a first stage transistor and a second stage transistor. The source-drain path of the first-level transistor is connected between a voltage source and an internal node, and the source-drain path of the second-stage transistor is connected between the voltage source and an output node The output voltage is generated at the output node. The first stage transistor returns an output control signal to generate a first current at the internal node, and the second stage transistor produces a second current proportional to the first current at the output node. The ratio between the two currents produced by the two driver stages corresponds to an aspect ratio between the first and second stage transistors, which is set by a known technique such that the first stage transistor is given a 〝1〞 The unit value and the second level transistor are given a value of 〝N〞 (for example, 10). The series resistor is coupled between the internal node and the output node, and a feedback resistor is coupled between the internal node and a non-inverting input terminal of the amplifier.

According to one aspect of the invention, a bridge resistor is coupled between the internal node and the common mode (ground) and is selected such that an internal voltage is generated at the internal node equal to a predetermined output generated at the output node The resistance value of the voltage whereby substantially no current flows between the output node and the internal node through the series resistor. In a particular embodiment, wherein the current through the feedback resistor is minimal, the resistance of the bridge resistor is substantially equal to the aspect ratio 〝N〞 multiplied by the load resistance R _L . In another embodiment, wherein the feedback resistance is non-negligible, the resistance value of the bridge resistor matches the total resistance value of the feedback resistor and the load resistor to produce a desired internal voltage node. By providing the bridge resistor, a bridge type circuit is generated such that the output voltage is the same as the internal node voltage generated by the first stage transistor (ie, no one-half of the conventional line driver is dropped), and the series connection The resistance of the resistor does not affect the output voltage, which allows the adjustment of the output resistor to be completely independent of the gain of the driver.

According to another aspect of the present invention, the series resistor is implemented by an adjustable resistor circuit including a plurality of parallel trimming units, the fine tuning units being independently adjustable (fine-tuned) by a control signal generated by a control circuit The output resistance of the driver conforms to the load resistance. In one embodiment, the series resistor has a resistance value substantially equal to (1+N)×R _L , where N represents an aspect ratio of the first and second stage transistors, and wherein R _L represents a load of the transmission line resistance. In another embodiment, an additional 〝 fixed 〞 series resistor is coupled to the output node, and the series resistor has a resistance value substantially equal to (1 + N) × (R _{L -} R _SL ), where R _SL represents the resistance value of the fixed tantalum series resistor. The purpose of adding the fixed series resistor is mainly to promote the function of echo cancellation, wherein if the output is a fully differential circuit, it will be completely cancelled at the receiving end.

In accordance with another embodiment, a system includes an integrated circuit having two associated line drivers for transmitting differential signals to associated transmission lines, and also includes echo cancellation coupled between respective output nodes of the line drivers Circuit. The echo cancellation circuit establishes a resistor divider between the output terminals of the line drivers using resistors proportional to the resistance values of the line drivers and transmission lines (but with an increase factor). The echo cancellation circuit provides an output voltage that is independent of the output signal produced at the output node of the line driver, thereby achieving echo cancellation.

30, 40, 102, 202, 202-1, 202-2‧‧‧ line drivers

31, 41, 120‧ ‧ amplifier

32, 42, 110‧‧‧ Current Drivers

34, 268‧‧‧ nodes

36, 46, 130‧‧‧ First P-channel transistor

37, 135‧‧‧Second P-channel transistor

38, 141‧‧‧ input nodes

39, 49, 145, 245, 245-1, 245-2, 247, 247-1, 247-2‧‧‧ output nodes

47‧‧‧Variable copying level

48, 143‧‧‧ internal nodes

100, 200, 200A‧‧‧ IC (integrated circuit)

122‧‧‧Output terminal

151‧‧‧Feedback resistor

153, 253‧‧‧ Bridge resistors

155, 255, 257‧‧‧ series resistors

260‧‧‧Tuner circuit

261, 262, 271‧‧‧ current source

265, 267, 272, 273, 302, 303, 304, 306, 307, 308, 401, 402‧‧‧ resistors

269‧‧‧ busbar

274, 275‧‧‧ node voltage

276, 277‧‧‧ comparator

300‧‧‧ system

301‧‧‧Echo cancellation circuit

305, 309‧‧ ‧ capacitor

310, 320‧‧‧ circuits

403, S1, S2‧‧ ‧ switch

404‧‧‧third resistor

405‧‧‧ openings

C _L ‧‧‧ load capacitance

CNTL‧‧‧ output control signal

CN1, CN2, C11, C12‧‧‧ control signals

V ₁₄₃ ‧‧‧ internal voltage

V _BG ‧‧‧Fixed Bandgap Voltage Reference

V _CM ‧‧‧ Common mode voltage

V _DD ‧‧‧voltage source

V _OUT, V _X, V _Y, V ₁ ‧‧‧ output voltage

R _A1 , R _A2 ‧‧‧ internal resistance

R _B , R _F , R _OUT , R _L N, R _TU1 -R _TUN, RT1‧‧‧ resistance value

R _EXT ‧‧‧External resistance

R _L ‧‧‧Load resistor

R _S, R _S', R _SL', R _SL ‧‧‧ series resistor

I‧‧‧current

Signal current I _DAC ‧‧‧

I _RS ‧‧‧net current

N1-N4‧‧‧ external nodes

TL, TL1, TL2‧‧‧ transmission line

M‧‧‧ increase factor

DN‧‧‧high pulse

UP‧‧‧ low pulse

The above and other features, aspects, and advantages of the present invention will become more apparent from the description and appended claims appended claims One embodiment includes an integrated circuit of an on-chip termination line driver; second (A) and (B) diagrams show a simplified circuit diagram of the first diagram driver; and FIG. 3 is a simplified circuit diagram showing one An adjustable series resistor of a first line driver in accordance with a particular embodiment of the present invention; and FIG. 4 is a simplified circuit diagram showing a trimming unit of an adjustable series resistor of FIG. 3 in accordance with a particular embodiment of the present invention Figure 5 is a simplified circuit diagram showing an on-chip termination line driver in accordance with another embodiment of the present invention; and Figure 6 is a simplified circuit diagram illustrating a full differential operation using two line drivers as shown in Figure 5; Circuit Figure 7 is a simplified circuit diagram showing a tuner circuit for tuning a series resistor of a 5th line driver in accordance with another embodiment of the present invention; Figs. 8(A) and 8(B) illustrate A circuit diagram for generating a circuit for a reference voltage used by the tuner circuit of FIG. 7; FIG. 9 is a simplified circuit diagram showing a conventional on-chip termination line driver; and FIG. 10 is a simplified circuit diagram showing another A conventional on-chip termination line driver; and 11(A) and 11(B) illustrate circuit diagrams of a simplified representation of the 10th line driver.

The present invention is directed to an improvement in an on-chip termination line driver. The following description is provided to enable a person skilled in the art to make and use the present invention as the subject matter of the present invention. In this specification, the terms "〝" and "〝" are defined as follows. The term "connection" is used to describe a direct connection between two circuit elements, such as via a wire connection formed in accordance with conventional integrated circuit fabrication techniques. Conversely, a 〝 coupling is used to describe a direct or indirect connection between two circuit elements. For example, the two coupling elements can be directly connected via a metal wire or via an intermediate circuit component (such as a capacitor, resistor, inductor, or via a source/汲 terminal of a transistor) Indirect connection. Various modifications of the preferred embodiment will occur to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments disclosed herein.

1 shows a simplified IC 100 comprising a general purpose logic circuit 101 for generating a digital signal DATA, and a line for generating a predetermined output voltage V _OUT at an output node 145 in response to the digital signal DATA. (Output) the drive 102. When implemented in a system, the output node 145 is coupled to a transmission line TL having a load resistor R _L , which is known in the present case (e.g., a 75 ohm (ohm) cable). The IC 100, including both the logic circuit 101 and the line driver 102, is formed on a semiconductor (e.g., single crystal germanium) wafer using an established semiconductor fabrication technique. Conversely, the transmission line TL is formed independently of the IC 100 and is connected to one of the external pins or pads of the IC 100, for example via a soldered connection.

Similar to the conventional line driver, the line driver 102 utilizes a current driver 110 and an amplifier 120 to generate an output control signal CNTL in response to the digital signal DATA. Current driver 110 includes a digital-to-analog converter (DAC) that receives a digital signal DATA from logic portion 101 of IC 100 and produces a current signal I _DAC at an input node 141. The amplifier 120 has an inverting input terminal connected to a common mode voltage V _CM (or ground), a non-inverting input terminal connected to the current driver 110 via an input node 141, and an output terminal 122. By this arrangement, the amplifier 120 generates an output control signal CNTL on the output terminal 122 in response to a digital data signal DATA. The output control signal CNTL is coupled to drive a gate terminal of a first P-channel transistor 130 and a second P-channel transistor 135. The source-drain path of the first P-channel transistor 130 is connected between the voltage source V _DD and an internal node 143, and the source-drain path of the second P-channel transistor 135 is connected to the voltage source V _DD and Between an output node 145, an output voltage _VOUT is generated at the output node. Input node 141 is coupled to internal node 143 via a feedback resistor R _F . The first transistor 130 forms a first stage of a current driving circuit, and generates a current I at the internal node 143 in response to the output control signal CNTL; and the second transistor 135 forms a second stage which is the first stage of the first stage. The replica is because it is also driven by the output control signal CNTL and produces a current NI (N times unit current I) proportional to the current I of the first stage at the output node 145. The ratio between the two currents I and NI produced by the two driver stages is equivalent to an aspect ratio between the transistors 130 and 135, which is set by a known technique such that the first transistor 130 is given a value of 〝1〞 and The second transistor 135 is given a value of 〝N〞. A series resistor 155 is coupled between the internal node 143 and the output node 145.

In accordance with one aspect of the present invention, a resistive path, represented by bridge resistor 153, is applied between internal node 143 and common mode (ground) and provides a decision to have an internal voltage V143 at internal node 143 substantially equal to the output. The resistance value R _B of the output voltage V _OUT generated at node 145 is such that substantially no current flows between the output node 145 and the internal node 143 through the series resistor 155. In this context, 〝 is substantially equal to 〞 and 〝. There is substantially no lanthanide used to express the resistance value. R _B is set to produce a zero voltage drop across the series resistor 155. However, for example, slight variations due to process mismatch may result in resistance R. _B is not exactly equal to N x R _L , resulting in a small current (e.g., equal to 5% or less of the current I _DAC generated by current source 110). Note that without the bridge resistor 153, almost all of the I _DAC current flows through the series resistor 155, which creates a large voltage difference between the internal node 143 and the output node 145. Since the in-line driver 102 includes a bridge resistor 153 having a resistance value that balances the voltages at the nodes 143 and 145, even if there is a defect due to process variations, only a small portion of the I _DAC current flows through the series resistor 155. And its effect can be ignored.

The primary benefit achieved by the addition of the bridge resistor 153 to the line driver 102 is to increase the transimpedance gain of the line driver 102 by a factor of two that is better than the conventional line driver 40 (described above with reference to FIG. 10). In contrast, U.S. Patent No. 7,119,611 conventional line driver (refer to section has 11 (A) and 11 (B) described in FIG.) To make the most of the current construction of system must flow through the resistor R _S, which not only forms a voltage divider The device also causes a mismatch in V _DS between transistors 45 and 47 (see Figure 10), which causes non-linear operation. As previously mentioned, in the linear driver 40, the resistor RS is a function of the output gain because when the resistor R _S is properly tuned, its resistance is equal to (1 + N) × R _L , which is 1/2 Gain value. Returning to the line driver 102 (Fig. 1), since the resistance R _{B of} the bridge resistor 153 is set such that substantially no current flows through the series resistor 155, the resistance R _{S of the} series resistor 155 is not part of the output voltage V _OUT ( That is, the output voltage V _OUT is independent of the resistance R _{S of the} series resistor 155, which allows the output resistor R _{OUT to} be adjusted via the series resistor 155 in a completely independent gain manner.

In an embodiment (i.e., where the resistance R _{F of the} feedback resistor 151 is substantially greater than the resistance of the bridge resistor 153), the bridge resistor 153 is fabricated to include a resistor that is substantially equal to 〝N〞 times the expected load resistance RL. (ie a R _L N resistance value). For example, when the line driver 102 is fabricated such that the aspect ratio between the transistor 135 and the transistor 130 is equal to 10, and is fabricated when the output node 145 is connected to a transmission line having a resistance value R _L equal to 75 Ω, A predetermined output voltage V _OUT is generated at the output node 145, and then the bridge resistor 153 is fabricated to have a resistance value R _L N substantially equal to 750 Ω.

2(A) and 2(B) are simplified representations of the line driver 101 when the resistance of the bridge resistor 153 is equal to R _L N . As shown in Fig. 2(A), similar to the conventional circuit, when a unit current I flows through the transistor 130, a current N x I flows through the transistor 135. The difference between the output driver 101 and the conventional driver 40 (Fig. 10) is that the current I through the transistor 130 all flows through the bridge resistor 153, which induces a voltage drop I x R _L N at the internal node 143. Similarly, current NI through transistor 135 all flows into load resistor R _L , which induces an output voltage V _OUT equal to NI x R _L at output node 145. Internal node 143 is the same as the voltage of the output node 145, there will be no voltage drop across the resistor 155, and no net current I _RS through a series resistor 155. Therefore, a bridge type circuit is formed, and the output voltage V _OUT is the same as the output voltage of the transistor 135, and there is no one-half drop in the conventional line driver 40. That is to say, the series resistance R _S is independent of the output voltage, which makes the adjustment of the output resistance ROUT completely independent of the gain. Therefore, as shown in FIG. 2(B), the series resistor 155 can be set equal to the load resistance value R _L multiplied by (1+N), which optimizes the output impedance R _OUT .

The above embodiment in which the bridge resistor 153 has a resistance value R _L N assumes that the resistance R _{F of the} feedback resistor 151 is much larger than the resistance value R _L N . Referring to Fig. 1, the current flowing through the feedback resistor R _F in this example is negligible compared to the current through the bridge resistor 153. However, if the resistance RF is small such that the current through the feedback resistor 151 becomes large, the resistance value of the bridge resistor 153 must be increased (i.e., greater than RLN) in order to maintain the purpose of minimizing the current through the series resistor 155. That is, in accordance with an alternate embodiment of the present invention, the feedback resistor 151 and the resistance of the bridge resistor 153 are matched to form a constant at the internal node 143 that is equal to the output voltage V _OUT (i.e., equal to I x R _L N). The bridge circuit of voltage V ₁₄₃ .

In accordance with another aspect of the present invention, series resistor 155 is implemented using a trimmable resistor circuit coupled between internal node 143 and output node 145 and controlled by a tuner (control) circuit 160, the tuner is integrated It is fabricated on the IC 100 and generates control signals CN1, CN2 that are transmitted to the series resistor 155, whereby the series resistance R _{S is} adjustable such that the output impedance R _{OUT of the} line driver 102 is set to conform to an applied load impedance. For example, in the embodiment shown in FIG. 1, the series resistance R _S is adjusted to be equal to (1+N)×R _L , whereby the output impedance R _{OUT of the} line driver 102 is set to match the load impedance of the transmission line TL. R _L . In other embodiments described below, the series resistance R _S can be set to another value.

3 is a simplified circuit diagram showing a series resistor 155 in accordance with a particular embodiment of the present invention. The series resistor 155 includes parallel trimming units 310-1 to 310-N, wherein each trimming unit 310-1 to 310-N provides an associated adjustable (trimmable) resistor R _TU1 to R _TUN , respectively, and is connected by a parallel trimming unit The total resistance provided by 310-1 to 310-N produces a series resistance R _S .

4 is a circuit diagram showing an example trimming unit 310-1, which includes a first resistor 401 and a second resistor 402, each having a resistor RT1, a first switch 403 and first and second The two resistors 401 and 402 are connected in series, and a third resistor 404 and a second opening 405 are connected in parallel with the first switch 403. Note that the switches S1 and S2 in each of the units 310-1 to 310-N are implemented with CMOS transmission gates. Control signals C11 and C12 are transmitted to unit resistance trimming unit 310-1 to selectively control switches S1 and S2, thereby providing fine control such that the sum equivalent resistance R _S between internal node 143 and output node 145 is in series desired One of the resistance values R _S is within a predetermined range. In the particular embodiment illustrated in FIG. 3, each of the parallel trimming units 310-1 through 310-N has a predetermined predetermined equivalent resistance (R _S × M) equal to being connected in series by resistors 401, 402, and 404. The total resistance provided by the combination (i.e., preset switch 405 is closed and switch 404 is open). When the control signals C11 and C12 are respectively responded such that the switch 403 (S1) is closed and the switch 405 (S2) is open, the resistance of the unit 310-1 is reduced to the sum of the resistors 401 and 402. When both switch 403 (S1) and switch 405 (S2) are open, unit 310-1 is open and has a high impedance. Various equivalent resistances can be achieved by selectively turning on/off the switches S1 and S2 of each of the units 310-1 to 310-N. For example, the preset equivalent resistance may be R _S ×M/N, wherein each of the N parallel units 310-1 to 310-N has a predetermined resistance RS×M. By turning on the switch S2 of K cells (e.g., cells 310-1 to 310-K, where K < N), and switch S1 is preset to be an open circuit, the equivalent resistance of series resistor 155 becomes R _S × M / ( NK), if M/(NK)>1, the equivalent resistance is greater than RS, and if M/(NK)<1, the equivalent resistance is less than R _S . Switching on the switch S1 in the additional trim unit provides a finer resolution for controlling the resistance R _S . In one embodiment, tuner circuit 160 (Fig. 1) includes a logic circuit that generates a preselected sequence of one of control signals CN1, CN2 such that switches S1 and S2 in each of units 310-1 through 310-N Turn on/off until the desired resistance R _{S is} reached. Note that the switches S1 and S2 in each of the units 310-1 to 310-N are implemented with CMOS transmission gates.

Figure 5 is a simplified circuit diagram showing an IC 200 incorporating a line driver 202 in accordance with a second embodiment of the present invention. Line driver 202 operates in a manner similar to line driver 102 (see FIG. 1), and elements that are substantially common in the two circuits (eg, current source 110, amplifier 120, transistors 130 and 135, and feedback resistor 153) are The same reference numerals are used and are not described in detail below for the sake of brevity. Similar to line driver 102, line driver 202 includes a bridge resistor 253 and a series (adjustable) resistor 255. However, unlike the line driver 102, the line driver 202 includes an additional series resistor 257 coupled between a first output node 245 and a second output node 247, the second output node being coupled to the associated transmission line (with load resistance) R _L stands for). Since the second series resistor 257 is added, the output resistance R _OUT is determined as shown in the following Equation 4: R _OUT = R _SL + R _S / (1 + N) Further, the addition of the series resistor 257 forms a partial pressure , which changes the output voltage V _OUT to the following equation 5: V _OUT =I _DAC ×R _F ×R _L /(R _SL +R _L ) Equation 5 is to achieve correct termination and balance, predetermined digital N, load resistance The value R _L , the bridge resistance value R _B and the series resistance value R _SL are matched such that the bridge value R _B is equal to the ratio N multiplied by the sum of the load resistance value R _L and the series resistance value R _SL as shown in the following Equation 6: R _B = (R _SL +R _L )×N The purpose of adding series resistor 257 is mainly to facilitate the echo cancellation function, which makes the output a full differential circuit (for example, as described below with reference to Figure 6). It is completely offset at the receiving end.

Figure 6 shows a system 300 forming an embodiment of a fully differential circuit in which the echo cancellation function of line driver 202 (Fig. 5) is implemented. The system 300 includes an integrated circuit 200A including a first line driver 202-1 and a second line driver 202-2 connected to the transmission lines TL1 and TL2, respectively, and a first and second line connected An echo cancellation circuit 301 between respective output nodes of drivers 202-1 and 202-2. Note that the associated transmission lines TL1 and TL2 are represented by respective load resistors R _L1 and R _L2 and form a load capacitance CL. In this configuration, two identical output drivers 202-1 and 202-2 are utilized (i.e., each driver 202-1 and 202-2 is identical to line driver 200 of Figure 5) at output node 245, respectively. 1 and 245-2 are supplied with amplifier output voltages V _X , -V _X and a fully differential output signal at output nodes 247-1 and 247-2 at load output voltages V _Y , -V _Y , respectively. An echo cancellation resistor network (circuit) 301 establishes a resistor divider between V _X and -V _Y . In the disclosed embodiment, the echo cancellation circuit 301 includes a first resistor 302 connected between the (first) output node 245-1 and a first external node N1, and a connection to the (second) output node. a second resistor 303 between 247-1 and a second external node N2, a third resistor 304 connected between the second external node N2 and a third external node N3, and a connection (second) a first capacitor 305 between the output node 247-1 and the third external node N3, a fourth resistor 306 connected between the (third) output node 245-2 and the third external node N3, and a connection a fourth resistor 307 between the output node 247-2 and a fourth external node N4, a sixth resistor 308 connected between the fourth external node N4 and the first external node N1, and a connection (Fourth) A second capacitor 309 between the output node 247-2 and the first external node N1. The resistance values of resistors 301-304 and 306-308 are indicated next to each resistor and are proportional to the resistance values R _SL and R _{L of} line drivers 202-1 and 202-2 (described above), but have one Increase the coefficient M (where M is approximately equal to 100). If there is a fully differential signal, the output voltage V ₁ can be independent of the voltage V _X . Similarly, the V ₂ system is independent of V _X and therefore echo cancellation is achieved at the input V _IN . The same increase factor can be applied to the load capacitance _CL to achieve large bandwidth cancellation (i.e., capacitors 305 and 309 have the values shown in Figure 6).

For good matching, the terminal R _OUT must be equal to R _L in all process ranges, which means that a tuner is needed to adjust the series resistance R _S to achieve the balance shown in Equation 7 below: R _SL +R _S /(1+ N)=R _L Equation 7 means that the resistance of the series resistor 255 is equal to the load resistance minus the second series resistor R _SL , and the sum is multiplied by a plus aspect ratio N, as shown in the following Equation 8: R _S =( R _L -R _SL )×(1+N) Equation 8 can be rewritten as Equations 8-1 and 8-2 as follows: R _S +R _SL ×(1+N)=R _L ×(1+N) Equation 8-1

[R _S /(1+N)]+R _SL =R _L Equation 8-2 Since the load resistance R _L is supplied by an external resistor having a resistance value independent of the process and temperature, and the R _SL is internally connected in series Resistor 257 provides, the latter is dependent on the process and temperature, so a tuner circuit is required not only to adjust the expected value of series resistance R _S , but also to compensate internal resistance (ie R _S and R _SL ) and external resistance (also That is, the characteristic difference between R _L ) (such as temperature effect). Equations 8-1 and 8-2 show that variations in all such as N and R _SL can be compensated by tuning the R _S value.

Figure 7 shows a simplified circuit diagram for tuning the series resistor 255 to perform the tuner circuit 260 of Equation 7. In this circuit, the resistor R _EXT represents an external resistor (shown in Figure 8(A)) with the same characteristics as the load resistor R _L (such as the temperature effect), and all remaining resistors are internal resistors (also That is, the resistor formed on the substrate for fabricating the IC 200, see Fig. 5) is applied. As shown in Fig. 8(A), current sources 261 and 262 are controlled by a signal generating circuit 310 which uses a fixed bandgap voltage reference V _BG and an external resistor R _EXT , together with an aspect ratio as shown. A P-channel transistor of 1 〞 and 〝N〞, where N is the same aspect ratio value associated with transistors 130 and 135 (see Figure 5). Therefore, the current generated by current source 261 is N times the current produced by current source 262. Resistors 265 and 267 have R _{S '} and R _{SL '} which are replicated versions of resistors 255 and 257 having a proportional ratio. The voltage at node 268 is therefore V _BG /R _EXT ×(R _S' +(1+N)×R _SL' ). The other current source 271 is controlled by a signal generating circuit 320 shown in Fig. 8(B), wherein the signal is generated by dividing the bandgap voltage reference V _BG by an internal resistance R _A1 by a factor (1 + N). As shown in Figure 7, this current flows to internal resistors ΔR (resistor 272) and R _A2 (resistor 273), producing node voltages 274 and 275. The node voltage 275 across the resistor 273 is V _BG /R _A1 ×(1+N)×R _A2 . Resistor 272 (resistance ΔR) is designed to be a relatively small value, so node voltages 274 and 275 are very similar, with node voltage 274 being slightly higher. A control signal is generated on bus bar 269 using two comparators 276 and 277 and a look-up table 279 that is used to tune series resistor 255 (Fig. 5) and replica series resistor 265. Comparator 276 is set such that if node voltage 268 is above node voltage 274, a high pulse 〝DN〞 (down) is output to lookup table 279. Conversely, comparator 277 is set such that if node voltage 268 is lower than node voltage 274, a low pulse 〝UP〞 is output to lookup table 279. The DN and UP signals cause the lookup control table 279 to adjust the resistance of the replica series resistor 265 (resistance R _{S '} ) to increase or decrease the voltage on node 268. A negative feedback loop is achieved throughout the operation such that node voltage 268 is maintained between node voltages 274 and 275. After eliminating the V _BG term on either side of resistor 265, the net result of this loop produces a function R _S' /(1+N)+R _SL' =β×R _EXT , where β is a resistor R _A2 / The constant set by R _A1 . The tuner circuit 260 achieves replica control satisfying the above Equation 8 by appropriately selecting the scaling factor and setting the β value such that β × R _EXT = (1 + N) × R _L ; that is, the output of the lookup table 279 causes the series resistor The 255 (Fig. 5) is tuned to the desired value. In one embodiment, lookup table 279 contains a series of preselected control signal combinations that adjust the resistance of RS' with appropriate resolution. The loop does not require a calibration cycle and does not require a clock signal, so the tuner circuit 260 can remain fully on (active) to make adjustments for temperature and environmental changes. Alternatively, by adding another 2 x (M+K) lockout circuit (not shown in Figure 7), the selection can be locked and the tuner can reduce power.

Although the present invention has been described with reference to the specific embodiments thereof, it will be apparent to those skilled in the art that the present invention may be applied to other embodiments, which are all within the scope of the present invention.

100‧‧‧IC (integrated circuit)

102‧‧‧Line driver

110‧‧‧current drive

120‧‧‧Amplifier

122‧‧‧Output terminal

130‧‧‧First P-channel transistor

135‧‧‧Second P-channel transistor

141‧‧‧ input node

143‧‧‧ internal nodes

145‧‧‧ Output node

151‧‧‧Feedback resistor

153‧‧‧Bridge resistors

155‧‧‧ series resistor

CNTL‧‧‧ output control signal

CN1, CN2‧‧‧ control signals

V143‧‧‧ internal voltage

VCM‧‧‧ Common mode voltage

VDD‧‧‧voltage source

VOUT‧‧‧ output voltage

IDAC‧‧‧ current signal

IRS‧‧‧ net current

RB, RF, ROUT‧‧‧ resistance values

RL‧‧‧ load resistor

RS‧‧‧ series resistor

TL‧‧‧ transmission line

N1‧‧‧ external nodes

Claims (10)

A line driver for generating a predetermined output voltage at an output node of an integrated circuit when an output node is connected to a transmission line having a first resistance value, the line driver comprising: for generating an output control a means for responding to a digital data signal; a first stage transistor for generating a first current at an internal node to output a control signal; and a second stage transistor for outputting the output node Generating a second current to output a control signal, wherein the second stage transistor is constructed such that the second current is greater than the first current by a predetermined multiple; a bridge resistor coupled to the internal node and a common mode voltage a first trimmable resistor circuit coupled between the internal node and the output node; and a control circuit for controlling the first fine-tunable between the internal node and the output node by controlling a series voltage of the resistor circuit to adjust a total output resistance value of the line driver, wherein the control circuit includes: a second trimmable resistor circuit for scheduling Generating a replica series voltage; and comparing the replica series voltage and a first and second node voltages, and for generating one or more control signals until the replica series voltage is at the first and second node voltages An apparatus between the one or more control signals simultaneously transmitted to both the first trimmable resistor circuit and the second trimmable resistor circuit, and wherein the first and second node voltages are generated such that When the series voltage is replicated between the first and second node voltages, the series voltage across the first trimmable resistor circuit is adjusted such that the total output resistance value is equal to the first resistance value of the transmission line. The line driver of claim 1, wherein the first trimmable resistance circuit comprises a plurality of parallel trimming units, wherein a unit resistance value of each of the plurality of parallel trimming units is adjustable such that Multiple parallel trimming A total equivalent resistance of the unit is equal to a predetermined resistance value. The line driver of claim 1, wherein the first trimmable resistance circuit has a resistance value substantially equal to (1+N)×R _L , wherein N represents the predetermined multiple, and wherein R _L represents The first resistance value of the transmission line. The line driver of claim 1, further comprising a first series resistor connected to the output node such that the first series resistor is connected between the output node and the transmission line, wherein the first series resistor The device has a third resistance value, and wherein the first trimmable resistance circuit has a resistance value substantially equal to (1+N)×(R _L −R _SL ), wherein N represents the predetermined multiple, wherein R _L represents the The first resistance value of the transmission line, and wherein R _SL represents the third resistance value of the second series resistor. The line driver of claim 4, wherein the second trimmable resistor circuit is connected in series with a second series resistor having a replica series resistor, the replica series resistor and the first series resistor The three resistance values are proportional. The line driver of claim 4, wherein the means for comparing and generating comprises: a first comparator for comparing the replica series voltage with the first node voltage, a second comparator Means for comparing the replica series voltage with the second node voltage, and a lookup table for storing a series of multiple preselected control signal combinations and for transmitting one of the plurality of preselected control signal combinations to the The first and second trimmable resistor circuits are responsive to the plurality of output signals generated by the first and second comparators. The line driver of claim 1, wherein the bridge resistor has a second resistance value group such that an internal voltage at the internal node is equal to the predetermined output voltage generated at the output node, thereby A substantially zero current flows between the output node and the internal node through the first series resistance circuit. A line driver for connecting an output node to have a first resistance value a transmission line, a predetermined output voltage is generated at the output node of the integrated circuit, the line driver comprising: means for generating an output control signal in response to a digital data signal; a first stage transistor for Generating a first current at an internal node to output a control signal; a second stage transistor for generating a second current at the output node to output a control signal, wherein the second stage transistor Constructed such that the second current is greater than the first current by a predetermined multiple; a bridge resistor is coupled between the internal node and a common mode voltage; a first trimmable resistor circuit coupled to the internal node and the output Between the nodes; a first series resistor connected to the output node such that the first series resistor is coupled between the output node and the transmission line; and a control circuit for controlling at the internal node Adjusting a total output resistance value of the line driver by a series voltage across the first trimmable resistor circuit between the output nodes, wherein the control circuit comprises: a second trimmable resistor circuit for generating a replica series voltage at a predetermined node; and for comparing the replica series voltage and a first and second node voltage, and for generating one or more control signals until the Means for replicating a series voltage between the first and second node voltages, wherein the one or more control signals are simultaneously transmitted to both the first trimmable resistor circuit and the second trimmable resistor circuit, and wherein The first and second node voltages are generated such that when the replica series voltage is between the first and second node voltages, the series voltage across the first trimmable resistor circuit is adjusted such that the total output resistance value is equal to The first resistance value of the transmission line. The line driver of claim 8, wherein the means for comparing and generating comprises: a first comparator for comparing the replica series voltage with the first node a second comparator for comparing the replica series voltage with the second node voltage, and a lookup table for storing a series of the plurality of preselected control signal combinations for transmitting the plurality of preselected control signals One of the plurality of trimming resistor circuits is combined to the first and second trimmable resistor circuits in response to the plurality of output signals generated by the first and second comparators. A line driver for generating a predetermined output voltage at an output node of an integrated circuit when an output node is connected to a transmission line having a first resistance value, the line driver comprising: for generating an output control a means for responding to a digital data signal; a first stage transistor for generating a first current at an internal node to output a control signal; and a second stage transistor for outputting the output node Generating a second current to output a control signal, wherein the second stage transistor is constructed such that the second current is greater than the first current by a predetermined multiple; a bridge resistor coupled to the internal node and a common mode voltage a first trimmable resistor circuit coupled between the internal node and the output node; a first series resistor coupled to the output node such that the first series resistor is coupled to the output node Between the transmission lines; and a control circuit for controlling a series voltage across the first trimmable resistor circuit between the internal node and the output node Adjusting a total output resistance value of the line driver, wherein the control circuit comprises: a second trimmable resistor circuit for generating a replica series voltage at a predetermined node; and a first comparator for comparing the replica a series voltage and a first node voltage; a second comparator for comparing the replica series voltage with a second node voltage, and a lookup table for storing a series of a plurality of preselected control signal combinations and for transmitting one of the plurality of preselected control signal combinations to the first and second trimmable resistor circuits in response to the first a plurality of output signals generated by the second comparator, wherein the one or more control signals are simultaneously transmitted to both the first trimmable resistor circuit and the second trimmable resistor circuit, and wherein the first and second a node voltage is generated and the first and second comparators are arranged such that the series voltage across the first trimmable resistor circuit is adjusted when the replica series voltage is between the first and second node voltages The total output resistance value is made equal to the first resistance value of the transmission line.