TWI483098B - Computer system and power sharing method thereof - Google Patents

Description

Computer system and its power sharing method

The present invention relates to a power sharing method, and more particularly to a power sharing method for a computer system and a computer system using the same.

In the computer system architecture, the operating frequency of a processor such as a central processing unit (CPU) and a graphics processing unit (GPU) has a great influence on system performance. Processor overclocking technology allows the central processing unit or graphics processor to overclock in a certain period of time to provide the maximum overclocking range that the processor chip can withstand, thereby improving the performance of the computer system.

However, increasing the operating frequency has caused more and more thermal energy from the computer system during operation. Taking a notebook computer as an example, because the heat dissipation space of the casing is limited, it is very difficult to control the system temperature while using the overclocking technology to improve the system performance. In order to ensure that important components can work properly without burning due to high temperatures, most computer systems have temperature monitoring mechanisms to ensure that the system temperature does not increase after rising to ambient temperature. However, according to the test and usage results, when the temperature of the computer system reaches the average temperature, the performance of the computer system is greatly reduced due to the temperature control. In other words, the current temperature monitoring mechanism is more difficult to balance the temperature and performance of the computer system, and it is easy to have a negative impact on the operating experience.

In view of this, the present invention provides a computer system and a power sharing method thereof, which are difficult to improve the performance of a computer system after it has risen to a uniform temperature.

The present invention provides a power sharing method for a computer system including a first processor and a second processor, the method comprising the steps of: receiving a first pulse width modulation signal, the first pulse width modulation signal having a duty cycle . The system heat dissipation power is defined as the sum of the first preset temperature design power (TDP) of the first processor and the second processor. Determine whether the system cooling power is greater than or equal to the preset upper limit. If yes, adjusting the power of the first processor and the second processor by using the first pulse width modulation signal, wherein increasing the power of the first processor by using the boost and increasing the power of the second processor by using the boosting Do not overlap each other. Determine if the system temperature of the computer system is rising. If so, reduce the duty cycle or system cooling power to reduce the time to use boost to increase power. If not, increase the duty cycle or system cooling power to increase the time to use boost to increase power. The method repeatedly determines whether the system heat dissipation power is greater than or equal to a preset upper limit value, adjusts the power of the first and second processors by using the first pulse width modulation signal, and increases or decreases the duty cycle or the system heat dissipation power according to the system temperature. Until the system cooling power is less than the preset upper limit.

In one embodiment of the invention, the step of reducing the duty cycle or system heat dissipation power to reduce the time to increase power with boosting includes determining whether the duty cycle has reached a lower cycle limit. If not, reduce the duty cycle. If yes, reduce the system cooling power.

In an embodiment of the invention, the step of increasing the duty cycle or system heat dissipation power to increase the time to utilize boost to increase power includes determining whether the duty cycle has reached the upper cycle limit. If not, increase the duty cycle. If yes, increase the system cooling power.

In an embodiment of the present invention, wherein the power sharing method is further included between adjusting the power of the first processor and the second processor by using the first pulse width modulation signal and determining whether the system temperature of the computer system is rising. When the usage rate of the first processor needs to be determined, the current usage power of the first processor is obtained, and the first processor is determined to be in a high usage state or a low usage rate according to the current usage power and temperature design power of the first processor. status. If the first processor is in the low usage state, the temperature design power of the first processor is lowered, and the temperature design power of the second processor is set as the difference between the system cooling power and the current temperature design power of the first processor. . If the first processor is in the high usage state, increasing the temperature design power of the first processor, and setting the temperature design power of the second processor to a difference between the system cooling power and the current temperature design power of the first processor .

In an embodiment of the invention, the step of adjusting the power of the first processor and the second processor by using the first pulse width modulation signal comprises increasing the first pulse width modulation signal when the first logic level is at the first logic level The voltage increases the power of the first processor and boosts the power of the second processor with the boost when the first pulse width modulation signal is at the second logic level.

In an embodiment of the invention, the step of adjusting the power of the first processor and the second processor by using the first pulse width modulation signal comprises providing a second pulse width modulation signal, the second pulse width modulation signal First pulse width modulation signal Mutual inversion. Raising the power of the first processor with the boost when the first pulse width modulation signal is at the first logic level, and boosting the second processor with the boost when the second pulse width modulation signal is at the first logic level Power.

From another point of view, the present invention provides a computer system including a first processor, a second processor, a chipset, a temperature sensor, and a controller. The chipset is coupled to the first processor and the second processor. A temperature sensor is used to sense the system temperature of the computer system. The controller is coupled to the chip set and the temperature sensor. The controller receives the first pulse width modulation signal, the first pulse width modulation signal has a duty cycle, and defines the system heat dissipation power as a sum of the temperature preset design powers preset by the first processor and the second processor. The controller adjusts the power of the first processor and the second processor by using the first pulse width modulation signal when determining that the system heat dissipation power is greater than or equal to the preset upper limit value, wherein boosting the power of the first processor by using the boosting The time does not overlap with the time of boosting the power of the second processor by using the boost, and determines whether the system temperature of the computer system rises, and reduces the duty cycle or the system heat dissipation power when determining the temperature rise of the system to shorten the use of the boost to increase the power. Time, and increase the duty cycle or system cooling power when determining the system temperature drops to increase the time to boost power with boost. The controller repeats the foregoing operation until the system heat dissipation power is less than the preset upper limit value.

In an embodiment of the present invention, if the controller determines that the duty cycle does not reach the lower limit of the cycle, the duty cycle is reduced to shorten the time for boosting the power by using the boost, and if the controller determines that the duty cycle reaches the lower limit of the cycle, the system is reduced. Heat dissipation power to reduce the time to increase power with boost.

In an embodiment of the invention, wherein the controller determines the duty cycle If the upper limit of the cycle is not reached, the duty cycle is increased to increase the time to increase the power by using the boost, and if the controller determines that the duty cycle reaches the upper limit of the cycle, the system heat dissipation power is increased to increase the time for boosting the power.

In an embodiment of the present invention, wherein the controller adjusts the power of the first processor and the second processor by using the first pulse width modulation signal and determines whether the system temperature of the computer system rises, and further includes determining The usage rate of the first processor obtains the current usage power of the first processor, and determines whether the first processor is in a high usage state or a low usage state according to the current usage power and temperature design power of the first processor. If the first processor is in the low usage state, the temperature design power of the first processor is lowered, and the temperature design power of the second processor is set as the difference between the system cooling power and the current temperature design power of the first processor. . If the first processor is in the high usage state, increasing the temperature design power of the first processor, and setting the temperature design power of the second processor to a difference between the system cooling power and the current temperature design power of the first processor .

In an embodiment of the invention, the controller increases the power of the first processor by boosting when the first pulse width modulation signal is at the first logic level, and is at the second of the first pulse width modulation signal. The logic level increases the power of the second processor with a boost.

In an embodiment of the invention, the controller receives the second pulse width modulation signal, and the second pulse width modulation signal and the first pulse width modulation signal are mutually inverted. The controller increases the power of the first processor by boosting when the first pulse width modulation signal is at the first logic level, and increases the boost by the boost when the second pulse width modulation signal is at the first logic level The power of the processor.

Based on the above, the present invention controls the two processors to switch to their upper power limit at high speed with a pulse width modulation signal, and dynamically allocates the system heat dissipation power that the computer system can provide according to the usage rate of the processor. According to this, it can ensure that the system temperature does not overheat and improve the system performance, and achieve the purpose of both the performance and temperature performance of the computer system.

The above described features and advantages of the present invention will be more apparent from the following description.

In the process of using a computer system, the power of the processor has a fairly direct impact on system performance and temperature. Since the system constantly monitors the power of the processor (for example, monitoring every hundred milliseconds), if the processor is overclocked to improve system performance, if the power is detected, the corresponding processing will be performed immediately. Controlling the system without excessive temperature rise allows the computer system to balance performance and temperature performance. The present invention is a computer system and a power sharing method thereof which have been developed based on the above-mentioned viewpoints. In order to clarify the content of the present invention, the following specific embodiments are exemplified by the present invention.

1 is a block diagram of a computer system in accordance with an embodiment of the present invention. Referring to FIG. 1, the computer system 100 includes a first processor 110, a second processor 120, a chipset 130, a temperature sensor 140, and a controller 150. The computer system 100 of this embodiment is, for example, a notebook computer system, but the invention is not limited thereto. In other embodiments, computer system 100 can also be a desktop computer system or tablet computer or the like.

The first processor 110 is, for example, a central processing unit (Central Processing) Unit, CPU), used to control the overall operation of the computer system 100. The second processor 120 is, for example, a graphics processing unit (GPU) for generating an image signal presented on a screen or other display device (not shown).

The chipset 130 is coupled to the first processor 110, the second processor 120, and the controller 150. In one embodiment, the wafer set 130 includes a south bridge wafer and a north bridge wafer, wherein the south bridge wafer is used to connect the controller 150, a basic input/output system (not shown), and a slower peripheral device, and the north bridge wafer is connected as The first processor 110, the second processor 120, and a faster memory component such as a main memory (not shown).

The temperature sensor 140 is configured to detect the system temperature of the computer system 100, which may include the temperature of the central processing unit, the temperature of the graphics processor, the temperature of the main memory, and the surface temperature of the computer system 100. For example, the temperature sensor 140 can include a plurality of sensors disposed around the components of the central processing unit, the graphics processor, and the main memory to detect the temperature thereof.

The controller 150 is coupled to the temperature sensor 140. In this embodiment, the controller 150 is, for example, an embedded controller (EC) for controlling the power of the computer system 100, an input device (such as a keyboard or a touch pad, etc.), and can receive a sense of temperature. The temperature information sensed by the detector 140. In particular, the present embodiment the controller 150 of the embodiment will utilize pulse width modulation signal PWM received by _control processor 110 of the first and the second processor 120 in a short time overclocking interaction, and to ensure that the first and the second processor 110 The second processor 120 does not experience simultaneous overclocking to provide higher performance to the computer system 100 at the same temperature performance.

A detailed flow of implementing the power sharing method in the computer system 100 will be described below with another embodiment in conjunction with FIG. 2 is a flow chart of a power sharing method according to an embodiment of the invention. Please also refer to Figure 1 and Figure 2.

First, as shown in step S210, the controller 150 receives the pulse width modulation signal PWM ₁ having a duty cycle. Taking FIG. 3A as an example, the duty cycle of the PWM signal PWM ₁ is 20%, that is, within each clock cycle T, the pulse width modulation signal PWM ₁ is at a high logic level H for 20% of the time. And 80% of the time is at the low logic level L. In the embodiment shown in FIG. 3B, the duty cycle of the PWM signal PWM ₁ is 60%, that is, the pulse width modulation signal PWM1 is 60% of the time in each clock cycle T. Level H, and 40% of the time is at low logic level L.

Next, in step S220, the controller 150 defines the system heat dissipation power as the sum of the temperature design power (TDP) preset by the first processor 110 and the second processor 120. In this embodiment, the temperature design power of the first processor 110 and the second processor 120 can be adjusted, however, the initial preset value is clearly defined in the specification of the processor, and the controller 150 can pass through the chipset. The preset value of the temperature design power of the first processor 110 and the second processor 120 is read.

In step S230, the controller 150 determines whether the system heat dissipation power is greater than or equal to a preset upper limit value. If the system cooling power is less than the preset upper limit, it means that the computer system 100 does not need to perform power sharing at present. Thus, the flow of the power sharing method of the present embodiment is ended.

However, if the system heat dissipation power is greater than or equal to the preset upper limit value, then the controller 150 adjusts the power of the first processor 110 and the second processor 120 by using the pulse width modulation signal PWM ₁ as shown in step S240. The time for boosting the power of the first processor 110 by boosting does not overlap with the time for boosting the power of the second processor 120 by boosting.

In this embodiment, the controller 150 boosts the power of the first processor 110 by boosting when the pulse width modulation signal PWM _{1 is} at the first logic level (eg, a high logic level), and adjusts the pulse width. The power of the second processor 120 is boosted by the boost when the signal PWM _{1 is} at the second logic level (eg, low logic level). Further, the controller 150 boosts the power of the first processor 110 to the upper power limit (eg, the maximum value of the temperature design power) by using the boost when the pulse width modulation signal PWM _{1 is} at the high logic level. When the pulse width modulation signal PWM _{1 is} at the low logic level, the power of the first processor 110 is adjusted back to the original set value of the temperature design power. Conversely, the power of the second processor 120 is boosted to a maximum value when the pulse width modulation signal PWM _{1 is} at a low logic level, and is reset when the pulse width modulation signal PWM _{1 is} at a high logic level. The originally set power. Since the PWM signal PWM ₁ is continuously switched between the high logic level and the low logic level, the first processor 110 and the second processor 120 can be quickly increased in power to increase the computer system 100. The efficiency and the power can be pulled back to the original set value before the system temperature has risen, and the heat can be effectively cooled to avoid the system temperature being too high. In addition, since the pulse width modulation signal PWM _{1 is} not at the high logic level and the low logic level at the same time, the mechanism can also ensure that the power of the first processor 110 and the second processor 120 are not raised to the upper limit at the same time. To ensure that no system temperature surges.

Next, in step S250, the controller 150 obtains the current system temperature from the temperature sensor 140 and compares it with the previous temperature to determine whether the system temperature of the computer system 100 has risen.

If the system temperature of the computer system 100 rises, as shown in step S260, the controller 150 reduces the duty cycle of the pulse width modulation signal PWM ₁ or reduces the system heat dissipation power to shorten the time for boosting power by boosting. In detail, if the controller 150 determines that the duty cycle has not reached the lower limit of the period (for example, 10%, but the invention is not limited thereto), the duty cycle is reduced to shorten the use of the boost to improve the first processor 110 or the second. The time of the power of the processor 120. If the controller 150 determines that the duty cycle has reached the lower limit of the cycle, the system heat dissipation power is reduced to shorten the time for boosting the power of the first processor 110 or the second processor 120.

If the system temperature of the computer system 100 drops, as shown in step S270, the controller 150 increases the duty cycle of the pulse width modulation signal PWM ₁ or increases the system heat dissipation power to increase the time for boosting power by boosting. Specifically, if the controller 150 determines that the responsibility period does not reach the upper limit of the period (for example, 90%, but the invention is not limited thereto), the duty cycle is increased to increase the boosting to improve the first processor 110 or the second. The time of the power of the processor 120, and if the controller 150 determines that the duty cycle has reached the upper limit of the cycle, the system heat dissipation power is increased to increase the time during which the boost is utilized to increase the power of the first processor 110 or the second processor 120.

After the above steps, the duty cycle or the system heat dissipation power of the pulse width modulation signal PWM ₁ may increase or decrease. Then, the power sharing method of the embodiment returns to step S230 to determine whether the current system heat dissipation power is greater than or Equal to the preset upper limit. If yes, the action of step S240 is performed according to the duty cycle of the current pulse width modulation signal PWM ₁ , and step S260 or step S270 is determined to be performed according to the determination result of step S250. The power sharing method of this embodiment will repeat steps S230 to S270 until the system heat dissipation power is less than the preset upper limit value.

As shown in FIG. 2, this embodiment controls the time for boosting the power of the processor by boosting according to the rise and fall of the system temperature of the computer system 100. This ensures that the performance of the computer system 100 is improved while not adversely affecting temperature performance.

On the other hand, since the first processor 110 and the second processor 120 are not in a high usage state at the same time in most of the usage conditions, the following embodiments illustrate how to provide limited heat dissipation space. The power consumption is adjusted according to the usage rate of the processor to improve system performance.

4 is a flow chart of a power sharing method according to another embodiment of the present invention. Please also refer to Figure 1 and Figure 4. Since steps S405 to S420 of FIG. 4 are the same as or similar to steps S210 to S240 of FIG. 2, they are not described herein again.

In this embodiment, after the controller 150 adjusts the power of the first processor 110 and the second processor 120 by using the pulse width modulation signal PWM ₁ , then, as shown in step S425, it is determined whether the first processor 110 needs to be determined. Usage rate. Specifically, if the release cycle of the power upper limit of the first processor 110 is dynamically set, the usage rate of the first processor 110 is not required to be determined, so the flow of the power sharing method of the embodiment will enter. Step S460. On the other hand, if it is not in the above release period, it is necessary to determine the usage rate of the first processor 110. Therefore, as shown in step S430, the controller 150 obtains the current usage power of the first processor 110, and according to the first processor 110. Power and temperature design power is currently used to determine whether the first processor is in a high usage state or a low usage state. In this embodiment, if the ratio of the currently used power to the temperature design power is less than a first preset value (eg, 50%), the controller 150 determines that the first processor 110 is in a low usage state, and if currently If the ratio of power to temperature design power is greater than a second predetermined value (eg, 80%), the controller 150 determines that the first processor 110 is in a high usage state.

According to the above judgment mechanism, if the result of the determination in step S435 is YES (ie, the first processor 110 is in the low usage state), then in step S440, the controller 150 decreases the temperature design power of the first processor 110, and The temperature design power of the second processor 120 is set as the difference between the system heat dissipation power and the current temperature design power of the first processor 110. That is to say, in this case, the temperature design power of the first processor 110 is adjusted down, and the excess power is distributed to the second processor 120. That is, the temperature design power of the second processor 120 is boosted.

If the result of the determination in step S435 is negative, then if the result of the determination in step S445 is YES (ie, the first processor 110 is in the high usage state), the controller 150 increases the first processor 110 as shown in step S450. The temperature design power, and the temperature design power of the second processor 120 is set as the difference between the system heat dissipation power and the current temperature design power of the first processor 110. value. That is, when the first processor 110 is in the high usage state, the power sharing method of the embodiment reduces the temperature design power of the second processor 120, and transfers the excess power to the first processor 110 to The temperature design power of the first processor 110 is boosted.

In short, steps S430 to S450 dynamically allocate system cooling power to the first processor 110 and the second processor 120 according to the load of the first processor 110. The next step S460 to step S480 is to determine how to control the power of the processor according to whether the system temperature of the computer system 100 rises. Since steps S460 to S480 are the same as or similar to steps S250 to S270 of FIG. Therefore, it will not be repeated here. The power sharing method shown in FIG. 4 will repeat steps S415 to S480 until the system heat dissipation power is less than the preset upper limit value.

In the above embodiment, the controller 150 monitors the current usage power of the first processor 110 and the second processor 120 by using a set of hardware lines, and obtains the temperatures of the first processor 110 and the second processor 120. The upper limit setting of the design power. When it is judged that the load of one processor is small, the excess power is transferred to another processor, and vice versa, thereby realizing the dynamic allocation of the system heat dissipation power.

In addition, even if both the first processor 110 and the second processor 120 are in high power demand, the power of the first processor 110 and the second processor 120 is switched to the upper limit quickly and alternately. It can be ensured that the system temperature does not rise excessively. The fast switching power cap enables the first processor 110 and the second processor 120 to operate at high speed in a short time to achieve higher system performance.

Although in the above embodiment, the controller 150 uses a pulse width modulation signal PWM ₁ to increase the power upper limit of the two processors, in another embodiment, the controller 150 can also receive two pulse width modulation signals PWM. ₁ and PWM ₂ , and control the two processors with the two pulse width modulation signals respectively.

In detail, the pulse width modulation signal PWM ₂ and the pulse width modulation signal PWM ₁ are mutually inverted. For example, as shown in FIG. 5, the duty cycle of the PWM signals PWM ₁ and PWM ₂ are both 50%, but when the PWM signal PWM _{1 is} at a high logic level in each clock cycle, The pulse width modulation signal PWM _{2 is} at a low logic level and vice versa. Then, the controller 150 adjusts the PWM responsibility ₁ cycle PWM signal will also affect the length of the pulse width modulation signals PWM ₁ and PWM _2. Specifically, when the duty cycle of the pulse width modulation signal PWM ₁ is adjusted by the controller 150, the pulse width modulation signal PWM ₂ is maintained in phase with the pulse width modulation signal PWM ₁ , so the duty cycle thereof is also Change with it.

In this embodiment, the controller 150 boosts the power of the first processor 110 with the boost when the pulse width modulation signal PWM _{1 is} at the first logic level (eg, a high logic level), and adjusts the pulse width. When the variable signal PWM _{2 is} at the first logic level, the power of the second processor 120 is boosted by the boost. Since the pulse width modulation signal PWM ₁ and the PWM ₂ are mutually inverted, it is possible to avoid the case where the power of the first processor 110 and the second processor 120 is simultaneously raised to the upper limit.

In summary, the computer system and the power sharing method thereof according to the present invention can achieve a balance between system performance and temperature. Further, since the surface temperature of the computer system depends on the accumulation of internal heat, the basis is The usage rate of the processor dynamically allocates the cooling power of the system and controls the high-speed switching of the two processors to the upper limit of the power by the pulse width modulation signal. This ensures that the processor operates at a high speed in a short time while controlling the heat source of the computer system to a certain extent. Within this, the computer system can be used to achieve better temperature performance without losing system performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ computer system

110‧‧‧First processor

120‧‧‧second processor

130‧‧‧chipset

140‧‧‧temperature sensor

150‧‧‧ Controller

PWM ₁ , PWM ₂ ‧‧‧ pulse width modulation signal

S210~S270‧‧‧ steps of the power sharing method according to an embodiment of the present invention

T‧‧‧ clock cycle

H‧‧‧High logic level

L‧‧‧Low logic level

S405~S480‧‧‧ steps of the power sharing method according to another embodiment of the present invention

1 is a block diagram of a computer system in accordance with an embodiment of the present invention.

2 is a flow chart of a power sharing method according to an embodiment of the invention.

3A and 3B are schematic diagrams showing a duty cycle of a pulse width modulation signal according to an embodiment of the invention.

4 is a flow chart of a power sharing method according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a duty cycle of different pulse width modulation signals according to another embodiment of the present invention.

S210~S270‧‧‧ steps of the power sharing method according to an embodiment of the present invention

Claims (12)

A power sharing method for a computer system including a first processor and a second processor, the method comprising the steps of: a. receiving a first pulse width modulation signal, wherein the first pulse width modulation The signal has a duty cycle; b. defines a system heat dissipation power as a sum of a temperature design power (TDP) of the first processor and the second processor; c. determining the heat dissipation of the system Whether the power is greater than or equal to a predetermined upper limit; d. if yes, adjusting the power of the first processor and the second processor by using the first pulse width modulation signal, wherein the first processor is boosted by boosting The time of the power does not overlap with the time for boosting the power of the second processor; e. determining whether the temperature of a system of the computer system is rising; f. if yes, reducing the duty cycle or the heat dissipation power of the system to shorten Use boost to increase power time; g. If not, increase the duty cycle or the system heat dissipation power to increase the time to use boost to increase power; and h. repeat steps c through g until the system heat dissipation power Less than the preset upper limit. The power sharing method of claim 1, wherein the step f comprises: determining whether the responsibility period reaches a lower limit of a period; If not, the duty cycle is reduced; and if so, the system cooling power is reduced. The power sharing method of claim 1, wherein the step g comprises: determining whether the responsibility period reaches an upper limit of the period; if not, increasing the responsibility period; and if so, increasing the heat dissipation power of the system. The power sharing method of claim 1, wherein the method further comprises: when the usage of the first processor needs to be determined, obtaining the first processor a current usage power; determining, according to the current usage power of the first processor and the temperature design power, that the first processor is in a high usage state or a low usage state; if the first processor is at the low The usage state, the temperature design power of the first processor is decreased, and the temperature design power of the second processor is set to a difference between the system heat dissipation power and the current temperature design power of the first processor. And if the first processor is in the high usage state, increasing the temperature design power of the first processor, and setting the temperature design power of the second processor to the system cooling power and the first The difference between the current design power of the processor. The power sharing method of claim 1, wherein the step d includes: Raising the power of the first processor by boosting when the first pulse width modulation signal is at a first logic level; and boosting when the first pulse width modulation signal is at a second logic level Increase the power of the second processor. The power sharing method of claim 1, wherein the step d includes: providing a second pulse width modulation signal, wherein the second pulse width modulation signal and the first pulse width modulation signal are mutually Inverting; increasing the power of the first processor by boosting when the first pulse width modulation signal is at a first logic level; and when the second pulse width modulation signal is at the first logic level The power of the second processor is increased by boosting. A computer system comprising: a first processor; a second processor; a chipset coupled to the first processor and a second processor; and a temperature sensor to sense one of the computer systems a system temperature coupled to the chip set and the temperature sensor, the controller receiving a first pulse width modulation signal, wherein the first pulse width modulation signal has a duty cycle, and defining a The system heat dissipation power is a sum of one of the temperature preset design powers of the first processor and the second processor; the controller uses the first when determining that the system heat dissipation power is greater than or equal to a predetermined upper limit value a pulse width modulation signal is adjusted to the first processor and The power of the second processor, wherein the time for boosting the power of the first processor by boosting does not overlap with the time for boosting the power of the second processor, and determining whether the temperature of the system of the computer system is Rising, reducing the duty cycle or the heat dissipation power of the system when determining the temperature rise of the system to shorten the time for using the boost to increase the power, and increasing the duty cycle or the heat dissipation power of the system to increase the utilization of the rise when the temperature of the system is determined to decrease. When the voltage is increased to increase the power, the controller repeats the foregoing operation until the system heat dissipation power is less than the preset upper limit value. The computer system of claim 7, wherein if the controller determines that the duty cycle has not reached a lower limit of a cycle, reducing the duty cycle to shorten the time for boosting power, and if the controller determines When the duty cycle reaches the lower limit of the cycle, the heat dissipation power of the system is reduced to shorten the time for boosting power by boosting. The computer system of claim 7, wherein if the controller determines that the duty cycle does not reach a cycle upper limit, increasing the responsibility cycle to increase the time for boosting power by using the boost, and if the controller determines When the duty cycle reaches the upper limit of the cycle, the heat dissipation power of the system is increased to increase the time for boosting power by using boost. The computer system of claim 7, wherein the controller adjusts the power of the first processor and the second processor by using the first pulse width modulation signal and determines the system temperature of the computer system Whether it is rising, or not, when determining the usage rate of the first processor, obtaining a current usage power of the first processor, and determining the first according to the current usage power of the first processor and the temperature design power of the first processor a processor is at In a high usage state or a low usage state, if the first processor is in the low usage state, reducing the temperature design power of the first processor, and designing the temperature of the second processor The power is set to a difference between the system cooling power and the current temperature design power of the first processor, and if the first processor is in the high usage state, increasing the temperature design power of the first processor, and The temperature design power of the second processor is set to a difference between the system heat dissipation power and the current temperature design power of the first processor. The computer system of claim 7, wherein the controller increases the power of the first processor by boosting when the first pulse width modulation signal is at a first logic level, and When the pulse width modulation signal is at a second logic level, the power of the second processor is increased by boosting. The computer system of claim 7, wherein the controller receives a second pulse width modulation signal, wherein the second pulse width modulation signal and the first pulse width modulation signal are mutually inverted. The controller increases the power of the first processor by boosting when the first pulse width modulation signal is at a first logic level, and when the second pulse width modulation signal is at the first logic level The power of the second processor is increased by boosting.