TWI481021B - Semiconductor device and manufacturing method and operating method for the same - Google Patents

Description

Semiconductor device, manufacturing method and operating method thereof

The present invention relates to a semiconductor device, a method of fabricating the same, and a method of operating the same, and more particularly to a semiconductor device having a variable threshold voltage, a method of fabricating the same, and a method of operating the same.

With the advancement of semiconductor technology, the shrinking capability of electronic components has been increasing, enabling electronic products to have more functions while maintaining a fixed size or even a smaller volume. As the processing volume of information becomes higher and higher, the demand for large-capacity and small-volume memory is also growing.

The current readable and writable memory system uses a transistor structure in conjunction with a memory unit for information storage, but this memory architecture has reached a bottleneck with the advancement of manufacturing technology. Therefore, advanced memory architectures have been proposed, such as phase change random access memory (PCRAM), magnetic random access memory (MRAM), and resistive random access memory. Resistive random access memory (RRAM), conductive bridging RAM (CBRAM), and the like.

However, current memory devices still need to be improved in operational efficiency.

A semiconductor device is provided. The semiconductor device includes a substrate, a doped region, and a stacked structure. The doped regions are located in the substrate. Stacked structure on the substrate on. The stacked structure includes a dielectric layer, an electrode layer, a solid electrolyte layer, and an ion supply layer.

A method of fabricating a semiconductor device is provided. The method includes the following steps. A substrate is provided. A doped region is formed in the substrate. A stacked structure is formed on the substrate. The stacked structure includes a dielectric layer, an electrode layer, a solid electrolyte layer, and an ion supply layer.

A method of operating a semiconductor device is provided. The method includes the following steps. A first bias voltage is supplied to the ion supply layer of the semiconductor device. A second bias is provided to the ion supply layer. The polarity of the first bias is opposite to the polarity of the second bias.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment. Referring to FIG. 1, a stacked structure 102 is formed on a semiconductor substrate 104. The stacked structure 102 may include a dielectric layer 106, an electrode layer 108, a solid electrolyte layer 110, and an ion supply layer 112 that are sequentially formed from bottom to top. In an embodiment, the solid electrolyte layer 110 is physically in contact between the electrode layer 108 and the ion supply layer 112. Source 114 and drain 116 are formed in semiconductor substrate 104 on opposite sides of stacked structure 102, respectively.

The semiconductor substrate 104 can include a germanium substrate, an overlying silicon oxide (SOI), a semiconductor epitaxial layer, or other suitable material.

Dielectric layer 106 can include an oxide, a nitride such as hafnium oxide (SiO2), tantalum nitride, hafnium oxynitride, a metal oxide, a high dielectric constant material, or other suitable material. Dielectric layer 106 can be a single layer of film, for example A single layer of oxide film, or a multilayer film such as an ONO structure, or other suitable structure. The dielectric layer 106 can be formed by deposition, thermal oxidation, thermal nitridation, or the like.

The electrode layer 108 may include polysilicon or a metal such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like. Electrode layer 108 can be a single layer film or a multilayer film such as a TiN/TaN/WN structure, or other suitable structure.

The material of the solid electrolyte layer 110 may be selected to have low electron conductivity and high ion conductivity. The solid electrolyte layer 110 may include an oxide, a nitride such as hafnium oxide (SiO2), tantalum nitride, hafnium oxynitride, a metal oxide, a high dielectric constant material, or other suitable materials. The solid electrolyte layer 110 may include hafnium oxide (Hf-oxide), zirconium oxide (Zr-oxide), or tantalum oxide (Ta-oxide) or the like. The solid electrolyte layer 110 may be a single layer thin film structure or a multilayer thin film structure. The solid electrolyte layer 110 may be formed in a suitable manner of deposition, thermal oxidation, thermal nitridation, or the like.

The ion supply layer 112 serves to supply movable ions to the solid electrolyte layer 110. In an embodiment, the soluble supply of ion supply layer 112 to ions is greater than the solubility of solid electrolyte layer 110 to ions. In some embodiments, ion supply layer 112 includes a chalcogenide containing a metallic material, such as a chalcogenide containing a metal such as copper, silver, zinc, or the like. The ion supply layer 112 may include a highly conductive material containing a Germanium Antimony Telluride (GST) such as Cu-GST, Au-GST, Zn-GST, or the like. The supplied ions may include metal ions such as copper ions, silver ions, zinc ions, and the like.

In an embodiment, the source 114 and the drain 116 may be formed after the dielectric layer 106 and the electrode layer 108 are formed. Then, other films of the stacked structure 102, such as the solid electrolyte layer 110 and the ion supply layer 112, are formed over the electrode layer 108. In other embodiments, the source 114 and the drain 116 may also be formed after all of the thin films of the stacked structure 102 are formed. The annealing step can be performed at an appropriate timing, for example, annealing at 400 ° C for 20 minutes after all the films of the stacked structure 102 are formed.

The manufacturing method of the semiconductor device according to the embodiment is simple, and the design of the stacked structure can also reduce the manufacturing area of the semiconductor device and contribute to the development of miniaturization. For example, each film in the stacked structure can be shrunk to a critical size of 5 nm node. For example, the storage of electrically neutral atoms in the solid electrolyte layer of the 5 nm node does not cause a coulomb blockade effect, which can improve the operational efficiency of the device.

In an embodiment, the semiconductor device can be regarded as a nonvolatile memory composed of a transistor and an electrochemical (EC) device. In other words, the device structure formed by the semiconductor substrate 104, the dielectric layer 106, the electrode layer 108, the source 114, and the drain 116 can be regarded as a transistor. The structural device composed of the electrode layer 108, the solid electrolyte layer 110, and the ion supply layer 112 can be regarded as an electrochemical device.

In an embodiment, electrode layer 108 is used as a floating gate electrode and ion supply layer 112 is used as a control gate electrode. In other words, only the ion supply layer 112 is coupled to the control electrode terminal 118 in the stacked structure 102. The electrode layer 108 is floating. The semiconductor substrate 104, the dielectric layer 106, and the electrode layer 108 constitute a device structure of a fixed capacitance. In the embodiment, the electrode layer 108, the solid electrolyte layer 110 and the ion supply layer 112 constitute a variable capacitor. Set the structure.

For example, the method of operation of the semiconductor device includes steps of stylization, reading and erasing, and the like.

Referring to FIG. 2, the method of programming a semiconductor device can include providing a first bias voltage V1 from the control electrode terminal 118 to the ion supply layer 112 of the semiconductor device. For example, the first bias voltage V1 is a positive bias voltage, such as a positive bias pulse, which may be relative to the semiconductor substrate 104, such as the semiconductor substrate 104 being grounded.

Referring to FIG. 2, the step of providing the first bias voltage V1 causes the charged carriers 120 in the semiconductor substrate 104 to tunnel through the dielectric layer 106 (ie, used as a tunneling layer) to the electrode layer 108 and transfer to the solid electrolyte. In layer 110. Charged charge carriers 120 include, for example, electrons. The step of providing the first bias voltage V1 simultaneously causes the ion supply layer 112 to provide ions 122 to move into the solid electrolyte layer 110. Ions 122 include metal ions such as positively charged copper ions, silver ions, or zinc ions.

Referring to FIG. 3, for example, the charged carrier 120 moved to the solid electrolyte layer 110 by the first bias voltage V1 is combined with the ion 122 to form a conductive medium 124 accumulated in the solid electrolyte layer 110 (ie, used as a storage). In the layer). The conductive medium 124 may include an electrically neutral metal atom such as a copper atom, a silver atom, or a zinc atom (ie, the solid electrolyte layer 110 functions as an atomic storage layer).

The conductive medium 124 generated in the solid electrolyte layer 110 by providing the first bias voltage V1 causes the conductivity of the solid electrolyte layer 110 to be improved, in other words, the dielectric constant and the permittivity are lowered. The step of providing the first bias voltage V1 to the ion supply layer 112 is caused by the electrode layer 108. The device structure formed by the solid electrolyte layer 110 and the ion supply layer 112 has a first capacitance Cs1. Further, the device structure constituted by the semiconductor substrate 104, the dielectric layer 106 and the electrode layer 108 has a capacitance value Cd1. The first capacitance value Cs1 and the capacitance value Cd1 having an electrical series relationship cause the semiconductor device to have the first threshold voltage Vt1.

In one embodiment, after stylizing the semiconductor device, the stylized state of the semiconductor device can be read. For example, a bias voltage can be applied from the source electrode terminal 126 and the drain electrode terminal 128 to the source 114 and the drain 116 for a read step, such as providing a bias voltage greater than zero to the source 114, and The drain 116 is grounded or other biasing configuration method is used.

Referring to FIG. 4, the method of erasing a semiconductor device can include providing a second bias voltage V2 from the control electrode terminal 118 to the ion supply layer 112 of the stacked structure 102. The polarity of the first bias voltage V1 for stylization is opposite to the polarity of the second bias voltage V2 for erasing. For example, the second bias voltage V2 is a negative bias voltage, such as a negative bias pulse, which may be relative to the semiconductor substrate 104, such as the semiconductor substrate 104 being grounded. In an embodiment, the erasing step can be performed after the stylization step or after the step of reading the stylized state.

Referring to FIG. 4, the step of providing the second bias voltage V2 causes the conductive medium 124 (Fig. 3) in the solid electrolyte layer 110 to decompose the charged carriers 120 and ions 122 having opposite electrical returns. Furthermore, charged carrier 120 is transferred from solid electrolyte layer 110 to electrode layer 108 and through dielectric layer 106 to semiconductor substrate 104. Charged charge carriers 120 include, for example, electrons. Further, ions 122 are attracted back from the solid electrolyte layer 110 into the ion supply layer 112. The ions 122 include metal ions such as positively charged copper ions, silver ions or zinc ions, and the like. By providing a second bias voltage V2 to the ion supply layer 112, half The conductor device is returned to the state shown in Fig. 1.

The conductive medium 124 in the solid electrolyte layer 110 is removed by the second bias voltage V2, so that the conductivity of the solid electrolyte layer 110 is lowered, in other words, the dielectric constant is increased. Therefore, the step of providing the second bias voltage V2 to the ion supply layer 112 causes the device structure composed of the electrode layer 108, the solid electrolyte layer 110 and the ion supply layer 112 to have a second capacitance value Cs2, and further, the semiconductor substrate 104, The device structure formed by the dielectric layer 106 and the electrode layer 108 has a capacitance value Cd2. The second capacitance value Cs2 and the capacitance value Cd2 having an electrical series relationship cause the semiconductor device to have the second threshold voltage Vt2. The capacitance value Cd2 caused by the second bias voltage V2 is the same as the capacitance value Cd1 caused by the first bias voltage V1. The second capacitance value Cs2 caused by the second bias voltage V2 is different from the first capacitance value Cs1 caused by the first bias voltage V1, that is, the coupling ratio of the first bias voltage to the semiconductor device is different from the first The coupling ratio of the two bias voltages to the semiconductor device. Therefore, the semiconductor device has the second threshold voltage Vt2 which is different from the first threshold voltage Vt1 and thus can correspond to different storage states. In an embodiment, the first capacitance value Cs1 is greater than the second capacitance value Cs2, that is, the coupling ratio of the first bias voltage to the semiconductor device is greater than the coupling ratio of the second bias voltage to the semiconductor device. Further, the first threshold voltage Vt1 is smaller than the second threshold voltage Vt2.

In an embodiment, after erasing the semiconductor device, the erased state of the semiconductor device can be read. For example, a bias voltage can be applied from the source electrode terminal 126 and the drain electrode terminal 128 to the source 114 and the drain 116 for a read step, such as providing a bias voltage greater than zero to the source 114, and The drain 116 is grounded or other biasing configuration method is used.

The semiconductor device according to the embodiment can be regarded as a 1T memory. In some In an embodiment, a two terminal RRAM device may use a semiconductor device according to an embodiment instead of a 1D1R or 1T1R device using a general charge storage structure, without the need for an additional driving device. The current in the stylization and erase steps is very low, mainly limited by the tunneling current. Thus the array can be designed to have a high cell density and the device has a low power consumption rate.

In an embodiment, the electrical characteristics of the semiconductor device in the stylized state and the erased state are as shown in FIG. 5. The stylized pulse is 12V/5us, and the erase pulse is -13V/1ms. The threshold voltage obtained by providing a stylized pulse is 1.4V @ 10nA. The threshold voltage obtained by providing the erase pulse is 2.4V @ 10nA. In this example, the threshold voltage difference between stylization and erase is approximately 1V.

The difference between the semiconductor device shown in FIG. 6 and the semiconductor device shown in FIG. 1 is that the stacked structure 102A includes the conductive layer 130 on the ion supply layer 112. The ion supply layer 112 is coupled to the control electrode end 118 through the conductive layer 130. The conductive layer 130 can serve as a barrier layer, which can prevent ion diffusion in the ion supply layer 112 to improve the operational efficiency of the device. The conductive layer 130 may include polysilicon or a metal such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like. Conductive layer 130 can be a single layer film or a multilayer film such as a TiN/TaN/WN structure, or other suitable structure.

The difference between the semiconductor device shown in FIG. 7 and the semiconductor device shown in FIG. 6 is that the spacers 132 are formed on the sidewalls of the dielectric layer 106 and the electrode layer 108 of the stacked structure 102A. This design concept can also be extended to the semiconductor device as shown in FIG. In an embodiment, the spacers 132 may be formed after the dielectric layer 106 and the electrode layer 108 are formed. Then, the semiconductor substrate 104 is doped with the spacer 132 as a doping mask to form a source. Pole 114, bungee 116. Then, other films of the stacked structure 102A, such as the solid electrolyte layer 110, the ion supply layer 112, and the conductive layer 130 are formed over the electrode layer 108. In other embodiments, the spacers 132 may be formed after all the thin films of the stacked structure 102A are formed, and then the source 114 and the drain 116 are formed. The annealing step can be performed at an appropriate timing, for example, annealing at 400 ° C for 20 minutes after all the films of the stacked structure 102A are formed.

The difference between the semiconductor device shown in FIG. 8 and the semiconductor device shown in FIG. 7 is that the spacers 132A are formed on the sidewalls of all the films of the stacked structure 102A. In the embodiment, the spacers 132A formed on the sidewalls of the solid electrolyte layer 110 and the ion supply layer 112 can serve as a barrier layer, and the diffusion of ions in the solid electrolyte layer 110 and the ion supply layer 112 can be avoided to improve the operation of the device. efficacy. This design concept can also be extended to the semiconductor device as shown in FIG.

The embodiments are disclosed above, but are not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope of the patent application is subject to change.

102, 102A‧‧‧Stack structure

104‧‧‧Semiconductor substrate

106‧‧‧Dielectric layer

108‧‧‧electrode layer

110‧‧‧Solid electrolyte layer

112‧‧‧Ion supply layer

114‧‧‧ source

116‧‧‧汲polar

118‧‧‧Control electrode end

120‧‧‧charged charge carriers

122‧‧‧ ions

124‧‧‧Electrical medium

126‧‧‧Source electrode end

128‧‧‧汲 electrode tip

130‧‧‧ Conductive layer

132, 132A‧‧‧ spacer

V1‧‧‧First bias

V2‧‧‧second bias

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

FIG. 2 is a schematic diagram showing the operation of a semiconductor device according to an embodiment.

FIG. 3 is a schematic diagram showing the operation of a semiconductor device according to an embodiment.

FIG. 4 is a schematic diagram showing the operation of a semiconductor device according to an embodiment.

FIG. 5 is a schematic diagram showing the operation of a semiconductor device according to an embodiment.

FIG. 6 is an electrical diagram of a semiconductor device in accordance with an embodiment.

FIG. 7 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

FIG. 8 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

102‧‧‧Stack structure

104‧‧‧Semiconductor substrate

106‧‧‧Dielectric layer

108‧‧‧electrode layer

110‧‧‧Solid electrolyte layer

112‧‧‧Ion supply layer

114‧‧‧ source

116‧‧‧汲polar

118‧‧‧Control electrode end

126‧‧‧Source electrode end

128‧‧‧汲 electrode tip

Claims (10)

A semiconductor device comprising: a substrate; a doped region in the substrate; and a stacked structure on the substrate, the stacked structure comprising: a dielectric layer; an electrode layer; a solid electrolyte layer; An ion supply layer for supplying movable ions to the solid electrolyte layer. The semiconductor device of claim 1, wherein the solid electrolyte layer is between the electrode layer and the ion supply layer. The semiconductor device of claim 1, wherein the electrode layer is used as a floating gate, and the ion supply layer is used as a control gate. The semiconductor device according to claim 1, wherein the electrode layer, the solid electrolyte layer and the ion supply layer form a variable capacitance device structure, and the substrate, the dielectric layer and the electrode layer are formed. A device structure with a fixed capacitance. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a doped region in the substrate; and forming a stacked structure on the substrate, the stacked structure comprising: a dielectric layer; an electrode layer; a solid electrolyte layer; and an ion supply layer for supplying movable ions to the solid electrolyte layer. The method of claim 5, wherein the electrode layer, the solid electrolyte layer and the ion supply layer form a variable capacitance device structure, and the substrate, the dielectric layer and the electrode layer form a Device structure for fixed capacitors. A method of operating a semiconductor device, comprising: providing a first bias voltage to the ion supply layer of the semiconductor device according to claim 1; and providing a second bias voltage to the ion supply layer, wherein the The polarity of a bias is opposite to the polarity of the second bias. The method of operating a semiconductor device according to claim 7, wherein the step of providing the first bias voltage to the ion supply layer causes the semiconductor device to have a first threshold voltage, and the second bias voltage is supplied to the semiconductor device The step of supplying the ion layer causes the semiconductor device to have a second threshold voltage, wherein the first threshold voltage is different from the second threshold voltage. The method of operating a semiconductor device according to claim 7, wherein the step of providing the first bias voltage to the ion supply layer is caused by the electrode layer, the solid electrolyte layer and the ion supply layer. The device structure has a first capacitance value, and the step of providing the second bias voltage to the ion supply layer causes the device structure to have a second capacitance value, wherein the first capacitance value is different from the second capacitance value. The method of operating a semiconductor device according to claim 7, wherein the step of providing the first bias voltage causes a charge carrier in the substrate to tunnel through the dielectric layer to the electrode layer and transfer to the In the solid electrolyte layer, and causing the ion supply layer to provide an ion to the solid electrolyte layer, the step of providing the second bias causes the charged charge carrier to move back from the solid electrolyte layer to the substrate and cause the ion The solid electrolyte layer is moved back into the ion supply layer.