TWI480879B - Flash memory and memory cell programming method thereof - Google Patents
Flash memory and memory cell programming method thereof Download PDFInfo
- Publication number
- TWI480879B TWI480879B TW100137696A TW100137696A TWI480879B TW I480879 B TWI480879 B TW I480879B TW 100137696 A TW100137696 A TW 100137696A TW 100137696 A TW100137696 A TW 100137696A TW I480879 B TWI480879 B TW I480879B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- write
- verification
- memory cell
- less
- Prior art date
Links
Landscapes
- Read Only Memory (AREA)
Description
本發明是有關於一種快閃記憶體，且特別是有關於一種快閃記憶體及其記憶胞寫入方法。The present invention relates to a flash memory, and more particularly to a flash memory and a memory cell writing method thereof.
快閃記憶體因具有非揮發性(non-volatile)、高密集度、以及反應速度快...等特性，而在眾多的記憶體中嶄露頭角。對於記憶體而言，記憶資料的保存與元件的可靠度息息相關。因此，近年來許多不同的快閃記憶體之資料寫入方法陸續被提出，以提升快閃記憶體之可靠度。Flash memory has emerged in many memories due to its non-volatile, high-density, and fast response characteristics. For memory, the preservation of memory data is closely related to the reliability of components. Therefore, in recent years, many different flash memory data writing methods have been proposed to improve the reliability of flash memory.
在程式化快閃記憶體時常需使用高電壓將資料寫入，而由於半導體製程差異的關係，往往會使得快閃記憶體中的記憶胞所需的寫入電壓不盡相同。為確保每個記憶胞皆能正確地被寫入資料，傳統的解決方式為提高寫入電壓，然此種方式將有降低快閃記憶體的可靠度的風險。如圖1之快閃記憶體的記憶胞陣列所示，當由位元線BL施予高電壓對記憶胞102進行程式化時，記憶胞104也會受到高電壓的影響，因此記憶胞104內的電子會由汲極端漸漸地流失，而影響快閃記憶體的可靠度。此外，以高寫入電壓將資料寫入快閃記憶體除了影響快閃記憶體的可靠度外，亦會造成電源浪費、電路面積增加、快閃記憶體壽命減短等缺點。In stylized flash memory, it is often necessary to use high voltage to write data. Due to the difference in semiconductor process, the write voltage required by the memory cells in the flash memory is often different. In order to ensure that each memory cell can be correctly written to the data, the traditional solution is to increase the write voltage, but this way there will be a risk of reducing the reliability of the flash memory. As shown in the memory cell array of the flash memory of FIG. 1, when the memory cell 102 is programmed by the high voltage applied to the bit line BL, the memory cell 104 is also affected by the high voltage, so that the memory cell 104 is inside. The electrons are gradually lost due to extremes, which affects the reliability of flash memory. In addition, writing data to the flash memory with a high write voltage not only affects the reliability of the flash memory, but also causes power waste, increased circuit area, and shortened flash memory life.
本發明提供一種快閃記憶體的記憶胞寫入裝置及方法，可減少製程偏移在寫入操作時所造成的影響，進而提高產品良率以及改善汲極干擾(drain disturb)。The invention provides a memory cell writing device and a method for flash memory, which can reduce the influence of process offset in a writing operation, thereby improving product yield and improving drain disturbance.
本發明提出一種快閃記憶體的記憶胞寫入方法，包括：施加一預設寫入電壓於記憶胞以寫入記憶胞；施加一第一驗證電壓於記憶胞，以偵測記憶胞的寫入結果；以及，依據記憶胞的寫入結果調整施加於記憶胞的一寫入電壓。The invention provides a method for writing a memory cell of a flash memory, comprising: applying a predetermined write voltage to a memory cell to write to a memory cell; applying a first verification voltage to the memory cell to detect writing of the memory cell And entering a result; and adjusting a write voltage applied to the memory cell according to the writing result of the memory cell.
在本發明之一實施例中，上述之依據記憶胞的寫入結果調整施加於記憶胞的寫入電壓的步驟包括：判斷記憶胞的一臨界電壓是否大於等於一第二驗證電壓；若臨界電壓大於等於第二驗證電壓，將寫入電壓調整為一第一寫入電壓；若臨界電壓小於第二驗證電壓，判斷臨界電壓是否大於等於一第三驗證電壓；若臨界電壓大於等於第三驗證電壓，將寫入電壓調整為一第二寫入電壓；以及，若臨界電壓小於第三驗證電壓，將寫入電壓調整為一第三寫入電壓，其中第一驗證電壓小於第二驗證電壓且大於第三驗證電壓，第二寫入電壓大於第一寫入電壓且小於第三寫入電壓。In an embodiment of the invention, the step of adjusting the write voltage applied to the memory cell according to the writing result of the memory cell includes: determining whether a threshold voltage of the memory cell is greater than or equal to a second verification voltage; and if the threshold voltage And greater than or equal to the second verification voltage, the write voltage is adjusted to a first write voltage; if the threshold voltage is less than the second verification voltage, determining whether the threshold voltage is greater than or equal to a third verification voltage; if the threshold voltage is greater than or equal to the third verification voltage Adjusting the write voltage to a second write voltage; and, if the threshold voltage is less than the third verify voltage, adjusting the write voltage to a third write voltage, wherein the first verify voltage is less than the second verify voltage and greater than The third verification voltage, the second write voltage is greater than the first write voltage and less than the third write voltage.
在本發明之一實施例中，上述之依據記憶胞的寫入結果調整施加於記憶胞的寫入電壓的步驟包括：判斷記憶胞的一臨界電壓是否小於等於一第二驗證電壓；若臨界電壓小於等於第二驗證電壓，將寫入電壓調整為一第一寫入電壓；若臨界電壓大於第二驗證電壓，判斷臨界電壓是否小於等於一第三驗證電壓；若臨界電壓小於等於第三驗證電壓，將寫入電壓調整為一第二寫入電壓；以及，若臨界電壓大於第三驗證電壓，將寫入電壓調整為一第三寫入電壓，其中第一驗證電壓大於第二驗證電壓且小於第三驗證電壓，第二寫入電壓小於第一寫入電壓且大於第三寫入電壓。In an embodiment of the invention, the step of adjusting the write voltage applied to the memory cell according to the writing result of the memory cell includes: determining whether a threshold voltage of the memory cell is less than or equal to a second verification voltage; The second verification voltage is equal to or less than the second verification voltage, and the write voltage is adjusted to a first write voltage; if the threshold voltage is greater than the second verification voltage, it is determined whether the threshold voltage is less than or equal to a third verification voltage; if the threshold voltage is less than or equal to the third verification voltage Adjusting the write voltage to a second write voltage; and, if the threshold voltage is greater than the third verify voltage, adjusting the write voltage to a third write voltage, wherein the first verify voltage is greater than the second verify voltage and less than The third verification voltage, the second write voltage is less than the first write voltage and greater than the third write voltage.
在本發明之一實施例中，上述之依據記憶胞的寫入結果調整施加於記憶胞的寫入電壓的步驟包括：同時分別判斷記憶胞的一臨界電壓是否大於等於一第二驗證電壓與一第三驗證電壓，其中第一驗證電壓小於第二驗證電壓且大於第三驗證電壓；以及，依據臨界電壓與第二驗證電壓以及第三驗證電壓的比較結果調整寫入電壓。In an embodiment of the invention, the step of adjusting the write voltage applied to the memory cell according to the writing result of the memory cell includes: simultaneously determining whether a threshold voltage of the memory cell is greater than or equal to a second verification voltage and a a third verification voltage, wherein the first verification voltage is less than the second verification voltage and greater than the third verification voltage; and the write voltage is adjusted according to a comparison result of the threshold voltage and the second verification voltage and the third verification voltage.
在本發明之一實施例中，其中當臨界電壓大於等於第二驗證電壓以及第三驗證電壓時，將寫入電壓調整為一第一寫入電壓；當臨界電壓大於等於第三驗證電壓且小於第二驗證電壓時，將寫入電壓調整為一第二寫入電壓；當臨界電壓小於第二驗證電壓以及第三驗證電壓時，將寫入電壓調整為一第三寫入電壓，其中第二寫入電壓大於第一寫入電壓且小於第三寫入電壓。In an embodiment of the invention, when the threshold voltage is greater than or equal to the second verification voltage and the third verification voltage, the write voltage is adjusted to a first write voltage; when the threshold voltage is greater than or equal to the third verification voltage and less than When the voltage is second verified, the write voltage is adjusted to a second write voltage; when the threshold voltage is less than the second verify voltage and the third verify voltage, the write voltage is adjusted to a third write voltage, wherein the second The write voltage is greater than the first write voltage and less than the third write voltage.
在本發明之一實施例中，快閃記憶體的記憶胞寫入方法，其中偵測記憶胞的寫入結果係偵測記憶胞的一讀取電流，以判斷記憶胞的寫入結果。In an embodiment of the present invention, a memory cell writing method of a flash memory, wherein detecting a memory cell write result detects a read current of the memory cell to determine a memory cell write result.
本發明亦提出一種快閃記憶體，包括一寫入驗證單元以及一寫入電壓控制單元。其中寫入驗證單元耦接記憶胞，用以施加一預設寫入電壓於記憶胞以寫入記憶胞，並施加一第一驗證電壓於記憶胞，以偵測記憶胞的寫入結果。寫入電壓控制單元耦接寫入驗證單元與記憶胞，用以依據記憶胞的寫入結果調整施加於記憶胞的一寫入電壓。The invention also provides a flash memory comprising a write verifying unit and a write voltage control unit. The write verification unit is coupled to the memory cell for applying a predetermined write voltage to the memory cell to write to the memory cell, and applying a first verification voltage to the memory cell to detect the memory cell write result. The write voltage control unit is coupled to the write verification unit and the memory cell for adjusting a write voltage applied to the memory cell according to the write result of the memory cell.
基於上述，本發明透過依據快閃記憶體的記憶胞的寫入結果來調整施加於記憶胞的寫入電壓，以減少製程差異在寫入操作時所造成的影響，進而提高產品良率以及改善汲極干擾。Based on the above, the present invention adjusts the write voltage applied to the memory cell according to the writing result of the memory cell of the flash memory to reduce the influence of the process difference in the writing operation, thereby improving the product yield and improving. Bungee interference.
為讓本發明之上述特徵和優點能更明顯易懂，下文持舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2繪示為本發明一實施例之快閃記憶體的示意圖。請參照圖2，快閃記憶體200包括多個記憶胞202所組成的記憶胞陣列(為方便說明，本實施例僅繪示4個記憶胞202作為代表)、一寫入驗證單元204以及一寫入電壓控制單元206。其中各個記憶胞202分別透過源極線SL與位元線BL耦接至寫入電壓控制單元206，並透過控制線CL與字元線WL耦接至寫入驗證單元204。在本實施例中，記憶胞202可利用一選擇電晶體ST以及一記憶電晶體來實現(假設其皆為P型電晶體)，然在實際應用上記憶胞202的實施方式並不以此為限。其中，選擇電晶體ST的源極耦接至源極線SL，選擇電晶體ST的閘極耦接至字元線WL，選擇電晶體ST的汲極耦接至記憶電晶體MT的源極，另外記憶電晶體MT的閘極與汲極則分別耦接至控制線CL以及位元線BL。寫入驗證單元204用以透過控制線CL施加預設寫入電壓與驗證電壓至記憶胞202，並透過字元線WL選擇控制欲寫入的記憶胞202。寫入電壓控制單元206則用以依據寫入驗證單元204所偵測的寫入結果調整施加於記憶胞202的寫入電壓。2 is a schematic diagram of a flash memory according to an embodiment of the invention. Referring to FIG. 2, the flash memory 200 includes a memory cell array composed of a plurality of memory cells 202 (for convenience of description, only four memory cells 202 are represented as representative), a write verification unit 204, and a The voltage control unit 206 is written. Each of the memory cells 202 is coupled to the write voltage control unit 206 via the source line SL and the bit line BL, and coupled to the write verification unit 204 via the control line CL and the word line WL. In this embodiment, the memory cell 202 can be implemented by using a selection transistor ST and a memory transistor (assuming that they are both P-type transistors). However, in practical applications, the implementation of the memory cell 202 is not limit. The source of the selection transistor ST is coupled to the source line SL, the gate of the selection transistor ST is coupled to the word line WL, and the gate of the selection transistor ST is coupled to the source of the memory transistor MT. In addition, the gate and the drain of the memory transistor MT are respectively coupled to the control line CL and the bit line BL. The write verification unit 204 is configured to apply a preset write voltage and a verify voltage to the memory cell 202 through the control line CL, and select and control the memory cell 202 to be written through the word line WL. The write voltage control unit 206 is configured to adjust the write voltage applied to the memory cell 202 according to the write result detected by the write verification unit 204.
值得注意的是，由於利用負電壓作為電晶體的控制電壓在實際應用上較為困難，因此可藉由將位元線BL耦接至接地電壓，並將源極線SL耦接至正電壓，以透過調整與源極線SL耦接的正電壓來對記憶胞202進行寫入操作，然並不以此為限。另外，在部分實施例中，寫入電壓控制單元206亦可偵測位元線BL上的讀取電流，以求得記憶胞202的寫入結果，並依據記憶胞202的寫入結果調整施加於記憶胞202的寫入電壓。It is worth noting that since the use of a negative voltage as the control voltage of the transistor is difficult in practical applications, the bit line BL can be coupled to the ground voltage and the source line SL can be coupled to the positive voltage. The memory cell 202 is written by adjusting the positive voltage coupled to the source line SL, but is not limited thereto. In addition, in some embodiments, the write voltage control unit 206 can also detect the read current on the bit line BL to obtain the write result of the memory cell 202, and adjust the application according to the write result of the memory cell 202. The write voltage of the memory cell 202.
圖3繪示為本發明一實施例之快閃記憶體的記憶胞寫入方法流程圖。以下將配合圖2與圖3說明快閃記憶體200的記憶胞寫入方法，請同時參照圖2與圖3。首先，為了依據製程差異在記憶胞202中所造成的多晶矽閘極長度(poly gate length)的不同而給予記憶胞202不同的寫入電壓，寫入驗證單元204施加一預設寫入電壓於記憶胞202以寫入記憶胞202(步驟S302)，並施加一第一驗證電壓於記憶胞202，以偵測記憶胞的寫入結果(步驟S304)。其中不同的多晶矽閘極長度將造成所偵測到之記憶胞202中記憶電晶體MT的臨界電壓(threshold voltage)不同。值得注意的是，記憶胞202的寫入結果亦可以利用偵測記憶胞202的讀取電流大小來獲得。3 is a flow chart of a method for writing a memory cell of a flash memory according to an embodiment of the invention. Hereinafter, a memory cell writing method of the flash memory 200 will be described with reference to FIGS. 2 and 3, and please refer to FIG. 2 and FIG. First, in order to give a different write voltage to the memory cell 202 depending on the poly gate length caused by the process difference in the memory cell 202, the write verifying unit 204 applies a predetermined write voltage to the memory. The cell 202 is written to the memory cell 202 (step S302), and a first verification voltage is applied to the memory cell 202 to detect the writing result of the memory cell (step S304). The different polysilicon gate lengths will cause the threshold voltage of the memory transistor MT in the detected memory cell 202 to be different. It should be noted that the writing result of the memory cell 202 can also be obtained by detecting the read current of the memory cell 202.
接著，寫入電壓控制單元206依據寫入驗證單元204所偵測的寫入結果調整施加於記憶胞202的寫入電壓(步驟S306)，例如對臨界電壓較小(多晶矽閘極長度較長)的記憶胞202施加較大的寫入電壓，而對臨界電壓較大(多晶矽閘極長度較短)的記憶胞202施加較小的寫入電壓。如此針對具有不同臨界電壓的記憶胞202給予不同的寫入電壓便可確保各個記憶胞202皆能正確地寫入資料，同時並提高產品的良率、減少汲極干擾、降低寫入電流、增加記憶胞202的耐久度及可靠度。Next, the write voltage control unit 206 adjusts the write voltage applied to the memory cell 202 according to the write result detected by the write verifying unit 204 (step S306), for example, the threshold voltage is small (the polysilicon gate length is long). The memory cell 202 applies a larger write voltage, while a smaller write voltage is applied to the memory cell 202 having a larger threshold voltage (the polysilicon gate length is shorter). Thus, different memory voltages are applied to the memory cells 202 having different threshold voltages to ensure that each memory cell 202 can correctly write data, and at the same time, improve product yield, reduce buckling interference, reduce write current, and increase The durability and reliability of the memory cell 202.
詳細來說，寫入電壓控制單元206依據寫入驗證單元204所偵測的寫入結果調整寫入電壓的方法(亦即步驟S306)可如圖4所示。在偵測出記憶胞202的寫入結果後，寫入電壓控制單元206判斷記憶胞202的臨界電壓是否大於等於一第二驗證電壓(步驟S402)。若臨界電壓大於等於第二驗證電壓，則寫入電壓控制單元206將寫入電壓調整為第一寫入電壓(步驟S404)。若臨界電壓小於第二驗證電壓，則寫入電壓控制單元206繼續判斷臨界電壓是否大於等於一第三驗證電壓(步驟S406)。若臨界電壓大於等於第三驗證電壓，則寫入電壓控制單元206將寫入電壓調整為一第二寫入電壓(步驟S408)。若臨界電壓小於第三驗證電壓，寫入電壓控制單元206將寫入電壓調整為一第三寫入電壓(步驟S410)。其中第一驗證電壓小於第二驗證電壓且大於第三驗證電壓，而第二寫入電壓大於第一寫入電壓且小於第三寫入電壓。藉由第二驗證電壓與第三驗證電壓可將記憶胞202的臨界電壓值劃分為三個區間，而各個區間分別對應一寫入電壓。In detail, the method in which the write voltage control unit 206 adjusts the write voltage according to the write result detected by the write verifying unit 204 (ie, step S306) may be as shown in FIG. 4. After detecting the writing result of the memory cell 202, the write voltage control unit 206 determines whether the threshold voltage of the memory cell 202 is greater than or equal to a second verification voltage (step S402). If the threshold voltage is greater than or equal to the second verification voltage, the write voltage control unit 206 adjusts the write voltage to the first write voltage (step S404). If the threshold voltage is less than the second verification voltage, the write voltage control unit 206 continues to determine whether the threshold voltage is greater than or equal to a third verification voltage (step S406). If the threshold voltage is greater than or equal to the third verification voltage, the write voltage control unit 206 adjusts the write voltage to a second write voltage (step S408). If the threshold voltage is less than the third verification voltage, the write voltage control unit 206 adjusts the write voltage to a third write voltage (step S410). The first verify voltage is greater than the second verify voltage and greater than the third verify voltage, and the second write voltage is greater than the first write voltage and less than the third write voltage. The threshold voltage value of the memory cell 202 can be divided into three sections by the second verification voltage and the third verification voltage, and each section corresponds to a write voltage.
舉例來說，可將第二驗證電壓與第三驗證電壓分別設為4V與2V，其中臨界電壓高於4V的記憶胞202，其寫入電壓被調整為4.5V(亦即第一寫入電壓)，臨界電壓介於4V與2V間的記憶胞202的寫入電壓被調整為5V(亦即第二寫入電壓)，而臨界電壓低於2V的記憶胞202的寫入電壓則被調整為5.5V。另外，步驟S302中的預設寫入電壓以及步驟S304中的第一驗證電壓則可分別設為5V和3V，然亦不以此為限。For example, the second verification voltage and the third verification voltage can be set to 4V and 2V, respectively, wherein the memory voltage of the memory cell 202 whose threshold voltage is higher than 4V is adjusted to 4.5V (ie, the first write voltage). The write voltage of the memory cell 202 with a threshold voltage between 4V and 2V is adjusted to 5V (ie, the second write voltage), and the write voltage of the memory cell 202 whose threshold voltage is lower than 2V is adjusted to 5.5V. In addition, the preset write voltage in step S302 and the first verify voltage in step S304 can be set to 5V and 3V, respectively, but not limited thereto.
圖5A繪示為習知之記憶胞寫入方法的汲極干擾示意圖。圖5B繪示為利用本發明實施例之記憶胞寫入方法改善汲極干擾的示意圖。如圖5A所示，假設記憶胞202在未被選擇進行寫入操作時，其臨界電壓值應小於1V。為使各個具有不同多晶矽閘極長度的記憶胞202皆能正確地寫入資料，必須將寫入電壓拉高至符合多晶矽閘極長度最長的記憶胞202所需的電壓。然此種作法將使得多晶矽閘極長度較短(長度為0.12um)的記憶胞202受到鄰近記憶胞寫入資料時位元線BL上的高電壓影響，而出現臨界電壓上升超出1V的情形，如此將使記憶胞202內的電子透過電晶體的汲極流出而影響到記憶胞202的可靠度。反觀圖5B可看出，藉由對具有不同多晶矽閘極長度的記憶胞202施加不同的寫入電壓，可使具有不同多晶矽閘極長度的記憶胞202的臨界電壓皆保持低於1V。由此可知，本實施例之記憶胞寫入方法確實可大幅地提高記憶胞202的可靠度。FIG. 5A is a schematic diagram showing the bungee interference of the conventional memory cell writing method. FIG. 5B is a schematic diagram of improving the drain interference by using the memory cell writing method of the embodiment of the present invention. As shown in FIG. 5A, it is assumed that the memory cell 202 should have a threshold voltage value of less than 1 V when it is not selected for a write operation. In order for each memory cell 202 having a different polysilicon gate length to correctly write data, the write voltage must be pulled high to the voltage required by the memory cell 202 that meets the longest polysilicon gate length. However, this method will make the memory cell 202 with a short polysilicon gate length (0.12 um length) affected by the high voltage on the bit line BL when the adjacent memory cell writes data, and the threshold voltage rises beyond 1 V. This will cause electrons in the memory cell 202 to flow out through the drain of the transistor to affect the reliability of the memory cell 202. In contrast, as can be seen in Figure 5B, by applying different write voltages to memory cells 202 having different polysilicon gate lengths, the threshold voltage of memory cells 202 having different polysilicon gate lengths can be kept below 1V. Therefore, it can be seen that the memory cell writing method of the present embodiment can greatly improve the reliability of the memory cell 202.
值得注意的是，本實施例之各個驗證電壓以及寫入電壓僅為一示範性的實施例，實際應用上並不以此為限，且用以劃分記憶胞202之臨界電壓的驗證電壓亦不限於第二驗證電壓與第三驗證電壓兩個，使用者可依實際情形設計更多個驗證電壓，以將記憶胞202的臨界電壓值劃分為更多個區間，並設計更多個與各個區間對應的寫入電壓。It should be noted that the verification voltage and the write voltage of the embodiment are only an exemplary embodiment, and the practical application is not limited thereto, and the verification voltage for dividing the threshold voltage of the memory cell 202 is not Limited to the second verification voltage and the third verification voltage, the user can design more verification voltages according to the actual situation, to divide the threshold voltage value of the memory cell 202 into more intervals, and design more and each interval. Corresponding write voltage.
圖6繪示為本發明另一實施例之快閃記憶體的記憶胞寫入方法流程圖。請參照圖6，本實施例之快閃記憶體的記憶胞寫入方法與圖4的不同之處在於，本實施例在步驟S402判斷出臨界電壓小於第二驗證電壓後，寫入電壓控制單元206接著改為判斷臨界電壓是否小於等於第三驗證電壓(步驟S602)。若臨界電壓小於等於第三驗證電壓，將寫入電壓調整為第二寫入電壓(步驟S408)，若臨界電壓大於第三驗證電壓，則將寫入電壓調整為第三寫入電壓(步驟S410)。值得注意的是，在本實施例中第三寫入電壓為大於第一寫入電壓且小於第二寫入電壓。如此亦可針對具有不同臨界電壓的記憶胞202給予不同的寫入電壓，進而確保各個記憶胞202皆能正確地寫入資料，同時並提高產品的良率、減少汲極干擾、降低寫入電流、增加記憶胞202的耐久度及可靠度。6 is a flow chart of a method for writing a memory cell of a flash memory according to another embodiment of the present invention. Referring to FIG. 6, the memory cell writing method of the flash memory of this embodiment is different from that of FIG. 4 in that the present embodiment determines that the threshold voltage is less than the second verification voltage in step S402, and writes the voltage control unit. 206 then changes to determine whether the threshold voltage is less than or equal to the third verification voltage (step S602). If the threshold voltage is less than or equal to the third verification voltage, the write voltage is adjusted to the second write voltage (step S408), and if the threshold voltage is greater than the third verification voltage, the write voltage is adjusted to the third write voltage (step S410) ). It should be noted that in the embodiment, the third write voltage is greater than the first write voltage and less than the second write voltage. Therefore, different write voltages can be given to the memory cells 202 having different threshold voltages, thereby ensuring that each memory cell 202 can correctly write data, and at the same time, improve product yield, reduce buckling interference, and reduce write current. Increase the durability and reliability of the memory cell 202.
圖7繪示為本發明另一實施例之快閃記憶體的記憶胞寫入方法流程圖。請參照圖7，本實施例之快閃記憶體的記憶胞寫入方法與圖4的不同之處在於，圖4為由大的驗證電壓至小的驗證電壓依序比較臨界電壓與驗證電壓間的大小以決定寫入電壓值，而圖7則為由小的驗證電壓至大的驗證電壓依序比較臨界電壓與驗證電壓間的大小來決定寫入電壓值。FIG. 7 is a flow chart of a method for writing a memory cell of a flash memory according to another embodiment of the present invention. Referring to FIG. 7, the memory cell writing method of the flash memory of this embodiment is different from that of FIG. 4 in that FIG. 4 compares the threshold voltage and the verify voltage sequentially from a large verify voltage to a small verify voltage. The size determines the write voltage value, and Figure 7 determines the write voltage value by sequentially comparing the threshold voltage to the verify voltage from a small verify voltage to a large verify voltage.
如圖7所示，在偵測出記憶胞202的寫入結果後，寫入電壓控制單元206判斷記憶胞202的臨界電壓是否小於等於一第二驗證電壓(步驟S702)。若臨界電壓小於等於第二驗證電壓，則寫入電壓控制單元206將寫入電壓調整為第一寫入電壓(步驟S704)。若臨界電壓大於第二驗證電壓，則寫入電壓控制單元206繼續判斷臨界電壓是否小於等於一第三驗證電壓(步驟S706)。若臨界電壓小於等於第三驗證電壓，則寫入電壓控制單元206將寫入電壓調整為一第二寫入電壓(步驟S708)。若臨界電壓大於第三驗證電壓，寫入電壓控制單元206將寫入電壓調整為一第三寫入電壓(步驟S710)。其中第一驗證電壓大於第二驗證電壓且小於第三驗證電壓，而第二寫入電壓小於第一寫入電壓且大於第三寫入電壓。As shown in FIG. 7, after detecting the writing result of the memory cell 202, the write voltage control unit 206 determines whether the threshold voltage of the memory cell 202 is less than or equal to a second verification voltage (step S702). If the threshold voltage is less than or equal to the second verification voltage, the write voltage control unit 206 adjusts the write voltage to the first write voltage (step S704). If the threshold voltage is greater than the second verification voltage, the write voltage control unit 206 continues to determine whether the threshold voltage is less than or equal to a third verification voltage (step S706). If the threshold voltage is less than or equal to the third verification voltage, the write voltage control unit 206 adjusts the write voltage to a second write voltage (step S708). If the threshold voltage is greater than the third verification voltage, the write voltage control unit 206 adjusts the write voltage to a third write voltage (step S710). The first verification voltage is greater than the second verification voltage and less than the third verification voltage, and the second write voltage is less than the first write voltage and greater than the third write voltage.
如此亦可對臨界電壓較小的記憶胞202給予較高的寫入電壓，而臨界電壓較大的記憶胞202則給予較低的寫入電壓，進而減低製程差異對寫入操作時所造成的影響。Therefore, the memory cell 202 having a smaller threshold voltage can be given a higher write voltage, and the memory cell 202 having a larger threshold voltage is given a lower write voltage, thereby reducing the process difference caused by the write operation. influences.
圖8繪示為本發明另一實施例之快閃記憶體的記憶胞寫入方法流程圖。請參照圖8，本實施例之快閃記憶體的記憶胞寫入方法與圖7的不同之處在於，本實施例在步驟S702判斷出臨界電壓小於第二驗證電壓後，寫入電壓控制單元206接著改為判斷臨界電壓是否大於等於第三驗證電壓(步驟S802)。若臨界電壓大於等於第三驗證電壓，將寫入電壓調整為第二寫入電壓(步驟S708)，若臨界電壓小於第三驗證電壓，則將寫入電壓調整為第三寫入電壓(步驟S710)。值得注意的是，在本實施例中第三寫入電壓為小於第一寫入電壓且大於第二寫入電壓。如此亦可對臨界電壓較小的記憶胞202給予較高的寫入電壓，而臨界電壓較大的記憶胞202則給予較低的寫入電壓，進而減低製程差異對寫入操作時所造成的影響。FIG. 8 is a flow chart of a method for writing a memory cell of a flash memory according to another embodiment of the present invention. Referring to FIG. 8, the memory cell writing method of the flash memory of the present embodiment is different from that of FIG. 7 in that the present embodiment determines that the threshold voltage is less than the second verification voltage in step S702, and writes the voltage control unit. 206 then determines whether the threshold voltage is greater than or equal to the third verification voltage (step S802). If the threshold voltage is greater than or equal to the third verification voltage, the write voltage is adjusted to the second write voltage (step S708), and if the threshold voltage is less than the third verification voltage, the write voltage is adjusted to the third write voltage (step S710) ). It should be noted that in the embodiment, the third write voltage is less than the first write voltage and greater than the second write voltage. Therefore, the memory cell 202 having a smaller threshold voltage can be given a higher write voltage, and the memory cell 202 having a larger threshold voltage is given a lower write voltage, thereby reducing the process difference caused by the write operation. influences.
圖9繪示為本發明另一實施例之快閃記憶體的記憶胞寫入方法流程圖。請參照圖9。本實施例之記憶胞寫入方法與圖4實施例之記憶胞寫入方法的不同之處在於，本實施例的記憶胞寫入方法為先同時分別判斷記憶胞202的臨界電壓是否大於等於第二驗證電壓與第三驗證電壓(步驟S902)。然後再依據臨界電壓與第二驗證電壓以及第三驗證電壓的比較結果調整寫入電壓(步驟S904)。其中當臨界電壓大於等於第二驗證電壓以及第三驗證電壓時，將寫入電壓調整為一第一寫入電壓；當臨界電壓大於等於第三驗證電壓且小於第二驗證電壓時，將寫入電壓調整為一第二寫入電壓；當臨界電壓小於第二驗證電壓以及第三驗證電壓時，將寫入電壓調整為一第三寫入電壓，其中第二寫入電壓大於第一寫入電壓且小於第三寫入電壓。FIG. 9 is a flow chart of a method for writing a memory cell of a flash memory according to another embodiment of the present invention. Please refer to Figure 9. The memory cell writing method of the embodiment is different from the memory cell writing method of the embodiment of FIG. 4 in that the memory cell writing method of the embodiment first determines whether the threshold voltage of the memory cell 202 is greater than or equal to the first. The second verification voltage and the third verification voltage (step S902). Then, the write voltage is adjusted according to the comparison result of the threshold voltage with the second verification voltage and the third verification voltage (step S904). When the threshold voltage is greater than or equal to the second verification voltage and the third verification voltage, the write voltage is adjusted to a first write voltage; when the threshold voltage is greater than or equal to the third verification voltage and less than the second verification voltage, the write voltage is written. The voltage is adjusted to a second write voltage; when the threshold voltage is less than the second verify voltage and the third verify voltage, the write voltage is adjusted to a third write voltage, wherein the second write voltage is greater than the first write voltage And less than the third write voltage.
在本實施例中，依據臨界電壓與第二驗證電壓以及第三驗證電壓的比較結果調整寫入電壓的電路可利用邏輯閘來實現，舉例來說，當臨界電壓大於等於第二驗證電壓時，將臨界電壓與第二驗證電壓的比較結果設為"1"，而當臨界電壓小於第二驗證電壓時，將臨界電壓與第二驗證電壓的比較結果設為"0"，類似地，當臨界電壓大於等於第三驗證電壓時，將臨界電壓與第三驗證電壓的比較結果設為"1"，而當臨界電壓小於第三驗證電壓時，將臨界電壓與第二驗證電壓的比較結果設為"0"。如此一來，寫入電壓控制單元206便可依據依據臨界電壓與第二驗證電壓以及第三驗證電壓的比較結果調整寫入電壓，亦即在比較結果為"11"時將寫入電壓調整為第一寫入電壓，在比較結果為"10"時將寫入電壓調整為第二寫入電壓，而在比較結果為"00"時將寫入電壓調整為第三寫入電壓。In this embodiment, the circuit for adjusting the write voltage according to the comparison result of the threshold voltage and the second verification voltage and the third verification voltage may be implemented by using a logic gate. For example, when the threshold voltage is greater than or equal to the second verification voltage, The comparison result of the threshold voltage and the second verification voltage is set to "1", and when the threshold voltage is smaller than the second verification voltage, the comparison result of the threshold voltage and the second verification voltage is set to "0", similarly, when critical When the voltage is greater than or equal to the third verification voltage, the comparison result of the threshold voltage and the third verification voltage is set to "1", and when the threshold voltage is less than the third verification voltage, the comparison result of the threshold voltage and the second verification voltage is set to "0". In this way, the write voltage control unit 206 can adjust the write voltage according to the comparison result of the threshold voltage and the second verification voltage and the third verification voltage, that is, when the comparison result is “11”, the write voltage is adjusted to The first write voltage adjusts the write voltage to the second write voltage when the comparison result is "10", and adjusts the write voltage to the third write voltage when the comparison result is "00".
綜上所述，本發明藉由偵測快閃記憶體的記憶胞的寫入結果，並依據記憶胞的寫入結果對具有不同臨界電壓的記憶胞給予不同的寫入電壓，以減少製程差異在寫入操作時所造成的影響，同時並確保各個記憶胞皆能正確地寫入資料，達到提高產品的良率、減少汲極干擾、降低寫入電流、增加記憶胞的耐久度及可靠度等改善目的。In summary, the present invention reduces the difference in process by detecting the writing result of the memory cell of the flash memory and applying different writing voltages to the memory cells having different threshold voltages according to the writing result of the memory cell. The impact of the write operation, while ensuring that each memory cell can correctly write data, to improve product yield, reduce buckling interference, reduce write current, increase memory cell durability and reliability Wait for improvement purposes.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
102、104、202．．．記憶胞102, 104, 202. . . Memory cell
200．．．快閃記憶體200. . . Flash memory
204．．．寫入驗證單元204. . . Write verification unit
206．．．寫入電壓控制單元206. . . Write voltage control unit
SL．．．源極線SL. . . Source line
BL．．．位元線BL. . . Bit line
CL．．．控制線CL. . . Control line
WL．．．字元線WL. . . Word line
ST．．．選擇電晶體ST. . . Select transistor
MT．．．記憶電晶體MT. . . Memory transistor
S302~S306、S402~S410、S602、S702~S710、S S802、S902~904．．．記憶胞寫入方法步驟S302~S306, S402~S410, S602, S702~S710, S S802, S902~904. . . Memory cell writing method steps
圖1繪示為一習知之快閃記憶體的記憶胞陣列示意圖。FIG. 1 is a schematic diagram of a memory cell array of a conventional flash memory.
圖2繪示為本發明一實施例之快閃記憶體的示意圖。2 is a schematic diagram of a flash memory according to an embodiment of the invention.
圖3繪示為本發明一實施例之快閃記憶體的記憶胞寫入方法流程圖。3 is a flow chart of a method for writing a memory cell of a flash memory according to an embodiment of the invention.
圖4繪示為本發明另一實施例之快閃記憶體的記憶胞寫入方法流程圖。4 is a flow chart of a method for writing a memory cell of a flash memory according to another embodiment of the present invention.
圖5A繪示為習知之記憶胞寫入方法的汲極干擾示意圖。FIG. 5A is a schematic diagram showing the bungee interference of the conventional memory cell writing method.
圖5B繪示為利用本發明實施例之記憶胞寫入方法改善汲極干擾的示意圖。FIG. 5B is a schematic diagram of improving the drain interference by using the memory cell writing method of the embodiment of the present invention.
圖6~圖9繪示為本發明實施例之快閃記憶體的記憶胞寫入方法流程圖。6 to 9 are flowcharts showing a method for writing a memory cell of a flash memory according to an embodiment of the present invention.
S302~S306．．．記憶胞寫入方法步驟S302~S306. . . Memory cell writing method steps
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100137696A TWI480879B (en) | 2011-10-18 | 2011-10-18 | Flash memory and memory cell programming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100137696A TWI480879B (en) | 2011-10-18 | 2011-10-18 | Flash memory and memory cell programming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201317992A TW201317992A (en) | 2013-05-01 |
| TWI480879B true TWI480879B (en) | 2015-04-11 |
Family
ID=48872007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100137696A TWI480879B (en) | 2011-10-18 | 2011-10-18 | Flash memory and memory cell programming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI480879B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI307099B (en) * | 2005-05-27 | 2009-03-01 | Hynix Semiconductor Inc | Flash memory device being programmed and verified using voltage higher than target/read threshold voltage to achieve unifrom threshold voltage characteristic |
-
2011
- 2011-10-18 TW TW100137696A patent/TWI480879B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI307099B (en) * | 2005-05-27 | 2009-03-01 | Hynix Semiconductor Inc | Flash memory device being programmed and verified using voltage higher than target/read threshold voltage to achieve unifrom threshold voltage characteristic |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201317992A (en) | 2013-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9704596B1 (en) | Method of detecting erase fail word-line in non-volatile memory device | |
| KR101903842B1 (en) | Dynamic erase depth for improved endurance of non-volatile memory | |
| US7495966B2 (en) | Memory voltage cycle adjustment | |
| TWI591636B (en) | Defective word line detection | |
| CN106504789B (en) | Storage device and operation method thereof | |
| US9785493B1 (en) | Data recovery method after word line-to-word line short circuit | |
| KR102192910B1 (en) | Semiconductor device and memory system and operating method thereof | |
| US20190088333A1 (en) | Memory system | |
| US9318203B2 (en) | Semiconductor device being capable of improving program speed and program disturbance characteristics | |
| WO2014039164A1 (en) | On chip dynamic read level scan and error detection for non-volatile storage | |
| US9330771B2 (en) | Semiconductor device | |
| US8144516B2 (en) | Dynamic pass voltage for sense operation in a memory device | |
| US20140185381A1 (en) | Semiconductor apparatus and method of operating the same | |
| KR102491133B1 (en) | Memory device and operating method thereof | |
| US8942048B2 (en) | Semiconductor device and method of operating the same | |
| US20140063971A1 (en) | Semiconductor device and method of operating the same | |
| US8526240B2 (en) | Flash memory and memory cell programming method thereof | |
| US8140778B1 (en) | Apparatus and method for data capture using a read preamble | |
| CN112614526B (en) | Erase verification method for semiconductor device and semiconductor device | |
| KR20110132767A (en) | Non volatile memory device, precharge voltage controlling method thereof, and devices having the same | |
| US20160267999A1 (en) | Semiconductor memory device and memory system | |
| JP2020047321A (en) | Semiconductor storage device | |
| US10297338B2 (en) | Memory system | |
| TWI480879B (en) | Flash memory and memory cell programming method thereof | |
| US20130314989A1 (en) | Memory system |