TWI480758B - Method for conjecturing effective width and effective length of gate - Google Patents

Description

Method for estimating gate effective width and gate effective length

The present invention relates to a method of estimating the effective width of a gate and the effective length of a gate. In particular, the present invention relates to a method for estimating a gate effective width and a gate effective length by estimating a gate channel capacitance value and an edge capacitance value and then optimizing the predicted width error and length error.

Gold oxide half field effect transistors (MOSFETs) are an important semiconductor component commonly produced using standard semiconductor processes. When using a semiconductor process, various parts of the MOS half-effect transistor, such as the source, drain, and gate, are gradually built up according to the designed component specifications. Among them, the effective gate width (Weff) and the effective gate length (Leff) related to the electrical properties of the MOS field-effect transistor are an important inspection item because the gate is effective. The width and effective gate length have a profound and extensive impact on component performance and process development.

Although in the semiconductor process, the various parts of the MOS field-effect transistor, such as the gate, are gradually established according to the designed component specifications, but the actual gate size in the finished die, or The effective width of the gate and the effective length of the gate are different, but the process variations are not the same as the designed component specifications. Strictly speaking, because the influence on the development of the process is more specific, the effective gate width and the effective gate length of the gate are actually much more important than the gate width (physical width) and the gate body length.

The current method of determining gate width and gate length is to use a tunneling electron microscope (TEM). This is not a perfect method. On the one hand, the results are not reliable due to the limited number of samples and manual visual inspection. On the other hand, the result obtained is only limited to the gate body width and the gate body length on the process, and does not actually reflect the electrical effective gate effective width and gate effective length.

Unfortunately, there is currently no way to determine the effective width of the gate and the effective length of the gate. Therefore, how to estimate the effective width of the gate and the effective length of the gate is a key issue that is important to promote the progress of the semiconductor process.

The present invention is directed to a method of determining the gate effective size, i.e., the effective width of the gate and the effective length of the gate. After calculating the intrinsic capacitance value and the inherent edge capacitance value of the gate channel, and then calculating the width error value and the length deviation value to optimize the predicted width error and length error, a design gate can be inferred. The effective width of the gate and the effective length of the gate. In one embodiment of the method of the present invention, the design gates may also include a plurality of distinct gate design widths or gate design lengths. Therefore, when predicting a group width error or a group length error, a prediction group width error or a prediction group width error suitable for all gate design widths or all gate design lengths can be obtained. These predicted group width errors or predicted group width errors are very helpful in predicting the gate effective length of an unknown design gate size, or the effective width of the gate.

The present invention therefore proposes a method for estimating the effective width of a gate and the effective length of a gate. First, a design gate set is provided that includes a gate design size, such as a first gate design width and a first gate design length. Next, a first measurement inversion capacitance value of the first design gate at a reverse voltage is measured to calculate a gate channel capacitance value of the first design gate. Thereafter, a value of one of the zero values of the first design gate at a gate voltage of zero is measured to calculate an edge capacitance value of the gate. Continuing, a first width error is predicted via the gate channel capacitance value and the edge capacitance value, and a first width calculation inversion capacitance value and a predicted first width deviation value are calculated. Next, the first width error is repeatedly predicted to minimize the predicted first width deviation value and optimize the predicted first width error to obtain an optimized first width error. Alternatively, a first length error is predicted via the gate channel capacitance value and the edge capacitance value, and a first length calculation inversion capacitance value and a predicted first length deviation value are calculated. The first length error is then overlaid to minimize the predicted first length deviation value and to optimize the predicted first length error to obtain an optimized first length error. Then, the gate effective width and the gate effective length are estimated by the optimized first width error and the optimized first length error.

In one embodiment of the method of the present invention, the design gates may also include a plurality of distinct gate design widths or gate design lengths. Therefore, a group width error or a group length error is predicted, and a prediction group width error or a prediction group length error suitable for all gate design widths or all gate design lengths can be obtained. In another embodiment of the method of the present invention, the predicted group width error or the predicted group length error may be additionally used to predict the gate effective length of a given design gate size, or the gate is effective. width.

The method for estimating the effective width of the gate and the effective length of the gate provided by the invention can be used to design the gate from the known physical width and the physical length, and determine the gate effective width and the effective gate length of the gate. . If the design gates comprise a plurality of different gate design widths or gate design lengths, it is also possible to predict a group width error or a group length error, thus obtaining a width suitable for all gate designs or The predicted group width error of all gate design lengths or the predicted group length error. On the other hand, the resulting predicted group width error or predicted group length error is also very helpful in predicting the gate effective length of the unknown design gate size, or the gate effective width.

Fig. 1A/1B is a view showing a method of estimating the effective width of the gate and the effective length of the gate of the present invention. For a design gate 101, it has a specific design length 110 (design length. L _des ) and a design width 120 (design width, W _des ). The design length 110 and the design width 120 are the ideal lengths/widths calculated from the simulation to achieve a particular electrical demand, which does not account for variations and errors in the process. As described above, the design gate 101 exhibits an electrical gate effective length and a gate effective width, but may be different from the designed design length 110 and the design width 120 due to process variations and error relationships. The following equation can be used to represent the gate effective width (W _eff ) and the gate effective length (L _eff ):

C _inv =L _eff *W _eff *C _A *N+2*C _edge *W _eff *N

C _inv = reverse capacitance value

C _A = gate channel capacitance

C _edge = edge capacitance value

N = number of gates

If the inversion capacitance value (C _inv ), the gate channel capacitance value (C _A ), and the edge capacitance value (C _edge ) are obtained, the gate effective width (W _eff ) can be estimated when the gate number is known. Effective length with gate (L _eff ).

First, as shown in FIG. 1A, a first design gate 101 is provided, which includes a first gate design length 110 and a first gate design width 120, but the gate effective width and the gate effective length are unknown. . In one embodiment of the method of the present invention, a plurality of design gate sets 101' of a plurality of distinct design gates 102 can also be provided, as shown in FIG. 1B. The design gate set 101' then includes a plurality of distinct gate design widths ( _Wdes ) or gate design lengths ( _Ldes ).

Secondly, when the design dimensions of the gate, such as the gate design width (W _des ) and the gate design length (L _des ) are large enough, the design size and the effective size, ie the gate effective width (W _eff ) and the gate are effective. The error between lengths (L _eff ) is negligible. In addition, when the gate design width (W _des ) and the gate design length (L _des ) are sufficiently large, the capacitance value (C _f ) of the gate and source 103, the gate and the drain are at a reverse voltage. The capacitance value (C _f ) of 103 and the edge capacitance value (C _edge = C _f + C _ov ) and the gate effective width (W _eff ) of the gate and the capacitance value (C _ov ) of the lightly doped drain 104 The product of the product (ie C _edge *W _eff ) compared to the gate channel capacitance value (C _A ), the gate effective length (L _eff ) and the gate effective width (W _eff ) (ie C _A *L _eff *W _Eff can also be ignored, so that the measured reverse capacitance value (C _minv ) of the first design gate 101 at a reverse voltage can be measured to calculate the gate channel capacitance of the first design gate 101 ( C _A ).

2*C _edge *W _eff *N<<L _eff *W _eff *C _A *N

C _minv =L _eff *W _eff *C _A *N

C _A =(C _minv )/(L _des *W _des *N)

example:

Gate design width (W _des )=9μm

Gate design length (L _des )=9μm

Number of gates (N)=1

Measuring reverse capacitance value (C _minv )=1.377E+03fF

Gate channel capacitance value (C _A )=1.70E+01 (fF/μm ² )

Also, when the gate voltage is zero (V _g =0), the gate has no channel capacitance value (C _A ). Moreover, when the design size of the gate is large enough, the error between the design size and the effective size can be neglected, so that the zero value capacitance value of the first design gate 101 when the gate voltage is zero can be measured (C). _Vg ) to calculate the edge capacitance value (C _edge ) of one of the gates.

L _eff *W _eff *C _A *N=0

C _vg =2*C _edge *W _des *N

C _edge =C _vg /(2*W _des *N)

example:

Gate design width (W _des )=9μm

Gate design length (L _des )=0.036μm

Number of gates (N)=1

Zero value capacitance value (C _vg ) = 4.41fF

Edge capacitance value (C _edge ) = 2.45E-01 (fF / μm)

Next, after actually measuring the inversion capacitance value (C _inv ) and calculating the gate channel capacitance value (C _A ) and the edge capacitance value (C _edge ), it is ready to start estimating the effective gate width (W). _Eff ) and gate effective length (L _eff ). Because, in fact, there should be an error between the gate design width (W _des ) and the gate effective width (W _eff ), so the gate effective width (W _eff ) is assumed to be the gate design width (W _des ) Add a width error (ΔW). For the first design gate 101:

W _eff = W _des + ΔW

Similarly, the gate effective length (L _eff ) is the gate design length (L _des ) plus a length error (ΔL):

L _eff =L _des +ΔL

Continuing, the prediction of the first width error is initiated via the previously obtained gate channel capacitance value (C _A ) and edge capacitance value (C _edge ). For the sake of convenience, the gate effective length (L _eff ) can be temporarily represented by the gate design length (L _des ), that is, ΔL=0 can be assumed first. For example, the arbitrary guess width error (ΔW) is the first width error (ΔW ₁ ), and a first width calculation inversion capacitance value (C _cwinv1 ) and a predicted first width deviation value (EW ₁ ) are calculated.

C _cwinv1 =L _des *(W _des +ΔW ₁ )*C _A *N+2*C _edge *(W _des +ΔW ₁ )*N

The size deviation values defined here are:

E=(C _cwinv /C _minv )-1

Therefore, the first width deviation value is:

EW ₁ =(C _cwinv1 /C _minv )-1={[L _des *(W _des +ΔW ₁ )*C _A *N+2*C _edge *(W _des +ΔW1)*N]/C _minv }- 1

Among them, L _des , W _des , ΔW ₁ , C _A , N, C _edge , and C _minv are all known.

Next, it is desirable that the first width deviation value (EW ₁ ) can be minimized. In other words, it is desirable to optimize the first width error (ΔW ₁ ) such that the predicted first width calculates the inverse capacitance value (C _cwinv1 ) As close as possible to the first measurement inversion capacitance value (C _minv ). The operation method may be, for example, using a plurality of sets of different width errors (ΔW), such as ΔW ₁ , ΔW ₂ , ΔW ₃ ... ΔW _n , and repeatedly calculating the first width deviation value (EW ₁ ), wherein there must be a A certain width error (ΔW _ox ) that minimizes the width deviation value (EW ₁ ). Thus, the optimum width error (ΔW _ox ) can be considered as the first width error (ΔW _ox ) optimized in the first stage.

On the other hand, a similar procedure can also be used to predict the first length error (ΔL ₁ ). For example, the arbitrary guess length error (ΔL) is the first length error (ΔL ₁ ), and a first length calculated inversion capacitance value (C _clinv1 ) and a predicted first length deviation value (EL ₁ ) are calculated. For the sake of convenience, the gate effective width (W _eff ) can be temporarily represented by the gate design length (W _des ), that is, ΔW=0 can be assumed first.

L _eff =L _des +ΔL

C _clinv1 = (L _des + ΔL) * W _des * C _A * N + 2 * C _edge * W _des * N

EL ₁ =(C _clinv1 /C _minv )-1={[(L _des +ΔL)*W _des *C _A *N+2*C _edge *W _des *N]/C _minv }-1

Also, it is desirable that the first length deviation value (EL ₁ ) can be minimized, in other words, it is desirable to optimize the first length error (ΔL ₁ ) such that the predicted first length calculates the inverse capacitance value ( C _clinv1 ) as close as possible to the first measured inversion capacitance value (C _minv ). A plurality of different length errors (ΔL), such as ΔL ₁ , ΔL ₂ , ΔL ₃ ... ΔL _n , may be used to repeatedly calculate a first length deviation value (EL ₁ ), wherein there must be a first length deviation value ( EL ₁ ) minimizes one of the best length errors (ΔL _ox ). Thus, this optimal length error (ΔL _ox ) can be considered as the first length error (ΔL _ox ) optimized in the first stage.

When the first width error (ΔW _ox ) is optimized and the first length error (ΔL _ox ) is optimized in the first stage, the first length error (ΔL) optimized at that time can be reused. _Ox ) to assist in the prediction of the width error (ΔW) or, on the other hand, to assist in the prediction of the length error (ΔL) using the then optimized first width error (ΔW _ox ). For example, when again guessing that the length error (ΔL) is the first length error (ΔL ₁ ), the previously obtained first width error (ΔW _ox ) is used as the basis for the current gate effective width (W _eff ). ,which is:

W _eff = W _des + ΔW _ox .

When it is again guessed that the width error (ΔW) is the first width error (ΔW ₁ ), the previously obtained optimized first length error (ΔL _ox ) can also be used as the current gate effective length (L _eff ). Foundation, namely:

L _eff = L _des + ΔL _ox .

On the one hand, the gate channel capacitance value (C _A ) is independent of the change in width error (ΔW) and length error (ΔL). On the other hand, the edge capacitance value (C _edge ) is also independent of the change in the width error (ΔW) and the length error (ΔL), so the gate channel capacitance value (C _A ) and the edge capacitance value (C _edge ) can be excluded from Outside the guessing process of the effective width of the gate and the effective length of the gate.

In this way, the predicted width error (ΔW) is continuously assisted by the optimized first length error (ΔL _ox ), and the predicted length error (ΔL) is continuously assisted by the optimized first width error (ΔW _ox ). After a plurality of repeated operations, when the dimensional deviation value is reduced to an acceptable range, for example, in the range of 1% or 0.1%, it can be considered that the required gate effective width is estimated ( W _eff ) and gate effective length (L _eff ), and the optimized width error (ΔW _o ) and the optimized length error (ΔL _o ).

In one embodiment of the method of the present invention, the design gate set 101' can also provide a plurality of distinct design gates 102, as shown in FIG. 1B. The different design gates 102 will each have a plurality of distinct gate design widths ( _Wdes ) or gate design lengths ( _Ldes ). In the method for estimating the gate effective width and the effective gate length of the present invention, it is also desirable to find a group width error (ΔW _G ), and simultaneously describe a plurality of different gate design widths of the same gate design length ( W _des ), preferably, can simultaneously describe all of the different gate design widths (W _des ) in the design gate set 101'. Similarly, the present invention also contemplates finding a group length error (ΔL _G ) that simultaneously describes a plurality of distinct gate design lengths (L _des ) of the same gate design width. Preferably, the design can be described simultaneously. All different gate design lengths (L _des ) in the gate set 101'.

For example, the different design gates 102 have three different sets of gate design lengths (L _des ), referred to as L _des α, L _des β, and L _des γ, respectively. First guess a group length error (ΔL _G ) as the first group length error (ΔL _G1 ), and calculate the first group length calculation inversion capacitance belonging to L _des α, L _des β and L _des γ respectively. The value (C _clginv1 ) is predicted from the first group length deviation value (EL _G1 ). For the sake of convenience, the gate effective width (W _eff ) can be represented by the gate design length (W _des ), that is, the group width error ΔW _G =0 can be assumed first.

L _eff α=L _des α+ΔL _G1

L _eff β=L _des β+ΔL _G1

L _eff γ=L _des γ+ΔL _G1

C _cαlginv1 =(L _des α+ΔL _G1 )*W _des α*C _A *N+2*C _edge *W _des α*N

EL _Gα1 =(C _cαlinv1 /C _minv )-1

Next, an attempt is made to find a first group length error (ΔL _G1 ) such that EL _Gα1 , EL _Gβ1 and EL _{Gγ1 are} minimized. For example, computing _EL Gα1, EL Gβ1, EL Gγ1 the root mean square (square root) minimum, so considered _EL Gα1, EL Gβ1, ELGγ1 best minimize the length of the first group of error (ΔL _Go1). Similarly, regarding the group width error (ΔW _G ), the first group width calculation inversion capacitance value (C _cwginv1 ) and the first prediction group width deviation value (EW _G1 ) can be calculated in a similar manner, thereby finding the most The first group width error (ΔLW _o1 ).

As mentioned before, when the first group length error (ΔL _Go1 ) and the optimized first group width error (ΔL _Wo1 ) are obtained in the previous stage, the optimization can be reused. The first group length error (ΔL _Go1 ) to assist in predicting the group width error (ΔW _G ), or, on the other hand, using the optimized first group width error (ΔL _Wo1 ) to assist the group length Prediction of the error (ΔL _G ). In this way, the predicted group width error (ΔW _G ) is continuously assisted by the optimized group length error (ΔL _Go ), and the predicted group is continuously assisted by the optimized group width error (ΔL _Wo ). The length error (ΔL _G ), after a plurality of repeated optimization operations, when the width or length dimension deviation value is reduced to an acceptable range, for example, in the range of 1% or 0.1%, It can be considered that the required gate effective width (W _eff ) and gate effective length (L _eff ) are estimated, and the optimized group width error (ΔW _Go ) and the optimized group length error are obtained ( ΔL _Go ).

example:

Gate design length (L _des )=0.036μm

Gate design width group (W _des )=9,0.45,0.108μm

Optimized group length error (ΔL _Go )=-0.0094μm

Group length deviation value (E _LG1 )

Due to the previously obtained optimized group width error (ΔW _Go ) or the optimized group length error (ΔL _Go ), for the design of the gate group 101', a plurality of, preferably all, phases The size of the differently designed gate 102, such as width or length, is considered to be optimal, and further, the resulting optimized group width error (ΔW _Go ) or optimized group length error (ΔL _Go ) can also be considered to be optimal in the size range of the distinct design gate 102.

In yet another embodiment of the method of the present invention, a dimension equation relating to width or length can also be found. These dimensional equations can essentially describe a plurality of distinct gate designs that are related in size to the optimized group size error. In this way, the use of these dimensional equations makes it possible to predict the gate effective width of a given design gate size, or the gate effective length.

For example, the different design gates have three different gate design widths, such as 9, 0.45, 0.108. After the above steps, the corresponding optimized group width errors are respectively found, namely (9, -0.05), (0.45, -0.0133), (0.108, 0.0035). Through the three sets of data, it is possible to find an equation that can satisfy the three sets of data conditions at the same time. If you can find more than one equation, it is better to have the smallest unknown power, for example:

ΔW=-0.0052W-0.0033

For the operation method of different gate design lengths, reference may be made to the foregoing. For example, (9, -0.0026), (0.9, -0.0174), (0.1, -0.0135), (0.036, -0.0094) can be:

ΔL=0.001L ² -0.0084L-0.0108

Therefore, it will not be repeated.

In still another embodiment of the method of the present invention, if a design gate having a known gate design width or a gate design length is given, the gate of the design gate can be derived according to the foregoing equation. Effective width, or effective gate length.

For example, if a design gate has a gate design length between 9 and 0.108, the previously obtained equation can be used to find the gate design length of the design gate by interpolation. The corresponding effective gate length. Similarly, a similar concept can be used to infer the gate effective width corresponding to the gate design width of the design gate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

101‧‧‧ Design gate

101’‧‧‧Design gate group

102‧‧‧Different design gates

103‧‧‧Source, bungee

104‧‧‧Lightly doped bungee

110‧‧‧Design length

120‧‧‧Design width

Fig. 1A/1B is a view showing a method of estimating the effective width of the gate and the effective length of the gate of the present invention.

101’. . . Design gate group

102. . . Different design gate

Claims (20)

A gate design method for estimating a gate effective width and a gate effective length by using a computer, comprising: providing a design gate including a first gate design width and a first gate design length; according to the following formula Make the following measurements: C _inv =L _eff *W _eff *C _A *N+2*C _edge *W _eff *N where C _inv = reverse capacitance value, C _A = gate channel capacitance value, C _edge = edge capacitance Value, N = gate number, L _eff = gate effective width, W _eff = gate effective length; measuring the first measured reverse capacitance value of the first design gate at a reverse voltage to calculate the a gate channel capacitance value of the first design gate; measuring a zero value capacitance value of the first design gate when a gate voltage is zero, to calculate an edge capacitance value of the first design gate; And calculating a first width error by using the gate channel capacitance value and the edge capacitance value, and calculating a first width calculation inversion capacitance value and a prediction first width deviation value; and repeatedly predicting the first width error to be the smallest The predicted first width deviation value is optimized and the first width error is optimized To optimize the first width error; predicting a first length error via the gate channel capacitance value and the edge capacitance value, and calculating a first length calculation inversion capacitance value and a prediction first length deviation value Overcoming the first length error to minimize the predicted first length deviation value and optimizing the first length error to obtain the first length error that is optimized; and the first The width error is optimized for the first length error, and the effective width of the gate and the effective length of the gate are inferred. The method of claim 1, wherein the gate channel capacitance value is independent of the first width error and the change in the first length error. The method of claim 1, wherein the edge capacitance value is independent of the first width error and the change in the first length error. The method of claim 1, wherein the edge capacitance value is related to a lightly doped drain capacitance value and a source/drain capacitance value of the design gate. The method of claim 1, wherein one of the first width error and the first length error is expected to be zero to facilitate prediction by the other one. The method of claim 1, wherein one of the first length error of the optimization and the first width error of the optimization is used to facilitate prediction by the other one. The method of claim 1, further comprising providing a plurality of distinct design gates, wherein the distinct design gates comprise a plurality of distinct gate design widths. The method of claim 7, further comprising: predicting a group width error, and calculating a group width calculation inversion capacitance value and a prediction group width deviation value; and repeatedly predicting the group width error to minimize The predicted group width deviation value of the plurality of distinct gate design widths is optimized and the group width error is optimized to obtain an optimized group width error. The method of claim 8, wherein the group width error is optimized to facilitate optimal prediction of a group length error. The method of claim 8, wherein a one-rooted method is used to determine the predicted group width deviation value of the plurality of distinct gate design widths. The method of claim 8, further comprising: providing a width equation substantially describing a relationship between the plurality of distinct gate design widths and the optimized group width error, wherein the width equation makes the prediction This gate effective width for a given design gate size is possible. The method of claim 11, wherein an interpolation method is used to estimate the gate effective width of the given design gate size via the width equation and the given design gate size. The method of claim 11, wherein the width equation has a minimum unknown power. The method of claim 1, wherein the design gate set comprises a plurality of distinct gate design lengths. The method of claim 14, further comprising: predicting a group length error, calculating a group length calculation inversion capacitance value and a prediction group length deviation value; and repeatedly predicting the group length error to minimize The predicted group length deviation value of the plurality of distinct gate design lengths is optimized, and the group length error is optimized to obtain an optimized group length error. The method of claim 15, wherein the optimized group length error is used to facilitate optimization of a group of width error errors. The method of claim 15, wherein the one-segment rooting method is used to determine the plurality of gate design lengths to minimize the predicted group length deviation value. The method of claim 15, further comprising: providing a length equation substantially describing a relationship between the plurality of gate design lengths and the optimized group length error, wherein the length equation causes the prediction to be given It is possible to design the effective length of the gate of the gate size. The method of claim 18, wherein an interpolation method is used to estimate the gate effective length of the given design gate size via the length equation and the given design gate size. The method of claim 18, wherein the length equation has a minimum unknown power.