TWI479610B - Non-volatile memory and manufacturing method thereof - Google Patents

Description

Non-volatile memory and method of manufacturing same

The present invention relates to a non-volatile memory (NVM) and a method of fabricating the same, and in particular to a second bit effect and a program disturbance. Non-volatile memory and its method of manufacture.

Non-volatile memory has the advantage that it does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical products when they are turned on.

A nitride-only read-only memory (ROM) is a commonly used non-volatile memory. In the memory cell of the nitride read-only memory, the data of the two-bit can be stored by the charge trapping structure composed of the nitride layer. In general, the two-bit data can be stored separately on the left side (ie, the left bit) or the right side (ie, the right bit) in the charge trapping structure.

However, there is a second bit effect in the nitride read-only memory, that is, when the left bit is read, it is affected by the right bit, or when the right bit is read, The influence of the left bit. In addition, as the size of the memory is gradually reduced, the length of the channel in the memory cell is also shortened, resulting in a more significant second bit effect, thus affecting the operation window and component performance.

In addition, as the size of the memory is gradually reduced, the spacing between the memory cells is also shortened, so that adjacent memory cells are prone to stylized interference when performing programmatic operations.

Embodiments of the present invention provide a method of fabricating a non-volatile memory that can produce non-volatile memory that can avoid second bit effects and stylized interference during operation.

Embodiments of the present invention further provide a non-volatile memory that avoids the generation of second bit effects and stylized interference during operation.

The invention provides a method for fabricating a non-volatile memory. In this method, a first oxide layer having protrusions is formed on the substrate, and a pair of doped regions are formed in the substrate on both sides of the protrusion. A pair of charge storage spacers are formed on sidewalls of the protrusions, and a second oxide layer is formed on the first oxide layer and the charge storage spacers, and a conductor layer is formed on the second oxide layer.

According to a method of fabricating a non-volatile memory according to an embodiment of the invention, the first oxide layer is formed by, for example, forming a first oxide material layer on a substrate. A patterned mask layer is then formed over the first oxide material layer. Next, a portion of the first oxide material layer is removed by patterning the mask layer as a mask to form protrusions. After that, the patterned mask layer is removed.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, after removing a portion of the first oxide material layer, the substrate on both sides of the protrusion is not exposed.

According to the method for fabricating a non-volatile memory according to the embodiment of the invention, after the forming of the protrusion and before removing the patterned mask layer, the method further comprises: patterning the mask layer as a mask for ion implantation. The process is to form a doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the charge storage spacers is, for example, conformally forming a charge storage material layer on the first oxide layer. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the charge storage spacers is, for example, conformally forming a charge storage material layer on the first oxide layer. Then, a second oxide material layer is formed on the charge storage material layer. Thereafter, an isotropic etching process is performed to remove a portion of the second oxide material layer and a portion of the charge storage material layer.

According to the method for fabricating a non-volatile memory according to the embodiment of the present invention, after the forming of the protrusion and before removing the patterned mask layer, the method further comprises forming a sidewall of the patterned mask layer and the protrusion. A pair of nitride spacers. Thereafter, an ion implantation process is performed by patterning the mask layer and the nitride spacer as a mask to form a doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the nitride spacer is simultaneously removed when the patterned mask layer is removed.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the charge storage spacers is, for example, conformally forming a charge storage material layer on the first oxide layer. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, after forming the doped region and before removing the patterned mask layer, the method further includes forming a third oxide layer to cover the patterned mask a layer, a nitride spacer and a first oxide layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for removing the patterned mask layer is, for example, performing a planarization process, removing the patterned mask layer, a portion of the nitride spacer and the portion. The third oxide layer is exposed until the protrusions are exposed and a charge storage spacer is formed.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, after removing a portion of the first oxide material layer, the substrate on both sides of the protrusion is exposed.

According to the method for fabricating a non-volatile memory according to the embodiment of the invention, after the forming of the protrusion and before removing the patterned mask layer, the method further comprises: patterning the mask layer as a mask for ion implantation. The process is to form a doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the charge storage spacer includes, for example, conformally forming a third oxide layer on the first oxide layer. Then, a charge storage material layer is conformally formed on the third oxide layer. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer.

The invention further provides a non-volatile memory comprising a substrate, a charge storage structure, a first doped region, a second doped region, and a gate. The charge storage structure is disposed on the substrate. The first doped region and the second doped region are respectively disposed in the substrate on both sides of the charge storage structure. The gate is disposed on the charge storage structure. The charge storage structure includes a dielectric body, a first charge storage spacer, and a second charge storage spacer. The first charge storage spacers are disposed in mirror symmetry with the second charge storage spacers in the dielectric body and are separated from each other. The first charge storage spacer is adjacent to the first doped region, and the second charge storage spacer is adjacent to the second doped region. The first charge storage spacer and the second charge storage spacer are respectively L-shaped, and the horizontal portion of the first charge storage spacer and the horizontal portion of the second charge storage spacer extend away from each other, or the first charge storage spacer The second charge storage spacers respectively have a curved surface or a sloped surface, and the curved surface or the inclined surface of the first charge storage spacer is away from the curved surface or the inclined surface of the second charge storage spacer.

According to the non-volatile memory of the embodiment of the present invention, the materials of the first charge storage spacer and the second charge storage spacer are, for example, nitride, polysilicon, high-k material, oxidation.铪 (Hf _x O _y ), yttrium oxynitride (HfO _x N _y ), alumina (Al _x O _y ) or yttrium aluminum oxide (Hf _x Al _y O _z ).

According to the non-volatile memory of the embodiment of the invention, the thickness of the first charge storage spacer and the second charge storage spacer is between 40 A and 80 A, for example.

Based on the above, the present invention utilizes a charge storage spacer formed on the sidewall of the oxide protrusion as a charge storage region, thereby effectively limiting the charge to the charge storage spacer, respectively, to avoid generation during a read operation. The second bit effect, and the problem of avoiding stylized interference when adjacent memory cells are programmed. In addition, the present invention can control the size of the charge storage spacer by adjusting the thickness of the charge storage material layer for forming the charge storage spacer to avoid causing the charge storage spacer to be too small in size to affect the memory storage charge.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

1A to 1D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a first embodiment of the present invention. First, referring to FIG. 1A, an oxide layer 102 having protrusions 102a is formed on a substrate 100. The oxide layer 102 is formed by, for example, forming an oxide material layer on the substrate 100. The method of forming the oxide material layer is, for example, a chemical vapor deposition method. A patterned mask layer 104 is then formed over the layer of oxide material. The patterned mask layer 104 covers the area of the oxide layer 102 where the protrusions are to be formed. Next, using the patterned mask layer 104 as a mask, an isotropic etching process is performed to remove a portion of the oxide material layer until the substrate 100 is exposed to form the protrusions 102a. In the present embodiment, since the oxide layer 102 not covered by the patterned mask layer 104 is removed, the remaining oxide layer 102 belongs to the protrusion 102a.

Then, referring to FIG. 1B, the ion mask process is performed by patterning the mask layer 104 as a mask to form the doping region 106 in the substrate 100 on both sides of the protrusion 102a (the oxide layer 102). Thereafter, the patterned mask layer 104 is removed.

Next, referring to FIG. 1C, an oxide layer 108 is conformally formed on the substrate 100. The method of forming the oxide layer 108 is, for example, a chemical vapor deposition method. The oxide layer 108 covers the protrusions 102a (oxide layer 102) and the doped regions 106. Then, a pair of charge storage spacers 110 are formed on the sidewalls of the protrusions 102a (oxide layer 102). The charge storage spacers 110 serve as charge storage regions in the subsequently formed memory. The charge storage spacer 110 is formed, for example, by conformally forming a charge storage material layer on the oxide layer 108. The material of the charge storage material layer is, for example, nitride, polycrystalline germanium, high dielectric constant material, cerium oxide, cerium oxynitride, aluminum oxide or cerium aluminum oxide. The method of forming the charge storage material layer is, for example, a chemical vapor deposition method. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer. As can be seen from the above, the size of the charge storage spacer 110 depends on the thickness of the charge storage material layer. In other words, the size of the charge storage spacers 110 can be controlled by adjusting the thickness of the charge storage material layer.

In the present embodiment, the thickness of the charge storage material layer is, for example, between 40 A and 80 A. As a result, after a voltage is applied to the formed memory, the charge can be efficiently stored and confined to the charge storage spacer 110. In addition, since the thickness of the charge storage material layer is between 40 A and 80 A, the size of the charge storage spacer 110 is not too small to affect the ability of the memory to store charges.

Thereafter, referring to FIG. 1D, an oxide layer 112 is formed on the oxide layer 108 and the charge storage spacers 110. The method of forming the oxide layer 112 is, for example, a chemical vapor deposition method. Then, a conductor layer 114 is formed on the oxide layer 112 to form the non-volatile memory 10. The method of forming the conductor layer 114 is, for example, a chemical vapor deposition method. The conductor layer 114 is, for example, a polysilicon layer.

The non-volatile memory 10 includes a plurality of memory cells as shown at the broken line, wherein the protrusions 102a (oxide layer 102), the oxide layer 108, the pair of charge storage spacers 110, and the oxide layer 112 constitute a charge storage structure. (The protrusion 102a, the oxide layer 108 and the oxide layer 112 may be collectively referred to as a dielectric body), and the doped regions 106 on both sides of the charge storage structure serve as a source region and a drain region, respectively, and the conductor layer 114 functions as Gate. In each of the memory cells, since the two charge storage spacers 110 are separated from each other, the charges can be effectively limited to the charge storage spacers 110 on the left side (ie, the left bit) and the charge storage spacers 110 on the right side ( That is, in the right bit), to avoid generating a second bit effect when a read operation is performed. In addition, since the electric charge is confined to the charge storage spacer 110, it is also possible to avoid the problem that stylized interference occurs when adjacent memory cells perform a program operation.

Second embodiment

2A to 2C are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a second embodiment of the present invention. First, referring to FIG. 2A, an oxide layer 202 having protrusions 202a is formed on the substrate 200. The oxide layer 202 is formed by, for example, forming an oxide material layer on the substrate 200. The method of forming the oxide material layer is, for example, a chemical vapor deposition method. A patterned mask layer 204 is then formed over the layer of oxide material. The patterned mask layer 204 covers the regions of the oxide layer 202 where the protrusions are to be formed. Next, using the patterned mask layer 204 as a mask, an isotropic etching process is performed to remove a portion of the oxide material layer without exposing the substrate 200 to form the protrusions 202a.

Then, referring to FIG. 2B, the ion mask process is performed by patterning the mask layer 204 as a mask to form a doping region 206 in the substrate 200 on both sides of the protrusion 202a. Next, the patterned mask layer 204 is removed. Thereafter, a pair of charge storage spacers 208 are formed on the sidewalls of the protrusions 202a. The charge storage spacers 208 serve as charge storage regions in the subsequently formed memory. The method of forming the charge storage spacers 208 is, for example, conformally forming a layer of charge storage material prior to the oxide layer 202. The material of the charge storage material layer is, for example, nitride, polycrystalline germanium, high dielectric constant material, cerium oxide, cerium oxynitride, aluminum oxide or cerium aluminum oxide. The method of forming the charge storage material layer is, for example, a chemical vapor deposition method. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer. As with the first embodiment, the size of the charge storage spacers 208 can be controlled by adjusting the thickness of the charge storage material layer. In the present embodiment, the thickness of the charge storage material layer is, for example, between 40 A and 80 A. In this way, the ability of the charge storage spacers 208 to be too small to affect the stored charge of the memory can be avoided.

Thereafter, referring to FIG. 2C, an oxide layer 210 is formed on the oxide layer 202 and the charge storage spacers 208. The method of forming the oxide layer 210 is, for example, a chemical vapor deposition method. Conductor layer 212 is then formed over oxide layer 210 to form non-volatile memory 20. The method of forming the conductor layer 212 is, for example, a chemical vapor deposition method. The conductor layer 212 is, for example, a polysilicon layer.

The non-volatile memory 20 includes a plurality of memory cells as shown at the broken line, wherein the oxide layer 202, the pair of charge storage spacers 208 and the oxide layer 210 constitute a charge storage structure (the oxide layer 202 and the oxide layer 210). The doped regions 206 on the two sides of the charge storage structure serve as the source region and the drain region, respectively, and the conductor layer 212 serves as a gate. Like the non-volatile memory 10, the second bit effect can be avoided when reading the memory cells of the non-volatile memory 20, and the adjacent memory cells can be prevented from generating programs during the stylization operation. The problem of interference.

Third embodiment

3A to 3D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a third embodiment of the present invention. First, referring to FIG. 3A, an oxide layer 302 having protrusions 302a is formed on the substrate 300. The oxide layer 302 is formed by, for example, forming an oxide material layer on the substrate 300. The method of forming the oxide material layer is, for example, a chemical vapor deposition method. A patterned mask layer 304 is then formed over the layer of oxide material. The patterned mask layer 304 covers the area of the oxide layer 302 where the protrusions are to be formed. Next, using the patterned mask layer 304 as a mask, an isotropic etching process is performed to remove portions of the oxide material layer without exposing the substrate 300 to form the protrusions 302a.

Then, referring to FIG. 3B, a pair of nitride spacers 306 are formed on the sidewalls of the patterned mask layer 304 and the protrusions 302a. The method of forming the nitride spacers 306 is, for example, to conformally form a layer of nitride material prior to the oxide layer 302. Thereafter, an isotropic etching process is performed to remove a portion of the nitride material layer. Next, an ion implantation process is performed by patterning the mask layer 304 and the nitride spacer 306 as a mask to form a doping region 308.

In this embodiment, since the ion implantation process is performed by patterning the mask layer 304 and the nitride spacer 306 as a mask while forming the doping region 308, the doping region 308 on both sides of the protrusion 302a There can be a large distance between each other, which can avoid the short channel effect and the punch through phenomenon of the memory formed in the subsequent operation, which affects the device performance.

Next, referring to FIG. 3C, the patterned mask layer 304 and the nitride spacers 306 are removed. In the present embodiment, the patterned mask layer 304 and the nitride spacers 306 can be removed simultaneously. Then, a pair of charge storage spacers 310 are formed on the sidewalls of the protrusions 302a. The charge storage spacers 310 serve as charge storage regions in the subsequently formed memory. The charge storage spacer 310 is formed by, for example, conformally forming a charge storage material layer on the oxide layer 302. The material of the charge storage material layer is, for example, nitride, polycrystalline germanium, high dielectric constant material, cerium oxide, cerium oxynitride, aluminum oxide or cerium aluminum oxide. The method of forming the charge storage material layer is, for example, a chemical vapor deposition method. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer. As with the first embodiment, the size of the charge storage spacers 310 can be controlled by adjusting the thickness of the formed charge storage material layer. In the present embodiment, the thickness of the charge storage material layer is, for example, between 40 A and 80 A. In this way, the ability of the charge storage spacers 310 to be too small to affect the stored charge of the memory can be avoided.

Thereafter, referring to FIG. 3D, an oxide layer 312 is formed on the oxide layer 302 and the charge storage spacers 310. The method of forming the oxide layer 312 is, for example, a chemical vapor deposition method. Conductor layer 314 is then formed over oxide layer 312 to form non-volatile memory 30. The method of forming the conductor layer 314 is, for example, a chemical vapor deposition method. The conductor layer 314 is, for example, a polysilicon layer.

The non-volatile memory 30 includes a plurality of memory cells as shown at the broken line, wherein the oxide layer 302, the pair of charge storage spacers 310 and the oxide layer 312 constitute a charge storage structure (the oxide layer 302 and the oxide layer 312). The doped regions 308 on the two sides of the charge storage structure serve as the source region and the drain region, respectively, and the conductor layer 314 serves as a gate. Like the non-volatile memory 10, the second bit effect can be avoided when reading the memory cells of the non-volatile memory 30, and the adjacent memory cells can be prevented from generating programs during the stylization operation. The problem of interference. Further, in the non-volatile memory 30, since there is a large distance between the source region and the drain region, the phenomenon of short channel effect and charge breakdown during operation can be avoided.

Fourth embodiment

4A-4D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a fourth embodiment of the present invention. First, referring to FIG. 4A, an oxide layer 402 having protrusions 402a is formed on the substrate 400. The oxide layer 402 is formed by, for example, forming a layer of an oxide material on the substrate 400. The method of forming the oxide material layer is, for example, a chemical vapor deposition method. A patterned mask layer 404 is then formed over the layer of oxide material. The patterned mask layer 404 covers the area of the oxide layer 402 where the protrusions are to be formed. Next, using the patterned mask layer 404 as a mask, an isotropic etching process is performed to remove portions of the oxide material layer without exposing the substrate 400 to form the protrusions 402a.

Then, referring to FIG. 4B, the ion mask process is performed by patterning the mask layer 404 as a mask to form a doping region 406 in the substrate 400 on both sides of the protrusion 402a. Next, the patterned mask layer 404 is removed. The charge storage material layer 408 is then conformally formed on the oxide layer 402. The material of the charge storage material layer 408 is, for example, nitride, polycrystalline germanium, high dielectric constant material, cerium oxide, cerium oxynitride, aluminum oxide or cerium aluminum oxide. The method of forming the charge storage material layer 408 is, for example, a chemical vapor deposition method. An oxide material layer 410 is then formed over the charge storage material layer 408. The method of forming the oxide material layer 410 is, for example, a chemical vapor deposition method.

Next, referring to FIG. 4C, an isotropic etching process is performed to remove a portion of the oxide material layer 410 and a portion of the charge storage material layer 408 to form a pair of charge storage spacers 408a on the sidewalls of the protrusions 402a. As with the first embodiment, the size of the charge storage spacers 408a can be controlled by adjusting the thickness of the formed charge storage material layer 408. In the present embodiment, the thickness of the charge storage material layer 408 is, for example, between 40 A and 80 A. In this way, the ability of the charge storage spacer 408a to be too small to affect the memory storage charge can be avoided.

Thereafter, referring to FIG. 4D, an oxide layer 412 is formed on the oxide layer 402, the charge storage spacers 408a, and the remaining oxide material layer 410. The method of forming the oxide layer 412 is, for example, a chemical vapor deposition method. Conductor layer 414 is then formed over oxide layer 412 to form non-volatile memory 40. The method of forming the conductor layer 414 is, for example, a chemical vapor deposition method. The conductor layer 414 is, for example, a polysilicon layer.

The non-volatile memory 40 includes a plurality of memory cells as shown at the broken line, wherein the oxide layer 402, the pair of charge storage spacers 408a, the oxide material layer 410, and the oxide layer 412 constitute a charge storage structure (oxide layer) 402, the oxide material layer 410 and the oxide layer 412 may be collectively referred to as a dielectric body), and the doped regions 406 on the two sides of the charge storage structure serve as a source region and a drain region, respectively, and the conductor layer 414 serves as a gate. . Like the non-volatile memory 10, the second bit effect can be avoided when reading the memory cells of the non-volatile memory 40, and the adjacent memory cells can be prevented from generating programs during the stylization operation. The problem of interference.

Fifth embodiment

5A to 5E are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a fifth embodiment of the present invention. First, referring to FIG. 5A, an oxide layer 502 having a protrusion 502a is formed on the substrate 500. The oxide layer 502 is formed by, for example, forming a layer of an oxide material on the substrate 500. The method of forming the oxide material layer is, for example, a chemical vapor deposition method. A patterned mask layer 504 is then formed over the layer of oxide material. The patterned mask layer 504 covers the area of the oxide layer 502 where the protrusions are to be formed. Next, using the patterned mask layer 504 as a mask, an isotropic etching process is performed to remove a portion of the oxide material layer without exposing the substrate 500 to form the protrusions 502a.

Then, referring to FIG. 5B, a pair of charge storage spacers 506 are formed on the sidewalls of the patterned mask layer 504 and the protrusions 502a. The charge storage spacers 506 are formed, for example, by conformally forming a layer of charge storage material prior to the oxide layer 502. The material of the charge storage material layer is, for example, nitride, polycrystalline germanium, high dielectric constant material, cerium oxide, cerium oxynitride, aluminum oxide or cerium aluminum oxide. Thereafter, an isotropic etching process is performed to remove a portion of the charge storage material layer. Next, an ion implantation process is performed with the patterned mask layer 504 and the charge storage spacers 506 as masks to form doped regions 508.

As in the third embodiment, in the present embodiment, the doped regions 508 on the two sides of the protrusions 502a have a large distance therebetween, so that short-channel effects and charges can be prevented from occurring in the subsequently formed memory during operation. The phenomenon of breakdown affects the performance of components.

Next, referring to FIG. 5C, an oxide layer 510 is formed on the oxide layer 502 to cover the patterned mask layer 504, the charge storage spacers 506, and the oxide layer 502. The method of forming the oxide layer 510 is, for example, a chemical vapor deposition method.

Then, referring to FIG. 5D, the patterned mask layer 504 is removed. The method of removing the patterned mask layer 504 is, for example, performing a planarization process (such as a chemical mechanical polishing process), removing the patterned mask layer 504, the portion of the charge storage spacers 506, and the portion of the oxide layer 510 until the protrusion is exposed. The portion 502a forms a pair of charge storage spacers 512 on the sidewalls of the protrusions 502a.

Thereafter, referring to FIG. 5E, an oxide layer 514 is formed on the oxide layer 502 and the charge storage spacers 512. The method of forming the oxide layer 514 is, for example, a chemical vapor deposition method. Conductor layer 516 is then formed over oxide layer 514 to form non-volatile memory 50. The method of forming the conductor layer 516 is, for example, a chemical vapor deposition method. The conductor layer 516 is, for example, a polysilicon layer.

The non-volatile memory 50 includes a plurality of memory cells as shown at the dashed line, wherein the oxide layer 502, the pair of charge storage spacers 512 and the oxide layer 514 constitute a charge storage structure (the oxide layer 502 and the oxide layer 514). The doped regions 508 on the two sides of the charge storage structure serve as a source region and a drain region, respectively, and the conductor layer 516 serves as a gate. Like the non-volatile memory 10, the second bit effect can be avoided when reading the memory cells of the non-volatile memory 50, and the adjacent memory cells can be prevented from generating programs during the stylization operation. The problem of interference. Further, in the non-volatile memory 50, since there is a large distance between the source region and the drain region, the phenomenon of short channel effect and charge breakdown during operation can be avoided.

In each of the memory cells of the non-volatile memory 10, 20, 30, 40, 50, the two charge storage spacers for storing charges are separated from each other and arranged in mirror symmetry. Further, in each of the memory cells of the non-volatile memory 10, 20, 30, the two charge storage spacers respectively have a curved surface or a sloped surface, and the curved surfaces or inclined surfaces of the two charge storage spacers are apart from each other. In addition, in each of the memory cells of the non-volatile memory 40, the two charge storage spacers 408a are respectively L-shaped, and the horizontal portions of the two L-shaped charge storage spacers 408a extend away from each other.

In addition, during the fabrication of the charge storage spacers 408a of the non-volatile memory 40, after the formation of the charge storage material layer 408, an oxide material layer 410 is formed on the charge storage material layer 408, and then The isotropic etching process is performed to form the charge storage spacers 408a, so the charge storage spacers 408a may have a larger memory storage spacers in each of the memory cells of the non-volatile memory 10, 20, 30. The volume, and therefore the stored charge, is closer to the doped region to effectively improve the second bit effect and stylized interference effects.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40, 50. . . Non-volatile memory

100, 200, 300, 400, 500. . . Base

102, 108, 112, 202, 210, 302, 312, 402, 412, 502, 510, 514. . . Oxide layer

102a, 202a, 302a, 402a, 502a. . . Protrusion

104, 204, 304, 404, 504. . . Patterned mask layer

106, 206, 308, 406, 508. . . Doped region

110, 208, 310, 408a, 506, 512. . . Charge storage spacer

114, 212, 314, 414, 516. . . Conductor layer

306. . . Nitride spacer

408. . . Charge storage material layer

410. . . Oxide material layer

1A to 1D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a first embodiment of the present invention.

2A-2C are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a second embodiment of the present invention.

3A-3D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a third embodiment of the present invention.

4A-4D are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a fourth embodiment of the present invention.

5A-5E are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to a fifth embodiment of the present invention.

100. . . Base

102, 108. . . Oxide layer

102a. . . Protrusion

106. . . Doped region

110. . . Charge storage spacer

Claims (17)

A method of fabricating a non-volatile memory, comprising: forming a first oxide layer on a substrate, the first oxide layer having a protrusion; forming a pair of doping in the substrate on both sides of the protrusion Forming a pair of charge storage spacers on sidewalls of the protrusions; forming a second oxide layer on the first oxide layer and the pair of charge storage spacers; and forming on the second oxide layer A conductor layer. The method for fabricating a non-volatile memory according to claim 1, wherein the method for forming the first oxide layer comprises: forming a first oxide material layer on the substrate; Forming a patterned mask layer on the material layer; using the patterned mask layer as a mask, removing a portion of the first oxide material layer to form the protrusion; and removing the patterned mask layer. The method of fabricating the non-volatile memory of claim 2, wherein the substrate on both sides of the protrusion is not exposed after removing a portion of the first oxide material layer. The method of fabricating the non-volatile memory of claim 3, wherein after the forming the protrusion and before removing the patterned mask layer, the mask layer is further covered by the patterned mask layer An ion implantation process is performed to form the pair of doped regions. The method for fabricating a non-volatile memory according to claim 4, wherein the method of forming the pair of charge storage spacers comprises: conformally forming a layer of charge storage material on the first oxide layer; An isotropic etching process is performed to remove a portion of the charge storage material layer. The method for fabricating a non-volatile memory according to claim 4, wherein the method for forming the pair of charge storage spacers comprises: conformally forming a layer of charge storage material on the first oxide layer; Forming a second oxide material layer on the charge storage material layer; and performing an isotropic etching process to remove a portion of the second oxide material layer and a portion of the charge storage material layer. The method for fabricating a non-volatile memory according to claim 3, wherein after the forming the protrusion and before removing the patterned mask layer, the method further comprises: the patterning mask layer and the Forming a pair of nitride spacers on sidewalls of the protrusions; and performing an ion implantation process by using the patterned mask layer and the pair of nitride spacers as a mask to form the pair of doped regions. The method of fabricating the non-volatile memory of claim 7, wherein the pair of nitride spacers are simultaneously removed when the patterned mask layer is removed. The method of fabricating the non-volatile memory of claim 7, wherein the method of forming the pair of charge storage spacers comprises: conformally forming a layer of charge storage material on the first oxide layer; An isotropic etching process is performed to remove a portion of the charge storage material layer. The method for fabricating a non-volatile memory according to claim 7, wherein after forming the pair of doped regions and before removing the patterned mask layer, forming a third oxide layer is further included. The patterned mask layer, the pair of nitride spacers and the first oxide layer are covered. The method of fabricating the non-volatile memory of claim 10, wherein the method of removing the patterned mask layer comprises performing a planarization process, removing the patterned mask layer, and partially removing the pair of nitrides The spacer and a portion of the third oxide layer are exposed until the protrusion is formed, and the pair of charge storage spacers are formed. The method of fabricating the non-volatile memory of claim 2, wherein after removing a portion of the first oxide material layer, the substrate on both sides of the protrusion is exposed. The method of fabricating the non-volatile memory of claim 12, wherein the forming the mask layer is used as a mask after forming the protrusion and before removing the patterned mask layer An ion implantation process is performed to form the pair of doped regions. The method for fabricating a non-volatile memory according to claim 13 , wherein the method for forming the pair of charge storage spacers comprises: conformally forming a third oxide layer on the substrate; Forming a layer of charge storage material conformally on the oxide layer; and performing an isotropic etching process to remove a portion of the charge storage material layer. A non-volatile memory comprising: a substrate; a charge storage structure disposed on the substrate; a first doped region and a second doped region respectively disposed in the substrate on both sides of the charge storage structure And a gate disposed on the charge storage structure, wherein the charge storage structure comprises a dielectric body, a first charge storage spacer and a second charge storage spacer, the first charge storage spacer and the The second charge storage spacers are mirror-symmetrically disposed in the dielectric body and are separated from each other, the first charge storage spacer is adjacent to the first doped region, and the second charge storage spacer is adjacent to the second doped region The first charge storage spacer and the second charge storage spacer are respectively L-shaped, and a horizontal portion of the first charge storage spacer and a horizontal portion of the second charge storage spacer extend away from each other, or The first charge storage spacer and the second charge storage spacer respectively have a curved surface or a slope, and a curved surface or a slope of the first charge storage spacer and the second charge storage gap The curved surface or inclined surface away from each other. The non-volatile memory of claim 15, wherein the material of the first charge storage spacer and the second charge storage spacer comprises a nitride, a polysilicon, a high dielectric constant material, a cerium oxide, and a nitrogen. Cerium oxide, aluminum oxide or yttrium aluminum oxide. The non-volatile memory of claim 15, wherein the first charge storage spacer and the second charge storage spacer have a thickness between 40 A and 80 A.