TWI478065B - Emulation of execution mode banked registers - Google Patents

Description

Execution mode backup register simulation [References in related applications]

This application is part of the continuous case of the US patent application in the application. These cases are all included in the case:

This application claims priority from the following US Provisional Patent Applications, each of which is incorporated herein by reference.

US official patent application

It refers to the following priority of the US temporary application:

The following three official US applications

These are the continuations of the following US official application:

And cite the following US temporary application priority:

This application is related to the following US official patent applications:

This invention relates to the technical field of microprocessors, and more particularly to microprocessors having conditional instructions in an instruction set.

The x86 processor architecture developed by Intel Corporation of Santa Clara, California and the advanced reduced risc machines (ARM) architecture developed by ARM Ltd. of Cambridge, UK are two well-known processes in the computer field. Architecture. Many computer systems using ARM or x86 processors have emerged, and the demand for this computer system is growing rapidly. Today, the ARM architecture processing core dominates the low-power, low-cost computer market, such as mobile phones, handheld electronics, tablets, network routers and hubs, and set-top boxes. For example, the main processing power of Apple's iPhone and iPad is provided by the processing core of the ARM architecture. On the other hand, x86 architecture processors dominate high-priced markets that require high performance, such as laptops, desktops, and servers. However, as the performance of ARM cores has improved and the power and cost of some x86 processors have improved, the boundaries between the aforementioned low-priced and high-priced markets have become blurred. In the mobile computing market, such as smart phones, these two architectures have begun to compete fiercely. In the laptop, desktop and server markets, it is expected that these two architectures will compete more frequently.

The aforementioned competitive situation has caused computer device manufacturers and consumers to be in a dilemma because it is impossible to judge which architecture will dominate the market, more precisely, It is impossible to determine which architecture software developer will develop more software. For example, some consumer individuals who purchase a large number of computer systems on a monthly or yearly basis, based on cost-efficiency considerations, such as price discounts for large purchases and simplification of system maintenance, tend to purchase computer systems with the same system configuration settings. . However, the user groups in these large consumer individuals often have various computing needs for these computer systems with the same system configuration settings. Specifically, some users' needs are to be able to execute programs on ARM architecture processors. Other users need to be able to execute programs on x86 architecture processors, and some users hope to be able to simultaneously The program is executed on the architecture. In addition, new, unexpected computing needs may arise and require another architecture. Under these circumstances, some of the funds invested by these large individuals become waste. In another example, the user has an important application that can only be executed on the x86 architecture, so he purchased a computer system with an x86 architecture (and vice versa). However, subsequent versions of this application were developed for ARM architecture and are superior to the original x86 version. The user would like to convert the architecture to execute the new version of the application, but unfortunately he has invested considerable cost in the architecture that is not intended to be used. Similarly, users originally invested in applications that can only be executed on the ARM architecture, but later hope to use applications developed for the x86 architecture that are not found in the ARM architecture or applications that are better than the ARM architecture. Will encounter such problems, and vice versa. It is worth noting that although the small entity or individual invested in a larger amount of entities is small, the investment loss ratio may be higher. Other examples of similar investment losses may occur in a variety of different computing markets, such as x86 architecture to ARM architecture or ARM architecture. Conversion to the x86 architecture. Finally, computing device manufacturers that invest large amounts of resources to develop new products, such as OEMs, will also fall into the trap of this architecture choice. If the manufacturer develops and manufactures a large number of products based on the x86 or ARM architecture, and the user's demand suddenly changes, it will lead to the waste of many valuable research and development resources.

It is helpful for manufacturers and consumers of computing devices to be able to protect their investments from the winners of the two architectures. It is therefore necessary to propose a solution for system manufacturers to develop x86 for users simultaneously. Arithmetic device for architecture and ARM architecture.

The need to enable systems to execute multiple instruction set programs has been around for a long time. These requirements are mainly due to the fact that consumers are consuming software programs that are executed on old hardware at considerable cost, and their instruction sets are often incompatible with new hardware. For example, the IBM 360 System Model 30 has the pain of being compatible with the features of the IBM 1401 system to mitigate the 360 system in which users switch from a 1401 system to a higher performance and improved feature. The Model 30 has a 360 system and a Read Only Storage (ROS) of the 1401 system, enabling it to be used in the 1401 system with the auxiliary storage space pre-stored with the required information. In addition, in the case of software programs developed in high-level languages, new hardware developers have little control over the software programs compiled for old hardware, and software developers lack the motivation to recompile for new hardware (re-compile). The source code, especially in the case where the software developer and the hardware developer are different individuals. Siberman and Ebcioglu's article "An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures" by Computer, June 1993, No. 6 reveals a benefit Improve existing Complex Instruction Set (CISC) architectures with systems implemented in Reduced Instruction Set (RISC), superscalar and super long instruction word (VLIW) architectures (hereafter referred to as native architecture) (eg IBM S/390) A technique for performing efficiency, the system disclosed therein includes a native engine that executes a native code and a migrant engine that executes a destination code, and can translate an object bode into a native code according to the translation software. (native code) translation effect, between the two encodings as needed to convert. Referring to U.S. Patent No. 7,047,394, issued May 16, 2006, Van Dyke et al. discloses a processor having an execution pipeline for executing program instructions of a native reduced instruction set (Tapestry) and utilizing hardware The combination of translation and software translation translates x86 program instructions into instructions for the native reduced instruction set. Nakada et al. proposed a heterogeneous SMT processor with an ARM architecture front-end pipeline and a Fujitsu FR-V (ultra-long instruction word) architecture front-end pipeline. The ARM architecture front-end pipeline is used for irregular (irregular) Software programs (such as operating systems), and the Fujitsu FR-V (ultra-long instruction word) architecture front-end pipeline is used in multimedia applications to import an additional long instruction word into the FR-V long instruction word. The end pipeline maintains instructions from the front end pipeline. Please refer to Buchty and Weib, eds, Universitatsverlag Karlsruhe in November 2008 at First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC'08), Lake Como, Italy, (with MICRO-41) The article "OROCHI: A Multiple Instruction Set SMT Processor" in the proceedings (ISBN 978-3-86644-298-6). The method proposed in this paper is to reduce the entire system in a heterogeneous system single-chip (SOC) device (such as Texas Instruments) The space occupied by the OMAP application processor). The heterogeneous system single chip device has an ARM processor core plus one or more co-processors (eg, TMS 320, multiple digital signal processors, or multiple graphics processing units (GPUs)). These coprocessors do not share instruction execution resources, but are integrated into different processing cores on the same die.

Software translators, or software emulators, dynamic binary translators, etc., are also used to support the ability to execute software programs on processors that differ from the software architecture. . Among the popular commercial examples are the Motorola 68K-to-PowerPC emulator with an Apple Macintosh computer, which can execute a 68K program on a Macintosh computer with a PowerPC processor, and a subsequent PowerPC- A to-x86 emulator that executes a 68K program on a Macintosh computer with an x86 processor. Transmeta, Inc., located in Santa Clara, Calif., combines the core hardware of the Very Long Instruction Word (VLIW) with the "Software Direct Translator (Code Morphing Software)) To dynamically compile or emulate x86 code sequences to execute x86 code, please refer to the 2011 Wikipedia instructions for Transmeta <http://en.wikipedia.org/wiki/Transmeta>. In addition, reference is made to U.S. Patent No. 5,832,205, issued to Kelly et al. IBM's DAISY (Dynamic Architecture Instruction Set from Yorktown) system features very long instruction word (VLIW) machines and dynamic binary software translation, and Cocoa provides 100% legacy architecture software compatible simulation. DAISY has a virtual machine observer in a read-only memory (Virtual Machine Monitor), parallelizing and storing VLIW primitives to some of the main memory of the old system architecture, avoiding the code fragments of these old architectures. Subsequent programs are re-translationed. DAISY has fast compiler optimization algorithms to improve performance. QEMU is a machine emulator with a software dynamic translator. QEMU can emulate a variety of central processing units such as x86, PowerPC, ARM and SPARC in a variety of host systems such as x86, PowerPC, ARM, SPARC, Alpha and MIPS. Please refer to QEMU, a Fast and Portable Dynamic Translator, Fabrice Bellard, USENIX Association, FREENIX Track: 2005 USENIX Annual Technical Conference, as its developers call "the dynamic translation of the target processor instruction execution (runtime conversion), Convert it to the main system instruction set, and the resulting binary code is stored in a translation cache for repeated access....QEMU [compared to other dynamic translators] is much simpler because it only connects to the GNCC compiler for offline The machine code fragment generated when (off line). Also refer to the dissertation "ARM Instruction Set Simulation on Multi-core x86 Hardware" by Lee Wang Hao of Adelaide University on June 19, 2009. While software-based solutions provide processing power that meets multiple computing needs, it is less than adequate for multiple users.

Static binary translation is another technology with high performance potential. However, there are technical problems in the use of binary translation technology. (eg self-modifying code, indirect branches only at run-time) and commercial and legal barriers (eg this technology may require a hardware developer) Cooperate with the pipeline needed to develop new programs; there is a potential for unauthorized distribution or copyright infringement).

One embodiment of the present invention provides a microprocessor. The microprocessor includes a plurality of processing modes including a user mode and a plurality of exception event modes. The microprocessor further includes at least one execution unit for performing an arithmetic operation on an operation element specified by the program instruction. The microprocessor further includes a first storage element group coupled to the execution unit, wherein the a storage element group includes a first subset of operation elements and provides the first operation element subset to the execution unit; the microprocessor further includes a second storage element group associated with each processing mode, wherein the The second storage element group includes a second subset of operation elements, wherein the second storage element group cannot directly provide the second operation element subset to the execution unit; and the microprocessor further includes a logic gate. The logic gate stores the first subset of the operands in the first set of storage elements to the second set of storage elements associated with the current processing mode when entering from a current processing mode to a new processing mode. And returning the second subset of operands in the second set of storage elements associated with the new processing mode to the first set of storage elements.

Another embodiment of the present invention provides a method for operating a microprocessor, the microprocessor including a plurality of processing modes having a user mode and a plurality of exception event modes, wherein the microprocessor Further comprising at least one execution unit, the execution unit performing an arithmetic operation on the operation unit through a specific program instruction, the method comprising: when the microprocessor operates in one of the processing modes, the first one Providing a first set of operands to the execution unit to perform an arithmetic operation; and when entering the new processing mode from the current processing mode into the processing mode, the method includes the following steps: The first set of operands of the storage element group is stored to a second storage unit group associated with one of the current processing modes; and the second operand set associated with one of the third storage element groups associated with the new processing mode is restored to The first set of storage elements; and when the microprocessor is operating in the new processing mode, the second set of operands is provided from the first set of storage elements to the execution unit to perform an arithmetic operation.

Yet another embodiment of the present invention provides a computer program product. The computer program product is encoded in at least one computer readable storage medium for use in an computing device. The computer program product has a computer readable code for the medium, the computer program product comprising: a computer readable code for the medium, which is used to designate a microprocessor, the computer readable program The code includes a first code, which is used to specify a plurality of processing modes, the processing mode includes a user mode and a plurality of exception event modes; the computer readable code further includes a second code, which is used to specify In at least one execution unit, the execution unit performs an arithmetic operation on the operation unit through a specific program instruction; the computer readable code further includes a third code, which is used to designate a first storage element group, the A storage element group is coupled to the execution unit, wherein the first storage element group has a first subset of operation elements and provides the first operation element subset to the execution unit; the computer can read the code Contains a fourth code to specify association with the processes One of the modes of the second storage element group. The second storage element group has a second subset of operation elements, wherein the second operation element cannot directly provide the second operation element subset to the execution unit; and the computer readable code further includes a fifth The code is used to specify a logic gate, wherein when the current processing mode enters one of the processing modes, the logic gate stores the first subset of the operation element of the first storage element group to Corresponding to the second storage element group of the current processing mode, and returning the second subset of operation elements of the second storage element group associated with the new processing mode to the first storage element group.

An embodiment of the present invention provides a microprocessor that supports an ISA, which is specified in a plurality of processing modes and is only fixed to a complex architecture register, and the architectural registers are associated with each processing mode. , and only one load multiple instructions, the load multiple instructions instruct the microprocessor to load data from the memory and pass in one or more architectural registers assigned to the load multiple instructions, the micro The processor includes: a direct storage device having data associated with the first portion of the one of the architecture registers, and coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; The processor further includes an indirect storage having data associated with a second portion of one of the architectural registers, wherein the indirect storage cannot directly provide information associated with the second portion of the architectural register to the An execution unit, wherein the architecture registers are dynamically distributed among the first portion of the architecture registers and the architecture registers according to the current processing mode in the processing modes Moiety; and wherein each configuration register specified based on the load multiple instruction: if the configuration register when a first line is located in the portion of the microprocessor-based data from memory loaded in vivo, and transmitted Entering the direct storage; and if the architecture register is located in the second portion, the microprocessor loads the data from the memory and transmits the data to the direct storage, and then the data of the direct storage Go to the indirect storage.

Another embodiment of the present invention provides a method for operating a microprocessor that supports an ISA that is assigned to a plurality of processing modes, to a complex architecture register associated with each processing mode, and to specify Loading multiple instructions, the load multiple instructions instructing the microprocessor to load data from the memory and pass in one or more architectural registers assigned to the load multiple instructions, the method comprising, for Designated for each architecture register that loads multiple instructions. If the architecture register is located in the first portion, the data is loaded from the memory into the direct storage of the microprocessor, and if the architecture register is Located in the second portion, the data is loaded from the memory to the direct storage, and then the data of the direct storage is stored to the indirect storage. The direct storage device has data associated with the first portion of one of the architecture registers and is coupled to at least one execution unit of the processor to provide the data to the execution unit; the indirect storage has associated with the Information of a second part of the architecture register, wherein the indirect storage cannot directly provide information related to the second portion of the architecture register to the execution unit; wherein the architecture registers are based on the The current processing mode of the processing modes is dynamically distributed between the first portion of the architectural register and the second portion of the architectural register.

Another embodiment of the present invention provides a microprocessor that supports an ISA that specifies a plurality of processing modes and a fixed-number architecture register, and the architectural registers are associated with each processing mode, and Specified on a store multiple command, the store multiple command indicates that the microprocessor will Data is dumped from the one or more architectural registers designated to store the multiple instructions to the memory, the microprocessor comprising a direct storage having information associated with the first portion of one of the architectural registers, And coupled to the at least one execution unit of the microprocessor to provide the data to the execution unit; the microprocessor further includes an indirect storage having information associated with the second portion of one of the architecture registers, The indirect storage device cannot directly provide the data associated with the second portion of the architecture register to the execution unit; wherein the architecture registers are dynamically according to the current processing mode in the processing modes. The first portion of the architecture register and the second portion of the architecture register; and wherein each architectural register is assigned to the store multiple instructions: if the architectural register is located In a first part, the microprocessor transfers data from the direct storage to the memory; and if the architecture register is located in the second portion, the microprocessor is loaded from the indirect storage Information and pass directly to the reservoir, and the data will be directly from the reservoir to dump memory.

Yet another embodiment of the present invention provides a method for operating a microprocessor that supports an ISA that specifies a plurality of processing modes and specifies a complex architecture register, and the structures are temporarily stored. Corresponding to each processing mode, and designating a store multiple instruction instructing the microprocessor to transfer data from the one or more architectural registers designated to store the multiple instructions to the memory The method includes: each architecture register is configured to store the multiple instructions: if the architecture register is located in the first portion, transferring data from the direct storage of the microprocessor to the memory; And if the architecture register is located in the second part, the data is loaded from the indirect storage and passed to the direct storage The memory is then transferred from the direct storage to the memory. The direct storage device has information associated with a first portion of the architecture register and is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; wherein the indirect storage device is associated with Information attached to the second part of one of the architecture registers. The indirect storage cannot directly provide the data associated with the second portion of the architecture register to the execution unit; wherein the architectural registers are dynamically distributed according to the current processing mode in the processing modes The first portion of the architecture register and the second portion of the architecture register.

A further embodiment of the present invention provides a computer program product encoded in at least one computer readable storage medium for use in an computing device, the computer program product comprising: a computer readable medium suitable for the medium The code is used to designate a microprocessor that supports an ISA that specifies a plurality of processing modes and only a complex architecture register, and the architecture registers are associated with each processing. a mode, and a load multiple instruction, the load multiple instruction instructing the microprocessor to load data from the memory and pass in one or more architectural registers designated for the load multiple instructions, The computer readable code includes a first code for specifying a direct storage having a data associated with a first portion of the architecture register and coupled to the microprocessor At least one execution unit for providing the information to the execution unit; the computer readable code further comprising a second code for specifying indirect storage, the indirect storage device To one of the plurality of configuration register information of the second portion, wherein the reservoir can not provide indirect directly related to the profile of the second portion of the architecture register to the execution unit; wherein the plurality of The architecture register is dynamically distributed in the first portion of the architecture register and the second portion of the architecture register according to the current processing mode in the processing modes; wherein each architecture register is Specifying to load multiple instructions: if the architecture register is located in the first portion, the microprocessor loads data from the memory and passes it to the direct storage; and if the architecture register In the second part, the microprocessor loads the data from the memory and transfers it to the direct storage, and then transfers the direct storage data to the indirect storage.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

Noun definition

The instruction set defines the correspondence between the set of binary code values (ie, machine language instructions) and the operations performed by the microprocessor. Machine language programs are basically encoded in binary systems, but other systems can be used, such as some of the early IBM computer language programs, although they are ultimately represented by physical signals that exhibit binary values at high or low voltages. It is encoded by the decimal system. The machine language instruction instructs the microprocessor to perform operations such as: adding the operands in the scratchpad 1 to the operands in the scratchpad 2 and writing the result to the scratchpad 3, and the operand of the memory address 0x12345678 The immediate operation element specified by the instruction is subtracted and the result is written into the scratchpad 5. The value in the temporary register 6 is moved according to the number of bits specified by the temporary register 7, and if the zero flag is set, the branch is commanded. The latter 36 bytes are loaded into the scratchpad 8 with the value of the memory address 0xABCD0000. Therefore, The set system defines the binary coded values of the various machine language instructions that cause the microprocessor to perform the operations to be performed. It should be understood that the instruction set defines the correspondence between the binary value and the operation of the microprocessor, and does not mean that a single binary value corresponds to a single microprocessor operation. Specifically, in some instruction sets, multiple binary values may correspond to the same microprocessor operation.

The Instruction Set Architecture (ISA), from the context of the family of microprocessors, contains (1) the instruction set; (2) the set of resources that the instruction set instruction can access (eg, the scratchpad required for memory addressing) Mode); and (3) a set of exception events generated by the microprocessor in response to instruction execution of the instruction set (eg, division by zero, page fault, memory protection violation, etc.). Because programmers, such as compilers and compiler writers, want to make machine language programs executed in a family of microprocessors, the ISA definition for this family of microprocessors is needed. So the manufacturer of the microprocessor family usually defines the ISA in the operator's manual. For example, the Intel 64 and IA-32 Architectures Software Developer's Manual (Intel 64 and IA-32 Architectures Software Developer's Manual), which was released in March 2009, defines the ISA for Intel 64 and IA-32 processor architectures. This software developer's manual contains five chapters. The first chapter is the basic architecture; the second chapter is the instruction set reference A to M; the second chapter is the instruction set reference N to Z; the third chapter is the system programming guide. The third chapter is the second part of the system programming guide. This manual series is the reference document for this case. This type of processor architecture is often referred to as the x86 architecture, and is described in x86, x86 ISA, x86 ISA family, x86 family, or similar terms. In another example, the ARM architecture reference manual published in 2010, ARM v7-A and ARM v7-R version Errata markup, defines the ISA of the ARM processor architecture. This reference manual series is a reference file. This ARM processor The architecture ISA is also referred to herein as ARM, ARM ISA, ARM ISA family, ARM family or similar terms. Other well-known ISA families include IBM System/360/370/390 and z/Architecture, DEC VAX, Motorola 68k, MIPS, SPARC, PowerPC and DEC Alpha. The definition of ISA will cover the processor family. As the processor family evolves, manufacturers will improve the original processor by adding new instructions to the instruction set and/or adding new scratchpads to the scratchpad group. ISA. For example, with the development of the x86 programming architecture, the Intel Pentium III processor family imported a set of 128-bit multimedia extended instruction set (MMX) registers as a single instruction multiple data stream extension (SSE) instruction set. As part of the x86 ISA machine language program has been developed to take advantage of the XMM scratchpad to improve performance, although the existing x86 ISA machine language program does not use the single-instruction multiple data stream extension instruction set XMM register. In addition, other manufacturers have designed and manufactured microprocessors that can execute x86 ISA machine language programs. For example, AMD and VIA Technologies are adding new technology features to the x86 ISA, such as 3DNOW for AMD! Single-instruction multiple data stream (SIMD) vector processing instructions, and VIA Technologies' Padlock security engine random number generator and advanced cryptography engine technology, all of which are machines using x86 ISA Language programs, but not implemented by existing Intel microprocessors. As another example, the ARM ISA originally defined an ARM instruction set state with a 4-bit instruction. However, as the ARM ISA evolves, other instruction set states are added, such as the Thumb instruction set state with 2-bit instruction to increase the encoding density and to speed up the Java bytecode program. The Jazelle instruction set state, the ARM ISA machine language program has been developed to use some or all of the other ARM ISA instruction set states, even if the existing ARM ISA machine language program was originally created without these other ARM ISA instruction set states.

An Instruction Set Architecture (ISA) machine language program that contains a sequence of ISA instructions, that is, a sequence of binary code values corresponding to the sequence of operations performed by the program writer to execute the program. Therefore, the x86 ISA machine language program contains the x86 ISA instruction sequence, and the ARM ISA machine language program contains the ARM ISA instruction sequence. Machine language program instructions are stored in memory and retrieved and executed by the microprocessor.

A hardware instruction translator comprising a plurality of transistor configurations for receiving ISA machine language instructions (eg, x86 ISA or ARM ISA machine language instructions) as input and correspondingly outputting one or more microinstructions to the microprocessor The execution pipeline. The execution result of the execution pipeline execution microinstruction is defined by the ISA instruction. Thus, the execution pipeline "implements" the ISA instructions through collective execution of these microinstructions. That is, the execution pipeline implements the operations specified by the input ISA instructions through the collective execution of the microinstructions that are output to the hardware instruction translator to produce the results defined by the ISA instructions. Thus, a hardware instruction translator can be considered to "translate" an ISA instruction into one or more execution microinstructions. The microprocessor described in this embodiment has a hardware instruction translator to translate x86 ISA instructions and ARM ISA instructions into microinstructions. However, it should be understood that the hardware instruction translator does not necessarily translate the entire instruction set defined by the x86 user manual or the ARM user manual, but often only translates a subset of these instructions, as Most x86 ISA and ARM ISA The processor only supports a subset of instructions defined in its corresponding user manual. Specifically, the x86 user operation manual defines a subset of instructions translated by the hardware instruction translator, which does not necessarily correspond to all existing x86 ISA processors, and the ARM user operation manual defines translation by the hardware instruction translator. The set of instructions does not necessarily correspond to all existing ARM ISA processors.

The execution pipeline is a sequence of stages. Each level of the multi-level sequence has hardware logic and a hardware register. The hardware register maintains the output signal of the hardware logic and provides the output signal to a level below the multi-level sequence according to the clock signal of the microprocessor. The execution pipeline can have multiple multi-level sequences, such as multiple execution pipelines. The execution pipeline receives the microinstruction as an input signal and accordingly performs an operation specified by the microinstruction to output an execution result. The operations specified by the microinstructions and performed by the hardware logic of the execution pipeline include, but are not limited to, arithmetic, logic, memory load/store, compare, test, and branch parsing, and the data formats for operations include, but are not limited to, integers. , floating point numbers, letters, binary coded decimals (BCD), and packed format. The execution pipeline executes microinstructions to implement ISA instructions (such as x86 and ARM) to generate the results defined by the ISA instructions. The execution pipeline is different from the hardware instruction translator. Specifically, the hardware instruction translator generates the execution micro-instructions, and the execution pipeline executes the instructions, but does not generate these execution micro-instructions.

The instruction cache is a random access memory device in the microprocessor. The microprocessor places instructions of the ISA machine language program (such as x86 ISA and ARM ISA machine language instructions), and the instructions are retrieved from the system memory. And by the microprocessor according to the execution flow of the ISA machine language program Cheng, to execute. Specifically, the ISA defines an instruction address register to hold the memory address of the next pending ISA instruction (for example, the x86 ISA is defined as an instruction indicator (IP) and is defined as a program in the ARM ISA system). Counter (PC)), and when the microprocessor executes a machine language program to control the program flow, the microprocessor updates the contents of the instruction address register. The ISA instructions are cached for subsequent retrieval. When the ISA instruction address of the next machine language program included in the register is located in the current instruction cache, the cache instruction can be quickly fetched according to the contents of the instruction register, and the ISA instruction is taken out from the system memory. The ISA directive. In particular, the program obtains data from the instruction cache based on the memory address of the instruction address register (such as instruction index (IP) or program counter (PC), instead of specifically using a load or store instruction. The specified memory address is used for data retrieval. Therefore, the instruction set architecture instruction is treated as a dedicated data cache of data (eg, data presented by the hardware portion of the software translation system), specifically using a load/store address rather than an instruction address. The value of the register is accessed, not the instruction cache referred to here. In addition, a hybrid cache of instructions and data is available, based on the value of the instruction address register and based on the load/store address, rather than just the load/store address, and is also covered in this description. Within the definition of the instruction cache. In the present description, a load instruction is an instruction to load data from a memory to a microprocessor, and a storage instruction is an instruction to write data to a memory by a microprocessor.

A microinstruction set is a collection of instructions (microinstructions) that a microprocessor's execution pipeline can execute.

Description of the embodiments

The microprocessor disclosed in the embodiment of the present invention can correspond to the hardware through the hardware. The x86 ISA and ARM ISA instructions are translated into micro-instructions that are executed directly by the microprocessor execution pipeline to achieve the x86 ISA and ARM ISA machine language programs. This microinstruction is defined by a microinstruction set different from the microarchitecture of the x86 ISA and ARM ISA. Since the microprocessor described herein requires execution of x86 and ARM machine language programs, the microprocessor's hardware instruction translator translates x86 and ARM instructions into microinstructions and provides these microinstructions to the microprocessor's execution pipeline. These microinstructions are executed by the microprocessor to implement the aforementioned x86 and ARM instructions. Since these implementation micro-instructions are directly provided by the hardware instruction translator to the execution pipeline, unlike systems using software translators, the host instructions are pre-stored to the memory before executing the pipeline execution instructions. Therefore, the aforementioned microprocessor has the potential to execute x86 and ARM machine language programs at a faster execution speed.

1 is a block diagram showing an embodiment of a microprocessor 100 of the present invention that executes x86 ISA and ARM ISA machine language programs. The microprocessor 100 has an instruction cache 102; a hardware instruction translator 104 for receiving x86 ISA instructions and ARM ISA instructions 124 by the instruction cache 102 and translating them into microinstructions 126; an execution pipeline 112, Executing the microinstruction 126 received by the hardware instruction translator 104 to generate the microinstruction result 128, the result is returned to the execution pipeline 112 in the form of an operand; a temporary register file 106 and a memory subsystem 108, respectively An operand is provided to execution pipeline 112 and receives microinstruction result 128 by execution pipeline 112; an instruction fetch unit and branch predictor 114 provides a fetch address 134 to instruction fetch 102; an ARM ISA defined program counter is temporarily The register 116 and an x86 ISA defined instruction indicator register 118 are based on the microinstruction result 128. An update is made and its contents are provided to the instruction fetch unit and the branch predictor 114; and a plurality of configuration registers 122 provide an instruction mode indicator 132 and an environmental mode indicator 136 to the hardware instruction translator 104 and the command port. The unit and branch predictor 114 are fetched and updated based on the microinstruction result 128.

Since the microprocessor 100 can execute x86 ISA and ARM ISA machine language instructions, the microprocessor 100 retrieves instructions from the system memory (not shown) to the microprocessor 100 in accordance with the program flow. The microprocessor 100 accesses the recently retrieved x86 ISA and ARM ISA machine language instructions to the instruction cache 102. The instruction fetch unit 114 will generate a fetch address 134 based on the x86 or ARM instruction byte segments retrieved by the system memory. If the hit instruction cache 102, the instruction cache 102 provides the x86 or ARM instruction byte segment located in the capture address 134 to the hardware instruction translator 104, otherwise the instructions in the system memory are retrieved from the instruction set architecture. 124. The instruction fetch unit 114 generates the fetch address 134 based on the values of the ARM program counter 116 and the x86 command indicator 118. Specifically, the instruction fetch unit 114 maintains a fetch address in a fetch address register. At any time, the instruction fetching unit 114 retrieves the new ISA instruction byte segment, and it updates the retrieval address according to the size of the segment, and sequentially performs according to the existing method until a control flow event occurs. . The control flow event includes the generation of an exception event, the prediction of the branch predictor 114 indicates that there is a take branch in the capture segment, and the execution pipeline 112 responds to a branch instruction that is not predicted by the branch predictor 114. The result of the execution is updated with the ARM program counter 116 and the x86 command indicator 118. The instruction fetching unit 114 updates the captured address to the exception handler address, the predicted target address, or the execution target address in response to a control flow. event. In one embodiment, the instruction cache 102 is a hybrid cache to access the ISA instructions 124 and data. It should be noted that in the hybrid cache embodiment, although the hybrid cache can write data to the cache or load data based on a load/store address, the microprocessor 100 is mixed. In the case of cache fetch instruction 124 of the instruction set architecture, the hybrid cache is accessed based on the values of the ARM program counter 116 and the x86 instruction index 118, rather than based on the load/store address. The instruction cache 102 can be a random access memory device.

The command mode indicator 132 is a state indicating whether the microprocessor 100 is currently capturing, formatting/decoding, and translating the x86 ISA or ARM ISA instructions 124 into the microinstructions 126. In addition, execution pipeline 112 and memory subsystem 108 receive this instruction mode indicator 132, which affects the manner in which microinstruction 126 is executed, although only a small set within the microinstruction set is affected. The x86 instruction index register 118 holds the memory address of the next x86 ISA instruction 124 to be executed, and the ARM program counter register 116 holds the memory address of the next ARM ISA instruction 124 to be executed. In order to control the program flow, the microprocessor 100 updates the x86 instruction index register 118 and the ARM program counter register 116 to the next instruction, the target address of the branch instruction, or the target code of the branch instruction, respectively, when executing the x86 and ARM machine language programs. Is the exception handler address. When the microprocessor 100 executes the instructions of the machine language program of the x86 and ARM ISA, the microprocessor 100 retrieves the instruction of the instruction set architecture of the machine language program from the system memory and places it into the instruction cache 102 to replace Recently less instructions have been taken and executed. The instruction fetch unit 114 is based on the number of the x86 instruction index register 118 or the ARM program counter register 116. The value, and in accordance with the instruction mode indicator 132, indicates that the ISA instruction 124 being retrieved by the microprocessor 100 is in x86 or ARM mode to generate the capture address 134. In one embodiment, the x86 instruction index register 118 and the ARM program counter register 116 can be implemented as a shared hardware instruction address register for providing its contents to the instruction fetch unit and the branch predictor. The mode indicated by the execution pipeline 112 in accordance with the command mode indicator 132 is x86 or ARM and x86 or ARM semantics.

The environmental mode indicator 136 is a state indicating that the microprocessor 100 is using x86 or ARM ISA to describe various execution environments operated by the microprocessor 100, such as virtual memory, exception events, cache control, and global execution time protection. . Thus, the command mode indicator 132 and the environmental mode indicator 136 together produce a plurality of execution modes. In the first mode, both the command mode indicator 132 and the environmental mode indicator 136 point to the x86 ISA, which acts as a general x86 ISA processor. In the second mode, both the command mode indicator 132 and the environment mode indicator 136 point to the ARM ISA, and the microprocessor 100 acts as a general ARM ISA processor. In the third mode, the command mode indicator 132 points to the x86 ISA, but the environment mode indicator 136 points to the ARM ISA, which facilitates the execution of the user mode x86 machine language program under the control of the ARM operating system or the hypervisor. Conversely, in the fourth mode, the command mode indicator 132 points to the ARM ISA, but the environment mode indicator 136 points to the x86 ISA, which facilitates the execution of the user mode under the control of the x86 operating system or hypervisor. ARM machine language program. The values of the command mode indicator 132 and the environmental mode indicator 136 are determined at the beginning of the reset. In an embodiment, the initial value is encoded as a microcode constant, but is permeable. Fuse the configuration fuse and/or modify it using microcode patching. In another embodiment, this initial value is provided to microprocessor 100 by an external input. In one embodiment, the ambient mode indicator 136 will only change after a reset by reset to the ARM (reset-to-ARM) instruction 124 or a reset to x86 (reset-to-x86) instruction 124. (Refer to Figures 6A and 6B below); that is, when the microprocessor 100 is operating normally without being reset by normal reset, reset to x86, or reset to ARM instruction 124, the environmental mode indicator 136 does not change.

The hardware instruction translator 104 receives the x86 and ARM ISA machine language instructions 124 as inputs, and accordingly provides one or more microinstructions 126 as output signals to implement the x86 or ARM ISA instructions 124. Execution pipeline 112 executes one or more microinstructions 126, the result of which is collectively implemented to implement x86 or ARM ISA instructions 124. That is, the collective execution of these microinstructions 126 may perform the operations specified by the x86 or ARM ISA instructions 124 in accordance with the x86 or ARM ISA instructions 124 specified at the input to produce the x86 or ARM ISA instructions 124 defined by the instructions. result. Thus, hardware instruction translator 104 translates x86 or ARM ISA instructions 124 into one or more microinstructions 126. The hardware instruction translator 104 includes a set of transistors that are configured in a predetermined manner to translate the x86 ISA and ARM ISA machine language instructions 124 into the execution microinstructions 126. The hardware instruction translator 104 also has a Boolean logic gate to generate a microinstruction 126 (such as the simple instruction translator 204 shown in FIG. 2). In one embodiment, hardware instruction translator 104 has a microcode read-only memory (e.g., element 234 of complex instruction translator 206 in FIG. 2). The hardware instruction translator 104 utilizes the microcode read-only memory and generates microinstructions according to the complex ISA instruction 124. 126, this part will be further explained in the description of Figure 2. In a preferred embodiment, the hardware instruction translator 104 does not necessarily have to translate the entire set of ISA instructions defined in the x86 user manual or the ARM user manual, as long as one of these instructions can be translated. The collection is fine. In particular, a subset of the ISA instructions 124 defined by the x86 programmer operating manual and translated by the hardware instruction translator 104 does not necessarily correspond to any existing Intel x86 ISA processor developed by the ARM user. The subset of ISA instructions 124 defined by the manual and translated by the hardware instruction translator 104 does not necessarily correspond to any of the existing ISA processors developed by ARM Ltd. Executing one or more of the implementation microinstructions 126 for implementing the x86 or ARM ISA instructions 124 may be provided by the hardware instruction translator 104 all at once to the execution pipeline 112 or sequentially. An advantage of this embodiment is that the hardware instruction translator 104 can provide the execution microinstructions 126 directly to the execution pipeline 112 without having to store the microinstructions 126 in memory between the settings. In the embodiment of the microprocessor 100 of FIG. 1, when the microprocessor 100 executes an x86 or ARM machine language program, the microprocessor 100 executes the x86 or ARM instructions 124 each time the hardware instruction translator 104 The x86 or ARM machine language instructions 124 are translated into one or more microinstructions 126. However, the embodiment of Figure 8 utilizes a microinstruction cache to avoid the problem of repeated translations encountered by the microprocessor 100 each time the x86 or ARM ISA instructions 124 are executed. An embodiment of the hardware instruction translator 104 will be described in more detail in FIG.

Execution pipeline 112 executes the execution microinstructions 126 provided by hardware instruction translator 104. Basically, execution pipeline 112 is a general purpose high speed microinstruction processor. Although the functions described in this article are made of x86/ARM specific Execution pipeline 112 is executed, but most x86/ARM specific functions are actually performed by other portions of microprocessor 100, such as hardware instruction translator 104. In one embodiment, execution pipeline 112 executes register renaming, super-scaling, and non-sequential execution of microinstruction 126 received by hardware instruction translator 104. Execution line 112 will be described in more detail in Figure 4.

The micro-architecture of the microprocessor 100 includes: (1) a microinstruction set; (2) a set of resources that can be accessed by the microinstruction 126 of the microinstruction set, which is a superset of the resources of the x86 and the ARM ISA. And (3) the micro-exception set defined by the microprocessor 100 corresponding to the execution of the microinstruction 126, which is a superset of the exception events of the x86 ISA and the ARM ISA. This microarchitecture is different from x86 ISA and ARM ISA. Specifically, this microinstruction set is oriented in many instruction sets that differ from x86 ISA and ARM ISA. First, the microinstructions of the microinstruction set indicate that the operations performed by the execution pipeline 112 and the instructions of the x86 ISA and ARM ISA instruction sets indicate that the operations performed by the microprocessor are not one-to-one correspondence. Although many of these operations are the same, there are still some microinstruction sets that specify operations that are not specified by the x86 ISA and/or ARM ISA instruction set. Conversely, some x86 ISA and/or ARM ISA instruction set specific operations are not specified by the microinstruction set. Second, the microinstructions of the microinstruction set are encoded in an encoding that is different from the instructions of the x86 ISA and ARM ISA instruction sets. That is, although many of the same operations (eg, add, offset, load, return) are specified in the microinstruction set and in the x86 and ARM ISA instruction sets, the microinstruction set is binary with the x86 or ARM ISA instruction set. There is no one-to-one correspondence between the opcode value correspondence tables. Microinstruction set with x86 or ARM ISA instructions It is often a coincidence that the set binary operation code value correspondence table is the same, and there is still no one-to-one correspondence between them. Third, the microinstruction bit field of the microinstruction set does not have a one-to-one correspondence with the instruction bit field of the x86 or ARM ISA instruction set.

In general, the microprocessor 100 can execute x86 ISA and ARM ISA machine language program instructions. However, the execution pipeline 112 itself is not capable of executing x86 or ARM ISA machine language instructions; rather, the execution microinstructions 126 of the microinstruction set of the microprocessor 100 microarchitecture translated by the x86 ISA and ARM ISA instructions are executed. However, although this micro-architecture is different from the x86 ISA and the ARM ISA, the present invention also proposes other embodiments to open the microinstruction set and other micro-architecture-specific resources to the user. In these embodiments, the microarchitecture can effectively function as a third ISA with a machine language program executable by the microprocessor outside of the x86 ISA and ARM ISA.

The following table (Table 1) describes some of the bit fields of the microinstructions 126 of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

The following table (Table 2) describes some of the microinstructions of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

The microprocessor 100 also contains some micro-architecture-specific resources, such as micro-architecture-specific general-purpose registers, media registers, and sector registers (such as scratchpads for renaming or used by microcode). The scratchpad) and the control scratchpad not found on x86 or ARM ISA, and a private random access memory (PRAM). In addition, this micro-architecture can generate exception events, which are the aforementioned micro-exception events. These exceptions are not seen or specified by the x86 or ARM ISA, but are typically replays of the microinstructions 126 and associated microinstructions 126. For example, these situations include: loading a load miss, which is an execution pipeline 112 assuming a load action and re-executing the load microinstruction 126 upon miss; missing the translation lookaside buffer (TLB), at After the page table walk and the translation lookaside buffer are filled, the microinstruction 126 is re-executed; the floating-point microinstruction 126 receives an abnormal operand (the denormal operand) but the operand is evaluated as normal and needs to be executed in the pipeline. After the operation unit is normalized, the micro-instruction 126 is re-executed; after the execution of the micro-instruction 126, an earlier storage micro-instruction 126 is detected and its address-colliding conflicts, and the loading micro-requirement needs to be re-executed. instruction 126. It should be understood that the bit columns listed in Table 1, the microinstructions listed in Table 2, and the micro-architecture-specific resources and micro-architecture-specific exception events are merely illustrative of the micro-architecture of the present invention, rather than exhaustive All possible embodiments of the invention.

The scratchpad file 106 contains hardware registers used by the microinstructions 126 to hold resources and/or destination operands. Execution pipeline 112 writes its result 128 to scratchpad file 106 and receives the operand by micro-instruction 126 from scratchpad file 106. The hardware scratchpad is an instantiated x86 ISA definition shared with the ARM ISA shared scratchpad family of some of the scratchpad files 106. For example, in one embodiment, the scratchpad file 106 references fifteen 32-bit scratchpads, from the ARM ISA scratchpad R0 to R14 and the x86 ISA estenator (EAX register) to R14D. Shared by the scratchpad. Therefore, if a first microinstruction 126 writes a value to the ARM R2 register, then a subsequent second microinstruction 126 reads the x86 accumulator to receive the same write as the first microinstruction 126. Value and vice versa. This technical feature facilitates the rapid communication of x86 ISA and ARM ISA machine language programs through the scratchpad. For example, assume that the ARM machine language program executed in the ARM machine language operating system can change the command mode 132 to x86 ISA and convert control to an x86 machine language program to perform specific functions because the x86 ISA can support some instructions. It performs operations faster than the ARM ISA, which in this case will facilitate the speed of execution. The ARM program can provide the required information to the x86 executive through the shared register of the scratchpad file 106. Conversely, the x86 executive can provide execution results to the shared scratchpad of the scratchpad file 106 for the ARM program to respond to the x86 executable. This execution result can be seen. Similarly, the x86 machine language program executed by the x86 machine language operating system can change the command mode 132 to the ARM ISA and transfer control to the ARM machine language program; the x86 program can be shared through the scratchpad file 106. The required data is provided to the ARM executive program, and the ARM executable program can provide execution results through the shared scratchpad of the scratchpad file 106, so that the x86 program can see the execution result after the ARM executable program replies. Because the ARM R15 scratchpad is an independently referenced ARM program counter register 116, the sixteenth 32-bit scratchpad that references the x86 R15D register is not shared with the ARM R15 scratchpad. In addition, in one embodiment, sixteen 128-bit XMM0 to XMM15 registers of x86 and sixteen 128-bit advanced single instruction multiple data extensions (Advanced SIMD ("Neon")) register 32 The bit segment is shared with thirty-two 32-bit ARM VFPV3 floating-point registers. The scratchpad file 106 also references the flag register (ie, the x86 EFLAGS register and the ARM condition flag register), and the various control and status registers defined by the x86 ISA and ARM ISA. The state register includes a model specific registers (MSRs) of the x86 architecture and a coprocessor (8-15) register reserved for the ARM architecture. The scratchpad file 106 also references non-architected scratchpads, such as non-architected general-purpose registers for register renaming or used by microcode 234, and non-architected x86-specific model registers and implementation definitions. Or an ARM coprocessor register specified by the manufacturer. The scratchpad file 106 will be further described in Figure 5.

The memory subsystem 108 includes a cache memory hierarchy of cache memory (in one embodiment, a level-1 instruction cache is included). 102, the first level (level-1) data cache and the second layer hybrid cache). The memory subsystem 108 includes a plurality of memory request queues, such as load, store, fill, snoop, and merge write merge buffers. The memory subsystem also includes a memory management unit (MMU). The memory management unit has translation look-aside buffers (TLBs), especially independent instruction and data translation back buffers. The memory subsystem also includes a table walk engine to obtain translations between virtual and physical addresses in response to missed translation buffer buffers. Although instruction cache 102 and memory subsystem 108 are shown as separate in FIG. 1, logically, instruction cache 102 is also part of memory subsystem 108. The memory subsystem 108 is configured to share a common memory space between the x86 and the ARM machine language program so that the x86 and ARM machine language programs can easily communicate with each other through the memory.

The memory subsystem 108 learns the instruction mode 132 and the environment mode 136 to enable it to perform various operations in the appropriate ISA content. For example, memory subsystem 108, in accordance with instruction mode indicator 132, indicates x86 or ARM ISA to perform a check for a particular memory access violation (eg, a limit violation check). In another embodiment, in response to a change in the environmental mode indicator 136, the memory subsystem 108 will flush the translation lookaside buffer; however, when the command mode indicator 132 changes, the memory subsystem 108 does not update the translation accordingly. The backup buffer provides better performance in the third and fourth modes of x86 and ARM in the aforementioned command mode indicator 132 and environmental mode indicator 136. In another embodiment, in response to a translation lookaside buffer miss (TKB miss), the lookup engine indicates x86 or ARM ISA according to the environment mode indicator 136, thereby determining to perform a page lookup operation using the x86 page table or the ARM page table. Take out Translation of the backup buffer. In another embodiment, if the environmental status indicator 136 indicates an x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control registers (eg, CR0 CD and NW bits) that affect the cache policy; Mode indicator 136, indicated as ARM ISA, checks the architectural mode of the associated ARM ISA control register (such as SCTLR I and C bits). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control register (eg, CR0 PG bit) that affects memory management; if the environmental mode indicator 136 Indicated as ARM ISA, check the architectural mode of the associated ARM ISA control register (such as SCTLR M bits). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control register (eg, CR0 AM bit) that would affect alignment detection, if the environmental mode indicator 136 Indicated as ARM ISA, check the architectural mode of the associated ARM ISA control register (such as SCTLR A bit). In another embodiment, if the status indicator 136 indicates an x86 ISA, the memory subsystem 108 (and the hardware instruction translator 104 for privileged instructions) checks the x86 ISA control staging of the currently assigned privilege level (CPL). The architectural state of the device; if the environmental mode indicator 136 indicates an ARM ISA, then the architectural mode of the associated ARM ISA control register indicating the user or privileged mode is checked. However, in one embodiment, the x86 ISA and the ARM ISA share control bits/scratches having similar functions in the microprocessor 100, and the microprocessor 100 does not reference independent control bytes for each instruction set architecture. / scratchpad.

Although the configuration register 122 and the register file 106 are separate in the illustration, the configuration register 122 can be understood as a register file 106. a part of. The configuration register 122 has a global configuration register for controlling various operations of the microprocessor 100 in the x86 ISA and ARM ISA, such as functions that invalidate or disable various features. The global configuration register can disable the ability of the microprocessor 100 to execute the ARM ISA machine language program, that is, the microprocessor 100 becomes a microprocessor 100 capable of executing only x86 instructions, and can make other related and exclusive ARM The capabilities (such as booting x86 (launch-x86) and resetting to x86 (reset-to-x86) instructions 124 and the implementation-defined coprocessor register) are invalid. The global configuration register can also disable the ability of the microprocessor 100 to execute the x86 ISA machine language program, that is, to make the microprocessor 100 a microprocessor 100 capable of executing only ARM instructions, and to enable other related capabilities. (such as the start of ARM and reset to ARM instructions 124 and the new non-architectural specific model register referred to herein) are invalid. In one embodiment, the microprocessor 100 has a predetermined configuration setting at the time of manufacture, such as a hard coded value in the microcode 234. The microcode 234 uses the hard coded value to set the microprocessor 100 at startup. The configuration is written, for example, to the code register 122. However, the partial code register 122 is set in hardware rather than in microcode 234. Additionally, the microprocessor 100 has a plurality of fuses that can be read by the microcode 234. These fuses can be blown to modify the preset configuration values. In one embodiment, the microcode 234 reads the fuse value, performs a mutual exclusion or operation on the preset value and the fuse value, and writes the result of the operation to the configuration register 122. In addition, the effect of the fuse value modification can be recovered with a microcode 234 patch. In the case where the microprocessor 100 is capable of executing x86 and ARM programs, the global configuration register can be used to confirm that the microprocessor 100 (or a particular core 100 of one of the multicore portions of the processor shown in FIG. 7) is Reset or as 6A and 6B show that in response to the x86 form of the INIT instruction, it will boot in the form of an x86 microprocessor or an ARM microprocessor. The global configuration register has some bits to provide the initial preset values to specific architecture control registers, such as the ARM ISA SCTLT and CPACR registers. The multi-core embodiment shown in FIG. 7 has only one global configuration register, even if the configuration of each core can be set separately, such as when the command mode indicator 132 and the environmental mode indicator 136 are both set to x86 or ARM. Choose to boot from x86 core or ARM core. In addition, the enable ARM instruction 126 and the start x86 instruction 126 can be used to dynamically switch between the x86 and ARM instruction modes 132. In one embodiment, the global configuration register can read a new non-architectural specific model register through an x86 RDMSR instruction, and some of the control bits can be uncovered by the x86 WRMSR instruction. A write to a non-architectural-specific model register for a write operation. The global configuration register can also be read by an ARM MCR/MCRR instruction to an ARM coprocessor register that corresponds to the previously unreleased non-architecture specific model register, and some of the control bits are transparent. The ARM MRC/MRRC instruction corresponds to the write to the ARM coprocessor register of this new non-architectural specific model register for write operations.

The register 122 is configured and includes a plurality of different control registers for controlling the operation of the microprocessor 100 from different sides. These non-x86 (non-x86)/ARM control registers include the global control register, non-instruction set architecture control register, non-x86/ARM control register, general control register, And other similar scratchpads. In one embodiment, these control registers can utilize x86 RDMSR/WRMSR instructions to access non-architected specific model registers (MSRS) and utilize ARM MCR/MRC (or The MCRR/MRRC) instruction is accessed by the coprocessor register defined by the new implementation. For example, the microprocessor 100 includes a control register that is not dedicated to x86/ARM to confirm fine-grained cache control. This micro-cache control system is smaller than the x86 ISA and ARM ISA control register. Can provide.

In one embodiment, the microprocessor 100 provides an ARM ISA machine language program to define an ARM ISA co-processor register to access an x86 ISA-specific model register by implementing the ARM ISA co-processor register. It corresponds directly to the corresponding x86 specific model register. The address of this particular model register is specified in the ARM ISA R1 scratchpad. This data is read or written by the ARM ISA register specified by the MRC/MRRC/MCR/MCRR instructions. In one embodiment, a subset of a particular model register is password protected, i.e., the instruction must use a password when attempting to access a particular model register. In this embodiment, the cipher is assigned to the ARM R7:R6 register. If this access action results in an x86 general protection fault, the microprocessor 100 then generates an ARM ISA undefined instruction abort mode (UND) exception event. In one embodiment, the ARM coprocessor 4 (address: 0, 7, 15, 0) accesses the corresponding x86 specific model register.

Microprocessor 100 also includes an interrupt controller (not shown) coupled to execution pipeline 112. In one embodiment, the interrupt controller is an x86 type of Advanced Programmable Interrupt Controller (APIC). The interrupt controller maps the x86 ISA interrupt event to the ARM ISA interrupt event. In one embodiment, x86 INTR corresponds to an ARM IRQ interrupt event; x86 NMI corresponds to an ARM IRQ interrupt event; x86 INIT triggers an INIT-reset sequence when microprocessor 100 starts, regardless of which The instruction set architecture (x86 or ARM) was originally initiated by a hardware reset; the x86 SMI corresponds to the ARM FIQ interrupt event; and the x86 STPCLK, A20, Thermal, PREQ, and Rebranch do not correspond to ARM interrupt events. The ARM machine language accesses the advanced programmable interrupt controller through the new implementation-defined ARM coprocessor register. In one embodiment, the APIC register address is specified in the ARM R0 register, and the address of the APIC register is the same as the address of the x86. In one embodiment, the ARM coprocessor 6 is typically used for privileged mode functions that are typically performed by the operating system. The address of the ARM coprocessor 6 is: 0, 7, nn, 0; wherein nn is 15 to access the advanced programmable interrupt controller; nn is 12-14 to access the bus interface unit, thereby The 8-bit, 16-bit, and 32-bit input/output loops are executed on the processor bus. The microprocessor 100 also includes a bus interface unit (not shown) coupled to the memory subsystem 108 and the execution pipeline 112 as an interface between the microprocessor 100 and the processor bus. In one embodiment, the processor bus is compliant with the specifications of a microprocessor bus of the Intel Pentium microprocessor family. The ARM machine language program can access the function of the bus interface unit through the new implementation-defined ARM coprocessor register to generate an input/output loop on the processor bus, that is, from the input/output bus to the input. One of the output spaces is a specific address to communicate with the system chipset. For example, an ARM machine language program can generate a specific cycle of SMI approval or an input/output loop for C state transitions. In one embodiment, the input and output address locations are assigned to the ARM R0 register. In one embodiment, the microprocessor 100 has power management capabilities, such as the well-known P-state and C-state management. ARM machine language program Power management can be performed through a new implementation of the ARM coprocessor register. In one embodiment, microprocessor 100 includes an encryption unit (not shown) that is located within execution pipeline 112. In one embodiment, the encryption unit is substantially similar to the encryption unit of the VIA microprocessor with Padlock security technology functionality. The ARM machine language program can obtain the functionality of an encryption unit, such as an encrypted instruction, through a new implementation-defined ARM coprocessor register. In one embodiment, the ARM coprocessor 5 is used for user mode functions typically performed by user mode applications, such as those produced using the technical features of the cryptographic unit.

When the microprocessor 100 executes the x86 ISA and ARM ISA machine language programs, each time the microprocessor 100 executes the x86 or ARM ISA instructions 124, the hardware instruction translator 104 performs a hardware translation. Conversely, a software-translated system can reuse the same translation across multiple events instead of repeatedly translating previously translated machine language instructions, thus helping to improve performance. In addition, the embodiment of Figure 8 uses microinstruction cache to avoid repeated translations that may occur each time the microprocessor executes the x86 or ARM ISA instructions 124. The manners described in the various embodiments of the present invention are in accordance with different program features and their execution environments, and thus indeed contribute to improved performance.

The branch predictor 114 accesses the history data of the x86 and ARM branch instructions that were previously executed. The branch predictor 114 analyzes whether the cache line obtained by the instruction cache 102 has x86 and ARM branch instructions and its target address based on the previous cache history data. In an embodiment, the cache history data includes a memory address of the branch instruction 124, a branch target address, a direction indicator, a type of branch instruction, and a branch instruction at the start of the cache line. A byte, and an indicator that shows whether it spans multiple cache lines. In an embodiment, the provisional application No. 61/473,067, "APPARATUS AND METHOD FOR USING BRANCH PREDICTION TO EFFICIENTLY EXECUTE CONDITIONAL NON-BRANCH INSTRUCTIONS", which is proposed on April 7, 2011, provides an improved branch predictor 114. The ability to make it possible to predict the direction of the ARM ISA conditional non-branch instruction. In one embodiment, the hardware instruction translator 104 includes a static branch predictor that predicts x86 and ARM branch instructions based on the execution code, the type of condition code, the backward or forward, and the like. The direction and branch target address.

The present invention also contemplates a variety of different embodiments to achieve a combination of different features of the x86 ISA and ARM ISA definitions. For example, in one embodiment, the microprocessor 100 implements the ARM, Thumb, ThumbEE, and Jazelle instruction set states, but provides a trivial implementation for the Jazelle extended instruction set; the microprocessor 100 implements The following extended instruction set includes: Thumb-2, VFPv3-D32, Advanced SIMD (Neon), multiple processing, and VMSA; but does not implement the following extended instruction set, including: security extension Fast content switching expansion, ARM debugging (ARM program can achieve x86 debugging function through ARM MCR/MRC instruction to new implementation definition coprocessor register), performance detection counter (ARM program can pass new real Define the coprocessor register to get the x86 performance counter). For example, in one embodiment, the microprocessor 100 treats the ARM SETEND instruction as a no-op (NOP) and only supports the Little-endian data format. In another embodiment, the microprocessor 100 does not implement the functionality of x86 SSE 4.2.

Consideration of the present invention a plurality of modified embodiments of the microprocessor 100 of the embodiment, for example, by the production of VIA Technologies, Inc., Taipei, Taiwan VIA Nano ^TM commercial microprocessor for improvement. This Nano microprocessor is capable of executing x86 ISA machine language programs, but cannot execute ARM ISA machine language programs. The Nano microprocessor includes high-performance register renaming (, super-scaling instruction technology, non-sequential execution pipeline and a hardware translator to translate x86 ISA instructions into microinstructions for execution pipeline execution. The present invention is for Nano hardware instructions The improved version of the translator, in addition to the translation of x86 machine language instructions, can also translate ARM ISA machine language instructions into micro-instructions for execution pipeline execution. Improvements to hardware instruction translators include improvements and complex instructions for simple instruction translators. The translator's improvements also include microcode. In addition, the microinstruction set can add new microinstructions to support translation between ARM ISA machine language instructions and microinstructions, and improve the execution pipeline to enable execution of new microinstructions. In addition, the Nano scratchpad file and memory subsystem can be improved to support the ARM ISA, including the sharing of specific scratchpads. The branch prediction unit can be improved to make it predictable on x86 branches. ARM branch instruction prediction. The advantage of this embodiment is that, because it is largely independent of ISA-agnostic restrictions, it is only necessary for Nano micro-location. The implementation pipeline of the processor can be applied to the ARM ISA instructions with minor modifications. The improvement of the execution pipeline includes the generation and use of the condition code flag, the semantics of the update and return instruction index register, and the access privileges. Protection methods, and a variety of memory management related functions, such as access violation detection, paging and translation lookaside buffer (TLB) use, and cache strategy, etc. The foregoing is merely illustrative, not limiting the invention, some of which Features will be further described in the following sections. Finally, as mentioned above, some of the features defined by x86 ISA and ARM ISA may not be supported by the previously unmodified embodiment of the Nano microprocessor, such as x86 SSE 4.2 and ARM. Security extensions, fast content switching extensions, debugging and performance counters, some of which will be further explained in the following sections. In addition, the previous release of the Nano processor is supported by the ARM ISA machine language program. Integrate design, test and manufacturing resources to complete single-integrated circuit products capable of executing x86 and ARM machine language programs For example, the single integrated circuit product product covers most of the existing machine language programs in the market, and conforms to the current market trend. The embodiment of the microprocessor 100 described herein can be substantially configured as an x86 microprocessor, ARM. A microprocessor, or both x86 ISA and ARM ISA machine language program microprocessors. This microprocessor can be used in x86 and ARM instruction modes on a single microprocessor 100 (or core 100 of Figure 7). Dynamic switching between 132 to achieve the ability to execute both x86 ISA and ARM ISA machine language programs. It is also possible to configure one or more cores of multi-core microprocessor 100 (corresponding to Figure 7) as ARM cores. Or multiple core configurations are x86 cores, that is, the ability to perform x86 ISA and ARM ISA machine language programs simultaneously by dynamically switching between x86 and ARM instructions on each core of the multi-core 100. In addition, the ARM ISA core is traditionally designed as the core of intellectual property and is being incorporated into its applications by third-party third-party vendors, such as system-on-a-chip and/or embedded applications. Therefore, the ARM ISA does not have a specific standard processor bus as the interface between the ARM core and other parts of the system, such as chipset or other peripherals. Advantageously, the Nano processor has a high speed x86 type processor bus as an interface to the memory and peripherals, and a memory coherency structure that cooperates with the microprocessor 100 to support the ARM ISA in an x86 computer system environment. Execution of machine language programs.

Referring to FIG. 2, the hardware command translator 104 of FIG. 1 is shown in detail in a block diagram. This hardware instruction translator 104 contains hardware, and more specifically, a collection of transistors. The hardware instruction translator 104 includes an instruction formatter 202 that receives the instruction mode indicator 132 and the blocks of the x86 ISA and ARM ISA instruction bytes 124 from the instruction cache 102 of FIG. 1 and outputs the formatted x86 ISA. And a simple instruction translator (SIT) 204 receives the instruction mode indicator 132 and the environment mode indicator 136, and outputs the execution microinstruction 244 and a microcode address 252; a complex instruction translator (CIT) 206 ( Also referred to as a microcode unit, receiving microcode address 252 and environment mode indicator 136, and providing execution microinstruction 246; and a multiplexer 212 having an input received by microinstruction 244 by simple instruction translator 204, The other input receives the microinstruction 246 by the complex instruction translator 206 and provides an execution pipeline 112 that executes the microinstructions 126 through FIG. Instruction formatter 202 will be described in more detail in Figure 3. The simple instruction translator 204 includes an x86 simple instruction translator 222 and an ARM simple instruction translator 224. The complex instruction translator 206 includes a microprogram counter 232 that receives the microcode address 252, a microcode counter 232 that receives the microcode read-only memory 234 of the read-only memory address 254, and a micro-program counter that updates the micro-program counter. The sequencer 236, an instruction indirection register (IIR) 235, and a microtranslator 237 for generating the microinstruction 246 output by the complex instruction translator. Implementation by the simple instruction translator 204 The microinstructions 244 and the execution microinstructions 246 generated by the complex instruction translator 206 are all microinstructions 126 of the microinstruction set of the microarchitecture of the microprocessor 100, and are all directly executable by the execution pipeline 112.

The multiplexer 212 is controlled by a select input 248. In general, multiplexer 212 will select microinstructions from simple instruction translator 204; however, when simple instruction translator 204 encounters a complex x86 or ARM ISA instruction 242, it transfers control or encounters traps. To transition to the complex instruction translator 206, the simple instruction translator 204 controls the selection input 248 to cause the multiplexer 212 to select the microinstructions 246 from the complex instruction translator. When the scratchpad configuration table (RAT) 402 (see FIG. 4) encounters a microinstruction 126 having a particular bit indicating that it is the last microinstruction 126 that implements the sequence of complex ISA instructions 242, the scratchpad configuration table 402 then selects control input 248 to cause multiplexer 212 to revert to selecting microinstruction 244 from simple instruction translator 204. In addition, when the rearrangement buffer 422 (see FIG. 4) is ready to cause the microinstruction 126 to retired and the state of the instruction indicates that a microinstruction from the complex instructor needs to be selected, the rearrangement buffer 422 controls the selection input 248 to The worker 212 selects the microinstructions 246 from the complex instruction translator 206. In the case where the microinstruction 126 needs to be retired, the microinstruction 126 has caused an exceptional condition to be generated.

The simple instruction translator 204 receives the ISA instructions 242 and treats these instructions as x86 ISA instructions for decoding when the instruction mode indicator 132 indicates x86, and treats these instructions as ARM ISA when the instruction mode indicator 132 indicates ARM. The instruction is decoded. The simple instruction translator 204 confirms that the ISA instruction 242 is a simple or complex ISA instruction. The simple instruction translator 204 can output all of the simple ISA instructions 242 The microinstruction 126 is implemented to implement the ISA instruction 242; that is, the complex instruction translator 206 does not provide any implementation microinstructions 126 to the simple ISA instruction 124. Conversely, the complex ISA instructions 124 require the complex instruction translator 206 to provide at least some, if not all, of the execution microinstructions 126. In one embodiment, for a subset of the instructions of the ARM and x86 ISA instruction sets 124, the simple instruction translator 204 outputs a portion of the microinstructions 244 that implement the x86/ARM ISA instructions 126, and then transfers control to complex instruction translations. The 206 is further processed by the complex instruction translator 206 to output the remaining microinstructions 246 to implement the x86/ARM ISA instructions 126. The multiplexer 212 is controlled to first provide the execution microinstructions 244 from the simple instruction translator 204 as microinstructions 126 provided to the execution pipeline 112, and then provide the execution microinstructions 246 from the complex instruction translator 206 as provided to the execution pipeline. 112 microinstructions 126. The simple instruction translator 204 is known to be executed by the hardware instruction translator 104 to generate an address of the starting microcode read memory 234 of the plurality of microcode programs that implement the microinstruction 126 for a plurality of different complex ISA instructions 124, And when the simple instruction translator 204 decodes a complex ISA instruction 242, the simple instruction translator 204 provides the corresponding microcode program address 252 to the microprogram counter 232 of the complex instruction translator 206. The simple instruction translator 204 outputs the microinstructions 244 required to implement a substantial proportion of the instructions 124 in the ARM and x86 ISA instruction sets, particularly for the ISA instructions 124 that are required to be executed more frequently by the x86 ISA and ARM ISA machine language programs. Only a relatively small number of instructions 124 need to be provided by the complex instruction translator 206 to implement the microinstructions 246. According to an embodiment, x86 instructions, such as RDMSR/WRMSR, CPUID, complex arithmetic instructions (such as FSQRT), are implemented primarily by complex instruction translator 206. Transcendental instructions, and IRET instructions; ARM instructions such as MCR, MRC, MSR, MRS, SRS, and RFE instructions implemented primarily by complex instruction translator 206. The above-listed instructions are not intended to limit the invention, but merely illustrate the types of ISA instructions that can be implemented by the complex instruction translator 206 of the present invention.

When instruction mode indicator 132 indicates x86, x86 simple instruction translator 222 decodes x86 ISA instruction 242 and translates it into execution microinstruction 244; when instruction mode indicator 132 indicates ARM, ARM simple instruction translator 224 for ARM The ISA instruction 242 decodes and translates it into a practice microinstruction 244. In one embodiment, the simple instruction translator 204 is a Boolean logic gate block that can be synthesized by conventional synthesis tools. In one embodiment, the x86 simple instruction translator 222 and the ARM simple instruction translator 224 are separate Boolean logic gate blocks; however, in another embodiment, the x86 simple instruction translator 222 and the ARM simple instruction translator 224 The system is located in the same Boolean logic gate block. In one embodiment, the simple instruction translator 204 translates up to three ISA instructions 242 and provides up to six execution microinstructions 244 to the execution pipeline 112 in a single clock cycle. In one embodiment, the simple instruction translator 204 includes three sub-translators (not shown), each sub-translator translating a single formatted ISA instruction 242, wherein the first inter-translator can translate no more than Three formatted ISA instructions 242 that implement microinstructions 126; the second translator can translate no more than two formatted ISA instructions 242 that implement microinstructions 126; the third interpreter can require no more than one translation The formatted ISA instruction 242 of the microinstruction 126 is implemented. In one embodiment, the simple instruction translator 204 includes a hardware state machine that is capable of outputting multiple fingers over multiple clock cycles. Let 244 implement an ISA instruction 242.

In one embodiment, the simple instruction translator 204 performs a plurality of different exception event detections in accordance with the instruction mode indicator 132 and/or the environmental mode indicator 136. For example, if the command mode indicator 132 indicates x86 and the x86 simple instruction translator 222 decodes an ISA instruction 124 that is invalid for the x86 ISA, the simple instruction translator 204 then generates an x86 invalid opcode exception event; Similarly, if the command mode indicator 132 indicates ARM and the ARM simple instruction translator 224 decodes an ISA instruction 124 that is invalid for the ARM ISA, the simple instruction translator 204 then generates an ARM undefined instruction exception event. In another embodiment, if the environmental mode indicator 136 indicates an x86 ISA, the simple instruction translator 204 then detects if each x86 ISA instruction 242 it encounters requires a particular privilege level, and if so, detects the current Whether the privilege level (CPL) satisfies the special privilege level required by this x86 ISA instruction 242 and generates an exception event when not satisfied; similarly, if the environment mode indicator 136 indicates an ARM ISA, the simple instruction translator 204 then detects if Each formatted ARM ISA instruction 242 requires a privileged mode instruction, and if so, whether the current mode is privileged mode and an exception condition is generated when the current mode is user mode. Complex instruction translator 206 also performs similar functions for specific complex ISA instructions 242.

Complex instruction translator 206 outputs a series of execution microinstructions 246 to multiplexer 212. The microcode read only memory 234 stores the read only memory command 247 of the microcode program. The microcode read-only memory 234 outputs a read-only memory command 247 in response to the next read-only memory reference obtained by the microcode-reading memory 234. The address of 247 is held by the microprogram counter 232. In general, the microprogram counter 232 receives its start value 252 by the simple instruction translator 204 in response to the decoding action of the simple instruction translator 204 for a complex ISA instruction 242. In other cases, such as responding to a reset or exception event, the microprogram counter 232 receives the reset microcode program bit or the appropriate microcode exception event processing address, respectively. Microprogrammer 236 typically updates microprogram counter 232 to a sequence of microcode programs and selectively updates to execution pipeline 112 in response to control microinstructions 126 (eg, branch instructions) in accordance with the size of read only memory instructions 247. The target address is validated for a branch that points to a non-program address within the microcode read-only memory 234. The microcode read only memory 234 is fabricated in a semiconductor wafer of the microprocessor 100.

In addition to the microinstructions 244 used to implement the simple ISA instructions 124 or portions of the complex ISA instructions 124, the simple instruction translator 204 also generates ISA instruction information 255 for writing to the instruction indirect registers 235. The ISA instruction information 255 stored in the instruction indirect register 235 contains information about the translated ISA instruction 124, for example, information identifying the source and destination registers specified by the ISA instruction, and the format of the ISA instruction 124, such as ISA. The instructions 124 are executed on one of the memory elements or in one of the architecture registers 106 of the microprocessor 100. This allows the microcode program to become versatile, i.e., does not require the use of different microcode programs for the various source and/or destination architecture registers 106. In particular, the simple instruction translator 204 knows the contents of the scratchpad file 106, including which registers are the shared registers 504, and can pass the scratchpad information provided in the x86 ISA and ARM ISA instructions 124 through the ISA instructions. The use of information 255 is translated to the appropriate register in the scratchpad file 106. ISA command information 255 contains a shift bar, a Immediate column, a constant column, renaming information of each source operand and microinstruction 126 itself, information for indicating the first and last microinstructions 126 in a series of microinstructions 126 of the ISA instruction 124, and storage by The other bits of the useful information collected by the hardware instruction translator 104 when the ISA instruction 124 was translated.

The micro translator 237 receives the read only memory instruction 247 from the contents of the microcode read only memory 234 and the indirect instruction register 235, and generates the execution microinstruction 246 accordingly. The micro-translator 237, based on the information received by the indirect instruction register 235, such as in accordance with the format of the ISA instruction 124 and its source and/or destination architecture register 106, specifies a particular read-only memory instruction 247. Translated into different microinstructions 246 series. In some embodiments, a number of ISA instruction messages 255 are combined with read-only memory instructions 247 to generate execution micro-instructions 246. In one embodiment, each of the read only memory instructions 247 is approximately 40 bits wide, and each microinstruction 246 is approximately 200 bits wide. In one embodiment, the micro-translator 237 can generate up to three micro-instructions 246 from one micro-read memory instruction 247. Micro-translator 237 includes a plurality of Boolean logic gates to generate execution microinstructions 246.

The advantage of using the micro-translator 237 is that since the simple instruction translator 204 itself generates the ISA instruction information 255, the microcode-reading memory 234 does not need to store the ISA instruction information 255 provided by the indirect instruction register 235, thereby reducing Reduce its size. In addition, because the microcode read-only memory 234 does not need to provide a separate program for each different ISA instruction format, and a combination of various source and/or destination architecture registers 106, the microcode read-only memory 234 program can Contains fewer conditional branch instructions. For example, if the complex ISA instruction 124 system memory format, simple instructions The translator 204 generates logic programming of the microinstruction 244, including the microinstruction 244 that loads the source operand from the memory into a temporary register 106, and the microtranslator 237 generates the microinstruction 246 to pass the result from the temporary register. 106 is stored to the memory. However, if the complex ISA instruction 124 is a register form, the logic programming moves the source operand from the source register specified by the ISA instruction 124 to the temporary register, and the micro translator 237 generates The microinstruction 246 is used to move the result from the temporary register to the architectural destination register 106 designated by the indirect instruction register 235. In one embodiment, the many aspects of the micro-translator 237 are similar to the application of U.S. Patent No. 12/766,244, filed on Apr. 23, 2010, which is incorporated herein by reference. However, the micro-translator 237 of this case has been modified to translate the ARM ISA instructions 124 in addition to the x86 ISA instructions 124.

It should be noted that the micro-program counter 232 is different from the ARM program counter 116 and the x86 command indicator 118, that is, the micro-program counter 232 does not hold the address of the ISA command 124, and the address held by the micro-program counter 232 is also Does not fall within the system memory address space. Moreover, more notably, the microinstructions 246 are generated by the hardware instruction translator 104 and are provided directly to the execution pipeline 112 for execution, rather than as an execution result 128 of the execution pipeline 112.

Please refer to FIG. 3, which illustrates the instruction formatter 202 of FIG. 2 in a block diagram. The instruction formatter 202 receives the x86 ISA and ARM ISA instruction byte 124 blocks from the instruction cache 102 of FIG. With the variable length of the x86 ISA instructions, the x86 instructions 124 can begin with any byte of the instruction byte 128 block. Because the x86 ISA allows the length of the first code byte to be affected by the current address length and the default value of the operand length. The task of confirming the length and location of the x86 ISA instructions in the cache block is more complicated. In addition, according to the current ARM instruction set state 322 and the ARM ISA instruction 124 opcode, the length of the ARM ISA instruction is not 2 bytes or 4 bytes, and thus is not 2-bit alignment or 4-bit alignment. Thus, the instruction formatter 202 fetches different x86 ISA and ARM ISA instructions from the instruction byte 124 stream, which is formed by the block received by the instruction cache 102. That is, the instruction formatter 202 formats the x86 ISA and ARM ISA instruction byte strings, thereby greatly simplifying the difficult task of decoding and translating the ISA instructions 124 by the simple instruction translator of FIG.

The instruction formatter 202 includes a predecoder 302 that, when the instruction mode indicator 132 indicates x86, pre-decodes the instruction byte 124 as an x86 instruction byte to generate pre-decoded information, in the instruction When mode indicator 132 is indicated as ARM, predecoder 302 pre-decodes instruction byte 124 as an ARM instruction byte to generate pre-decoded information. Instruction byte array (IBQ) 304 receives the ISA instruction byte 124 block and associated pre-decode information generated by pre-decoder 302.

An array of length decoders and chopping logic gates 306 receives the contents of the bottom entry of the instruction byte array 304, i.e., the ISA instruction byte 124 block and associated pre-decode information. The length decoder and chopping logic gate 306 also receives the command mode indicator 132 and the ARM ISA instruction set state 322. In one embodiment, the ARM ISA instruction set state 322 includes the J and T bits of the ARM ISA CPSR scratchpad. In response to its input information, the length decoder and chopping logic gate 306 generate decoding information that includes x86 within the block of the ISA instruction byte 124. With the length of the ARM instruction, the x86 first code information, and the metrics for each ISA instruction byte 124, this indicator indicates whether the byte is the starting byte, the terminating byte, and/or the ISA instruction 124. A valid byte. A multiplexer array 308 receives the ISA instruction byte 126 block, the associated pre-decode information generated by the predecoder 302, and the associated decoded information generated by the length decoder and the chop logic gate 306.

Control logic (not shown) examines the contents of the bottom item of the multiplexer queue (MQ) 308 and controls the multiplexer 312 to retrieve different or formatted ISA commands and associated pre-decode and decode information. The information is provided to a formatted command queue (FIQ) 314. The formatter command queue 314 acts as a buffer between the formatted ISA command 242 and the associated information provided to the simple instruction translator 204 of FIG. In one embodiment, multiplexer 312 retrieves up to three formatted ISA instructions and associated information in each clock cycle.

In one embodiment, the instruction formatting program 202 is similar in many respects to U.S. Patent Nos. 12/571,997, 12/572,002, 12/572,045, 12/572,024, issued October 1, 2009. The XIBQ, the instruction formatter, and the FIQ are disclosed in the application Serial No. 12/572,052, the disclosure of which is incorporated herein by reference. However, the XIBQ, the instruction formatter, and the FIQ are modified by the aforementioned patent application to enable formatting of the ARM ISA instructions 124 in addition to formatting the x86 ISA instructions 124. Length decoder 306 is modified to enable decoding of ARM ISA instructions 124 to produce length and start, end and validity byte metrics. In particular, if the command mode indicator 132 is indicated as an ARM ISA, the length decoder 306 detects the current ARM instruction set state 322 and the ARM ISA instruction 124 opcode to confirm the ARM finger. Let 124 be a 2-bit length or a 4-byte length instruction. In one embodiment, the length decoder 306 includes a plurality of independent length decoders for generating the length data of the x86 ISA instructions 124 and the length data of the ARM ISA instructions 124. The outputs of the independent length decoders are then connected. Wire-ORed are coupled together to provide an output to chopper logic gate 306. In one embodiment, the formatted command queue 314 includes separate queues to hold a plurality of separate portions of the formatted instructions 242. In one embodiment, the instruction formatter 202 provides a simple instruction translator 204 to at most three formatted ISA instructions 242 in a single clock cycle.

Referring to FIG. 4, the execution pipeline 112 of FIG. 1 is shown in detail in a block diagram. The execution pipeline 112 is coupled to the hardware instruction translator 104 to directly receive the hardware instruction translator 104 from FIG. The implementation of micro-instructions. The execution pipeline 112 includes a microinstruction queue 401 for receiving the microinstruction 126; a register configuration table 402 for receiving the microinstruction by the microinstruction queue 401; an instruction scheduler 404 coupled to the register configuration table 402 A plurality of reservation stations 406 are coupled to the instruction scheduler 404; an instruction transmission unit 408 is coupled to the reservation station 406; a reorder buffer 422 is coupled to the register configuration table 402, the instruction scheduler 404, and Retention station 406; and execution unit 424 is coupled to reservation station 406, instruction transmission unit 408, and reorder buffer 422. The scratchpad configuration table 402 and the execution unit 424 receive the command mode indicator 132.

In the case where the hardware instruction translator 104 generates a rate at which the microinstruction 126 is executed differently than the execution pipeline 112 executes the microinstruction 126, the microinstruction queue 401 acts as a buffer. In one embodiment, the microinstruction queue 401 includes an M to N compressible microinstruction queue. This compressible microinstruction queue enables execution pipeline 112 to be transferred from a hardware command within a given clock cycle. Translator 104 receives at most M (in one embodiment, M is six) microinstructions 126, and then stores the received microinstructions 126 to a queue of width N (in one embodiment, N is three) The structure is configured to provide up to N microinstructions 126 to the scratchpad configuration table 402 at each clock cycle, the scratchpad configuration table 402 being capable of processing up to N microinstructions 126 per clock cycle. The microinstruction queue 401 is compressible because it will sequentially fill the empty items of the queue by the microinstruction 126 transmitted by the hardware instruction translator 104 regardless of the particular clock cycle in which the microinstruction 126 is received. Therefore, it will not leave a void in the queue project. An advantage of this method is that the execution unit 424 can be fully utilized (see Figure 4) because it provides higher instruction storage performance than an instruction array of incompressible width M or width M. In particular, a queue of incompressible widths N would require a hardware instruction translator 104, particularly a simple instruction translator 204, to repeatedly translate one or more already preceding clock cycles during subsequent clock cycles. The ISA instruction 124 that has been translated. The reason for this is that the queue of incompressible width N cannot receive more than N microinstructions 126 in the same clock cycle, and repeated translations will result in power loss. However, the incompressible width M column does not require a simple instruction translator 204 to repeatedly translate, but it creates a void in the queue item and wastes, thus requiring more columns and a larger and more energy-consuming flaw. Columns provide considerable buffering power.

The register configuration table 402 receives the microinstructions 126 from the microinstruction queue 401 and generates ancillary information with the microinstructions 126 in progress in the microprocessor 100. The register configuration table 402 and the execution of the register renaming action are incremented. The instructions are processed in parallel to facilitate execution of the ultra-scaling, non-sequential execution capability of pipeline 112. If the ISA instruction 124 indicates x86, the scratchpad configuration table 402 Corresponding to the x86 ISA register 106 of the microprocessor 100, the auxiliary information is generated and the corresponding register rename operation is performed; otherwise, if the ISA command 124 is indicated as ARM, the register configuration table 402 corresponds to the micro The ARM ISA register 106 of the processor 100 generates the affiliate information and performs the corresponding scratchpad rename operation; however, as previously described, the portion of the scratchpad 106 may be shared by the x86 ISA and the ARM ISA. The scratchpad configuration table 402 also configures an entry in the reorder buffer 422 in accordance with the program order for each microinstruction 126, so the reorder buffer 422 can cause the microinstruction 126 and its associated x86 ISA and ARM ISA instructions 124 to be programmed. The retirement is performed sequentially, even though the execution of microinstruction 126 corresponds to the x86 ISA and ARM ISA instructions 124 that it is intended to implement in a non-sequential manner. The rearrangement buffer 422 includes a circular array of items for storing information about the in-progress microinstruction 126. The information includes, among other things, the microinstruction 126 execution status, a confirmation microinstruction. 126 is a tag translated by x86 or ARM ISA instructions 124 and a storage space for storing the results of microinstructions 126.

The instruction dispatcher 404 receives the scratchpad rename microinstruction 126 and the affiliate information from the scratchpad configuration table 402, and assigns the microinstruction 126 and its ancillary information to the appropriate one depending on the type of the instruction and the availability of the execution unit 424. Retention station 406 of execution unit 424. This execution unit 424 will execute the microinstruction 126.

For each microinstruction 126 that is waiting in the reservation station 406, the instruction issue unit 408 detects that the correlation execution unit 424 can be used and its ancillary information is satisfied (eg, the source operand can be used), ie, issues the microinstructions 126. Execution unit 424 is available for execution. As described above, the instruction issuing unit 408 issues The microinstructions 126 of the cloth can be executed out of order and in a super-scalar manner.

In an embodiment, execution unit 424 includes integer/branch unit 412, media unit 414, load/store unit 416, and floating point unit 418. Execution unit 424 executes microinstructions 126 to produce results 128 and provides them to reorder buffer 422. Although execution unit 424 is not greatly affected by the translation of microinstructions 126 that it executes by x86 or ARM ISA instructions 124, execution unit 424 will still use instruction mode indicator 132 and environment mode indicator 136 to perform relatively small. A subset of microinstructions 126. For example, execution pipeline 112 manages the generation of flags, the management of which is slightly different depending on the command mode indicator 132 indicating x86 ISA or ARM ISA, and the execution pipeline 112 is indicated by the command mode indicator 132 as x86 ISA or The ARM ISA updates the ARM condition code flag in the x86 EFLAGS register or in the Program Status Register (PSR). In another example, execution pipeline 112 samples instruction mode indicator 132 to determine whether to update x86 instruction index (IP) 118 or ARM program counter (PC) 116 or to update a common instruction address register. In addition, the execution pipeline 122 also uses this to determine whether to perform the aforementioned actions using x86 or ARM semantics. Once the microinstruction 126 becomes the oldest completed microinstruction 126 in the microprocessor 100 (i.e., in the top of the rearrangement buffer 422 queue and presents the completed state) and other to implement the associated ISA instruction 124 All microinstructions 126 have been completed and the reorder buffer 422 retires the ISA instruction 124 and releases the items associated with the microinstruction 126. In one embodiment, microprocessor 100 can retid up to three ISA instructions 124 in a clock cycle. An advantage of this processing method is that the execution pipeline 112 A high performance, general purpose execution engine that executes microinstructions 126 that support the microprocessor 100 microarchitecture of the x86 ISA and ARM ISA instructions 124.

Please refer to FIG. 5, which illustrates the register file 106 of FIG. 1 in a block diagram. In a preferred embodiment, the scratchpad file 106 is a separate scratchpad block entity. In one embodiment, the general purpose register is implemented by a register file entity having a plurality of read and write ports; other registers can be physically separate from the general register file and other Adjacent function blocks that access these registers but have fewer read writes. In an embodiment, some non-general-purpose scratchpads, especially those that do not directly control the hardware of the microprocessor 100 and only store the values that the microcode 234 will use (such as partial x86 MSR or ARM collaboration) The processor register is implemented in a private random access memory (PRAM) accessible by the microcode 234. However, x86 ISA and ARM ISA programmers cannot see this private random access memory, which means that this memory is not in the ISA system memory address space.

In summary, as shown in FIG. 5, the scratchpad file 106 is logically divided into three types, namely, an ARM-specific register 502, an x86-specific register 504, and a shared register 506. In one embodiment, the shared scratchpad 506 includes fifteen 32-bit scratchpads shared by the ARM ISA scratchpads R0 through R14 and the x86 ISA EAX through R14D registers, with an additional sixteen 128 bits. The meta-register is shared by the x86 ISA XMM0 to XMM15 registers and the ARM ISA Advanced Single Instruction Multiple Data Extension (Neon) register, which is partially overlapped by thirty-two 32-bit ARM VFPv3 Floating point register. As described in Figure 1 above, the sharing of the general purpose register means the number of writes to a shared register by the x86 ISA instruction 124. The value will be seen by the ARM ISA instruction 124 when subsequently reading the shared scratchpad, and vice versa. The advantage of this approach is that it enables the x86 ISA and ARM ISA programs to communicate with each other through the scratchpad. In addition, as described above, the specific bits of the x86 ISA and ARM ISA architecture control registers may also be referred to as shared registers 506. As described above, in one embodiment, the x86-specific model scratchpad can be accessed by the ARM ISA instruction 124 through the implementation-defined coprocessor register, and thus is shared by the x86 ISA and the ARM ISA. This shared scratchpad 506 can include non-architected scratchpads, such as non-architected equivalents of conditional flags, which are also renamed by the scratchpad configuration table 402. The hardware instruction translator 104 knows which register is shared by the x86 ISA and the ARM ISA, and thus executes the microinstruction 126 to access the correct register.

The ARM specific scratchpad 502 contains other scratchpads defined by the ARM ISA but not included in the shared scratchpad 506, while the x86 specific scratchpad 502 contains x86 ISA defined but not included in the shared scratchpad 506 other scratchpads. For example, the ARM-specific register 502 includes an ARM program counter 116, a CPSR, an SCTRL, an FPSCR, a CPACR, a coprocessor register, a banked general-purpose register for various exception event modes, and a program state save temporary. Saved program status registers (SPSRs) and so on. The ARM-specific registers 502 listed above are not intended to limit the invention, but are merely illustrative to illustrate the invention. In addition, for example, the x86-specific register 504 includes x86 instruction indicators (EIP or IP) 118, EFLAGS, R15D, 64-bit R0 to R32 registers above the 32-bit (ie, not falling under the share) Part of the register 506), sector register (SS, CS, DS, ES, FS, GS), x87 FPU register, MMX register, control System registers (such as CR0-CR3, CR8). The x86 specific registers 504 listed above are not intended to limit the invention, but are merely illustrative to illustrate the invention.

In one embodiment, the microprocessor 100 includes a new implementation-defined ARM coprocessor register, which, when the instruction mode indicator 132 indicates an ARM ISA, defines the coprocessor register to be accessible. Perform x86 ISA related operations. These operations include, but are not limited to, the ability to reset microprocessor 100 to an x86 ISA processor (reset to x86 instructions); initialize microprocessor 100 to an x86-specific state, switch command mode indicator 132 to x86 And begin to capture the ability of the x86 instruction 124 (boot to x86 instruction) on a particular x86 target address; the ability to access the aforementioned global configuration register; access to x86 specific registers (eg EFLAGS), This x86 register is specified in the ARM R0 register, accessing power management (such as P state and C state conversion), accessing processor bus functions (such as input/output cycles), and interrupt controller storage. Access and access to the encryption acceleration function. Moreover, in an embodiment, the microprocessor 100 includes a new x86 non-architectural specific model register that can be accessed to execute ARM when the instruction mode indicator 132 is indicated as an x86 ISA. ISA related operations. These operations include, but are not limited to, the ability to reset the microprocessor 100 to an ARM ISA processor (reset to ARM instructions); initialize the microprocessor 100 to an ARM-specific state, and switch the command mode indicator 132 to ARM. And the ability to capture ARM instructions 124 (start to ARM instructions) at a particular ARM target address; the ability to access the aforementioned global configuration registers; access to ARM specific registers (such as CPSR), This ARM register is specified in the EAX register.

Referring to Figures 6A and 6B, there is shown a flow chart illustrating the operation of the microprocessor 100 of Figure 1. This process begins in step 602.

As shown in step 602, the microprocessor 100 is reset. A reset signal can be sent to the reset input of microprocessor 100 to perform this reset action. Moreover, in one embodiment, the microprocessor bus is arranged in an x86 type processor bus, and the reset action can be performed by an x86 type INIT command. In response to this reset action, the reset procedure of the microcode 234 is invoked to execute. The action of resetting the microcode includes: (1) initializing the x86 specific state 504 to a preset value specified by the x86 ISA; (2) initializing the ARM specific state 502 to a preset value specified by the ARM ISA; 3) Initializing the non-ISA-specific state of the microprocessor 100 to a preset value specified by the microprocessor 100 manufacturer; (4) initializing the shared ISA state 506, such as GPRs, to a preset value specified by the x86 ISA And (5) setting the command mode indicator 132 and the environmental mode indicator 136 to indicate the x86 ISA. In another embodiment, unlike the pre-launch actions (4) and (5), the reset microcode initializes the shared ISA state 506 to an ARM ISA-specific preset value and directs the command mode indicator 132 to the environmental mode indicator. 136 is set to indicate the ARM ISA. In this embodiment, the actions of steps 638 and 642 need not be performed, and prior to step 614, the reset microcode initializes the shared ISA state 506 to the preset value specified by the x86 ISA and will mode the command. Indicator 132 and environmental mode indicator 136 are set to indicate the x86 ISA. Next, proceed to step 604.

At step 604, the reset microcode confirms that the microprocessor 100 is configured as an x86 processor or an ARM processor to boot. In an embodiment, as described above, the preset ISA boot mode is hard coded in the microcode. However, it can be modified by blowing the fuse configuration or by using a microcode patch. In one embodiment, the preset ISA boot mode is provided as an external input to the microprocessor 100, such as an external input pin. Next, proceed to step 606. In step 606, if the default ISA boot mode is x86, then step 614 is entered; otherwise, if the default boot mode is ARM, then step 638 is entered.

In step 614, resetting the microcode causes microprocessor 100 to begin the x86 instruction 124 by the reset vector address specified by the x86 ISA. Next, proceed to step 616.

In step 616, the x86 system software (e.g., BIOS) configures the microprocessor 100 to use, for example, the x86 ISA RDMSR and WRMSR instructions 124. Next, proceed to step 618.

In step 618, the x86 system software executes an instruction 124 to reset to the ARM. This reset to ARM instruction causes the microprocessor 100 to reset and exit the reset procedure in the state of an ARM processor. However, because the x86 specific state 504 and the non-ISA specific configuration state are not changed by the instruction 126 reset to the ARM, this approach facilitates the x86 system firmware to perform the preliminary setup of the microprocessor 100 and the microprocessor 100 It is then rebooted in the state of the ARM processor, while still allowing the non-ARM configuration of the microprocessor 100 executed by the x86 system software to remain intact. In this way, the method can use the "small" micro boot code to execute the boot process of the ARM operating system without using the micro boot code to solve the complicated problem of how to configure the microprocessor 100. In one embodiment, this reset to the ARM instruction is an x86 WRMSR instruction to a new non-architectural specific model register. Next, proceed to step 622.

At step 622, the simple instruction translator 204 enters the trap to reset the microcode in response to a complex reset to ARM (complex reset-to-ARM) instruction 124. This reset microcode initializes the ARM specific state 502 to a preset value specified by the ARM ISA. However, resetting the microcode does not modify the non-ISA specific state of the microprocessor 100, thus facilitating the saving of the configuration settings required for execution of step 616. In addition, resetting the microcode causes the shared ISA state 506 to be initialized to a preset value specified by the ARM ISA. Finally, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the ARM ISA. Next, proceed to step 624.

In step 624, resetting the microcode causes microprocessor 100 to begin fetching ARM instruction 124 at the address specified by the x86 ISA EDX:EAX register. The process ends at step 624.

In step 638, the reset microcode will share the ISA state 506, such as GPRs, to the preset value specified by the ARM ISA. Next, proceed to step 642.

In step 642, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the ARM ISA. Next, proceed to step 644.

In step 644, resetting the microcode causes the microprocessor 100 to begin fetching the ARM instruction 124 at the reset vector address specified by the ARM ISA. This ARM ISA defines two reset vector addresses and can be selected by an input. In one embodiment, microprocessor 100 includes an external input to select between two ARM ISA defined reset vector addresses. In another embodiment, the microcode 234 includes a preset selection between two ARM ISA defined reset vector addresses, which can be modified by blowing fuses and/or microcode patching. . Next, proceed to step 646.

In step 646, the ARM system software sets up the microprocessor 100 to use specific instructions, such as the ARM ISA MCR and MRC instructions 124. Next, proceed to step 648.

In step 648, the ARM system software executes a reset 124 to x86 instruction to reset the microprocessor 100 and exit the reset procedure in an x86 processor state. However, because the ARM-specific state 502 and the non-ISA-specific configuration state are not changed by the instruction 126 reset to x86, this approach facilitates the ARM system firmware to perform the preliminary setup of the microprocessor 100 and the microprocessor 100 It is then rebooted in the state of the x86 processor while still maintaining the non-x86 configuration of the microprocessor 100 executed by the ARM system software intact. In this way, the method can use the "small" micro boot code to execute the boot process of the x86 operating system without using the micro boot code to solve the complicated problem of how to configure the microprocessor 100. In one embodiment, this reset to the x86 instruction is an ARM MRC/MRCC instruction to a new implementation-defined coprocessor register. Next, proceed to step 652.

In step 652, the simple instruction translator 204 enters the trap to reset the microcode in response to the complex reset to x86 instruction 124. Resetting the microcode initializes the x86 specific state 504 to the preset value specified by the x86 ISA. However, resetting the microcode does not modify the non-ISA specific state of the microprocessor 100, which facilitates saving the configuration settings performed at step 646. In addition, resetting the microcode causes the shared ISA state 506 to be initialized to a preset value specified by the x86 ISA. Finally, the microcode set command mode indicator 132 and the ambient mode indicator 136 are reset to indicate the x86 ISA. Next, proceed to step 654.

In step 654, resetting the microcode causes microprocessor 100 to begin fetching ARM instruction 124 at the address specified by the ARM ISA R1:R0 register. This stream The process terminates at step 654.

Referring to Figure 7, a dual core microprocessor 700 of the present invention is illustrated in a block diagram. The dual core microprocessor 700 includes two processing cores 100, each of which includes the components of the microprocessor 100 of FIG. 1, whereby each core can execute x86 ISA and ARM ISA machine language programs. These cores 100 can be configured such that both cores 100 execute x86 ISA programs, both cores 100 execute ARM ISA programs, or one core 100 executes x86 ISA programs and the other core 100 executes ARM ISA programs. During the operation of the microprocessor 700, the aforementioned three settings may be mixed and dynamically changed. As described in the description of FIG. 6A and FIG. 6B, each core 100 has a preset value for its command mode indicator 132 and the environment mode indicator 136, and the preset value can be modified by using fuse or microcode patching. Thereby, each core 100 can be independently changed to an x86 or ARM processor through a reset. Although the embodiment of Figure 7 has only two cores 100, in other embodiments, the microprocessor 700 can have more than two cores 100, and each core can execute x86 ISA and ARM ISA machine language programs.

Referring to FIG. 8, a block diagram of a microprocessor 100 emulating an x86 ISA and ARM ISA machine language program according to another embodiment of the present invention is illustrated. The microprocessor 100 of Figure 8 is similar to the microprocessor 100 of Figure 1, in which the components are similar. However, the microprocessor 100 of FIG. 8 also includes a microinstruction cache 892 that accesses the microinstructions 126 generated by the hardware instruction translator 104 and provided directly to the execution pipeline 112. The microinstruction cache 892 is indexed by the retrieved address generated by the instruction fetch unit 114. If the capture address 134 hits the micro-instruction cache 892, The multiplexer (not shown) in row pipeline 112 selects microinstruction 126 from microinstruction cache 892 instead of microinstruction 126 from hardware instruction translator 104; conversely, the multiplexer is selected directly by The microinstruction 126 provided by the hardware instruction translator 104. Micro-instruction cache operations, also commonly referred to as trace caches, are techniques well known in the art of microprocessor design. The advantage of microinstruction cache 892 is that the time required to retrieve microinstruction 126 by microinstruction cache 892 is typically less than the instruction fetch 124 by instruction fetch 102 and is translated using a hardware instruction interpreter. The time for the microinstruction 126. In the embodiment of FIG. 8, when the microprocessor 100 executes an x86 or ARM ISA machine language program, the hardware instruction translator 104 does not need to perform a hardware translation every time the x86 or ARM ISA instruction 124 is executed. That is, when the execution microinstruction 126 already exists in the microinstruction cache 892, there is no need to perform a hardware translation.

An advantage of an embodiment of the microprocessor described herein is that it can execute x86 ISA and ARM ISA through a built-in hardware instruction translator to translate x86 ISA and ARM ISA instructions into microinstructions of the microinstruction set. A machine language program that differs from the x86 ISA and ARM ISA instruction sets, and the microinstructions can be executed using a shared execution pipeline of the microprocessor to provide execution microinstructions. An advantage of the embodiment of the microprocessor described herein is that the microprocessor is designed and manufactured by cooperatively utilizing a large number of micro-instructions that are hard-translated by the x86 ISA and ARM ISA instructions with the ISA execution pipeline. The resources will be less than two independently designed microprocessors (that is, one capable of executing an x86 ISA machine language program, one capable of executing an ARM ISA machine language program). Moreover, embodiments of these microprocessors, especially those that use ultra-pure quantities of non-sequential execution pipelines The processor has the potential to provide higher performance than existing ARM ISA processors. In addition, embodiments of these microprocessors offer greater potential for higher performance in x86 and ARM implementations than systems employing software interpreters. Finally, because the microprocessor can execute x86 ISA and ARM ISA machine language programs, this microprocessor facilitates the construction of a system that can efficiently execute both x86 and ARM machine language programs.

Backup scratchpad simulation

The ARM ISA includes a feature of a backup scratchpad, as shown in Table 3, which is extracted from Figure B1-1 on page B1-9 of the ARM programmer's manual. In Section B1, a system-level program developer model for the ARM ISA core is described, which contains a detailed layout of the ARM core scratchpad and backup scratchpad. As described in Section B1.3.2 of the ARM Program Developer's Manual: The application hierarchy of the ARM scratchpad file as described in the ARM Core Register on page A2-11. This architecture provides 16 ARM core registers, namely R0-R15, which includes Stack Pointer (SP), Link Register (LR) and Program Counter (Program Counter, PC). The registers are selected from a total of 31 or 33 registers, depending on whether a security extension is implemented. As shown in Figure B1-1, the current execution mode determines the group selection of the scratchpad. The display of the scratchpad is based on the selection of the current execution mode, and the contents of some registers are reworked. This setting is called a scratchpad backup, and the scratchpad of this rework is called a backup scratchpad.

So as shown in Table 3, the core of an ARM ISA may perform one of eight different execution modes. The execution mode can also be referred to as a processing mode or an operation method. The application level program is executed in user mode and cannot access protected system resources, and the execution mode cannot be switched unless an exception event occurs. In contrast, the other seven modes are collectively referred to as privileged mode, which has access to system resources and is free to change the core processing mode. The six of the privileged modes are called the exception event mode, which enters the mode when there are exception events, and the seventh mode of the privileged mode is the system mode. Entering this mode is not because of the exception event, which is usually Because one finger Let it enter and enter.

As can be seen from the foregoing Table 3, the ARM ISA includes 16 general-purpose core registers R0-R15 for supplying the user program in a hierarchical mode. The R13-R15 registers have their exclusive uses: R13 is the stack register (SP); R14 is the link register (LR); and R15 is the program counter (PC). These 16 identical general-purpose registers are available to the operating system in the system mode.

In the six exception event modes, as shown in Table 3, each mode has a backup version associated with the SP and LR registers to avoid the SP and LR registers being corrupted by exceptions encountered during use. That is, when an exception event is encountered, the core accesses the SP and LR registers associated with the exception event mode, rather than the SP and LR registers in user mode (or another exception mode). SP and LR register). More specifically, when an exception event is encountered, the core stores an exception event return address specific to the exception event in the LR register, wherein the LR register is associated with an exception event pattern of the exception event encountered (eg, LR_abt) instead of storing the LR register (LR_usr) in the user mode. In addition, when an exception event manager's instruction accesses the SP or LR register, the core accesses the backup version of the SP or LR register associated with the exception event (unless otherwise explicitly specified by the directive), rather than using SP mode and LR register (or SP and LR register in another exception mode). For example, a Branch that includes a link instruction executed in an administrator mode places the address of the next instruction in the LR_svc register instead of the LR_ust register. In another example, executing one of the Push or Pop instructions in IRQ mode will use the SP_irq register instead of the SP_usr register to store in memory. Stacking related to one of the IRQ exception event modes instead of accessing the user mode stack (assuming that the SP_irq register has been accessed according to the initialization of the operating system, accessing different memory stacks instead of user mode stacking) ).

In addition, the FIQ mode has a backup version of the R8-R12 scratchpad, which allows the FIQ interrupt management program to avoid having to save and reply to the R8-R12 register from the memory, so the FIQ interrupt management program will execute faster than others. The exception event handler comes quickly. When the instruction of the FIQ exception event handler accesses the R8-R12 register, the core accesses the FIQ backup version of R8-R12 (as indicated in Table 3, R8_fiq to R12_fiq) (unless the instruction is otherwise specified) R8-R12 scratchpad instead of user mode. For example, an Add instruction that accesses the R10 register in FIQ mode accesses the R10_fiq register instead of the R10_user register. Therefore, the security-expanded ISA ARM core will select a related monitoring mode backup register from a group of 33 temporary registers, including: 16 user mode registers, related to each of the six exception event modes. SP and LR scratchpad backup versions, and R8-R12 backup versions related to FIQ mode; conversely, the ARM ISA core without security extension will select the relevant monitoring mode from a total of 31 registers. Back up the scratchpad, which means that it does not contain the LR_mon and SP_mon registers.

Finally, the ARM ISA assigned to the Current Program Status Register (CPSR) contains condition code flags, execution status bits, exception event mask bits, and bits that define the current processing mode. The mode of the CPSR application level program is called the Application Program Status Register (APSR) and only provides the access condition code flag. Each exception has its own CPSR backup The version is as shown in Table 3 above. When an exception event is encountered, a copy of the CPSR value is written into the SPSR associated with the entered exception event. This allows the exception manager to recover from the exception event and restore the CPSR to the value before the exception event to view the value of the CPSR when the exception occurred.

Figure 9 is a conventional embodiment in which the ARM ISA general-purpose register is implemented as a hardware register 906, and the hardware register 906 is located in the hardware including the ARM ISA exception event mode backup register. The scratchpad file 902 (the computer is not shown in the figure). As shown in FIG. 9, the scratchpad file 902 includes a hardware multiplex logic gate 908 that is based on the current processing mode 914 to select the appropriate version of the R8 through R12 registers and the appropriate versions of the R13 and R14 registers. The additional hardware multiplex logic gate 904 is based on the register address 912 specified by the instruction to select the register specified to execute the instruction. (A general scratchpad file is implemented as a multi-register register file, which includes two load files and one write file, so that an instruction can specify two source operation elements and a destination operation element, so the hardware The multiplexed logic gates 908 and 904 can be repeatedly set three times, each corresponding to one). An embodiment can combine the operational mode hardware multiplex logic gate 908 with the scratchpad address hardware multiplex logic gate 904; however, such The method requires additional complexity, transistors, and power components in processing mode 914 to enable the selection of the scratchpad.

Typically, the processor executes a number of instructions (sometimes in the thousands) in one of the provided processing modes, and when an exception event mode occurs or a mode switching instruction is executed to switch to the new processing mode, then many instructions are executed A new processing mode, followed by a new mode switch and so on. Almost (if not all) of all executed instruction accesses contain backup versions Universal register 902 of R8-R14. According to the conventional embodiment, each access to the general-purpose register file passes through the hardware multiplex logic gate 908 as shown in FIG. 9 to select a suitable backup register (R8-R14 register) It increases the delay of each access connection to the provisioning staging file 902. This phenomenon also occurs on relatively less frequent processing mode switching, as well as access to backup registers that are less frequently accessed by the user mode register. In other words, even if the selection input 914 to the hardware multiplex logic gate 908 is less frequently updated, the operation of accessing the register file 902 for each instruction execution will result in the hardware multiplex processor 908. delay. Basically, accessing the scratchpad file 902 is a critical hardware timing path for the processor, which may require lowering the core clock or cutting the higher access portion into a lower frequency binning window. (bin). Therefore, there is a need for a solution that avoids the delay of the hardware multiplex logic gate 908.

The microprocessor provided in this embodiment provides an improved ARM ISA Universal Scratchpad file (the rest are the same), since the microprocessor is simplified in the hardware multiplex logic gate and is different based on the processing mode input. The way to choose the appropriate register, so it has better access performance than the traditional general temporary file. In addition, the backup version of R8-R14 described in this embodiment is simulated, instead of actually existing in the scratchpad file (this register file directly provides the operation unit to the execution unit of the microprocessor), so only A separate physical register R8-R14 exists in the scratchpad file. More specifically, the microprocessor includes an indirect storage to place the simulated file. In another embodiment, the indirect storage is a private random access memory that is included in a memory subsystem of the microprocessor. In order to respond to the processing mode switching, the value of the hardware register R13-R14 (or R8-R14, if switched to FIQ mode) is stored in the indirect storage in relation to the old processing mode, and the hardware registers R13-R14 (or R8-R14, if switched to FIQ mode) are then in the new processing mode. Reply to the relevant location in the indirect storage. In addition, in the case of switching to the FIQ mode, the contents of R8-R12 are stored to the global indirect storage, and in the case of switching from the FIQ mode, the contents are replied by the global indirect storage. It should be noted that the operation of storing and replying is performed using the microcode of the microprocessor. Thus, the subsequent execution unit is a single copy of R8-R14 from the direct register file, accessing the value associated with the new processing mode. Therefore, conceptually, the advantage of this embodiment is that relatively less frequent intra-mode switching is performed through a virtual multiplexer, rather than frequently executing each temporary storage through a physical multiplexer. take. Another advantage of this embodiment is that since the switching of processing modes is relatively infrequent, additional costs associated with mode switching are used at the expense of other benefits, such as lack of associated hardware multiplex logic gates and Based on the selection of multiple mode registers for processing mode input, faster register file access and the like can be performed.

Please refer to FIG. 10, which is a block diagram of the system of the present invention, showing the microprocessor of FIG. 1 in detail. As previously described, the microprocessor 100 of the micro-architecture is similar in many respects to the system processor VIA Nano ^TM VIA being fabricated, but has been modified to support embodiments ARM ISA, more particularly, to simulate Backup servlet mode for ARM ISA.

The microprocessor 100 includes: a register file 106 as shown in FIG. 1 , which is labeled as a direct storage 106 in FIG. 10; and multiplexers 1014 , 1016 and 1018 are coupled to the direct storage 106 for receiving direct Storage 106 Outputs; multiplexers 1004, 1006, and 1008 are coupled to multiplexers 1014, 1016, and 1018 to receive outputs of multiplexers 1014, 1016, and 1018; load unit 416, storage unit 416, and FIG. The integer/branch unit, media unit and floating point unit 412/414/418 (referred to as ALU unit 412/414/418 in FIG. 10) are respectively coupled to multiplexers 1004, 1006 and 1008 for receiving The output of the multiplexers 1004, 1006, and 1008; the rearrangement buffer (ROB) 422 of FIG. 4 is coupled to the loading unit 416, the storage unit 416, and the ALU unit 412/414/418 to receive the loading unit 416. The storage unit 416 and the result 128 of the ALU unit 412/414/418; and the indirect storage 1002, the indirect storage 1002 is coupled to the rearrangement buffer 422 and the multiplexer 1008 for receiving from the rearrangement buffer 422 The result 128 of the microinstruction 126, and its output is passed to the multiplexer 1008 as an input.

The reorder buffer 422 retains the result 128 of the microinstruction 126 and renames the rename registers thereto until the result 128 is retired to the architectural register. Each multiplexer 1014/1016/1018 selects an operand from the direct store 106 based on the register address associated with the microinstruction 126. Each multiplexer 1004/1006/1008 is based on an operand type assigned to microinstruction 126 to select an operand from its input source. Although only one set of operand multiplexer pairs is displayed in each execution unit, 1014 corresponds to 1004, 1016 pairs 1006 and 1018 pairs 1008, it is to be understood that a multiplexer pair exists in each source operation unit and each execution. Between units. Moreover, in addition to being coupled to the outputs of the multiplexers 1014/1016/1018, respectively, the multiplexers 1004, 1006, 1008 are coupled to each of the execution units to receive the results 128 from the respective execution units, and are stored in the rearrangement buffer. The result in 422 is 128. this In addition, load unit 416 also receives the output of indirect storage 1002 from multiplexer 1008. An advantage of the present invention is that when processing mode switching, in order to emulate an ARM ISA backup scratchpad, the microprocessor 100 can use the microcode 234 to store or restore values between the direct storage 106 or the indirect storage 1002, as will be The way it works is further described.

As shown in FIG. 10, the direct memory 106 includes a plurality of registers to store data or operands for use by the ARM R0-R14 general purpose register. Although the general purpose register residing in the physical scratchpad file is different from the CPSR (and from the PC), the direct storage 106 still contains a register for storing the CPSR. In one embodiment, a hardware scratchpad file contains a direct storage 106.

The indirect storage 1002 includes R13, R14 and SPSR storage, which are related to the processing mode of each ARM ISA, that is, User, Manager (SVC), Termination (ABT), Undefined (UND), IRQ and FIQ processing mode. In addition, indirect storage 1002 includes R8-R12 storage associated with the FIQ processing mode. Finally, in addition to the FIQ mode, the indirect storage 1002 contains all processing modes associated with the global domain (GLOBAL). The use of these different memory addresses contained in the indirect storage 1002 will be described later.

In one embodiment, the indirect storage 1002 includes a private random access memory (PRAM) belonging to one of the memory subsystems 108. As previously described, the PRAM is addressed using the microcode 234 as shown in FIG. 2, but This operation is invisible to the x86 ISA and ARM ISA programmers, that is, it does not exist in the ISA system memory address space. PRAM implementation as described in U.S. Patent No. 7,827,390, issued Feb. 11, 2010. In the example, it is hereby incorporated by reference. In particular, the indirect storage 1002 can only be loaded using the load unit 416 and can only be stored using the storage unit 416. More specifically, the indirect storage 1002 can only be executed by the load unit 416 by the load micro-instruction 126 of the inter-storage storage 1002 (here, which corresponds to the load_PRAM micro-instruction), and the inter-bank storage executed by the storage unit 416. The store microinstruction 126 of 1002 (here corresponding to the store_PRAM microinstruction) is addressed. Therefore, other execution units 411/414/418 cannot be loaded or written to the indirect storage 1002. The load_PRAM microinstruction instructs the load unit 416 to load data from one of the specified addresses in the indirect storage 1002 to a particular register of the scratchpad file 106, which may be as shown in FIG. An architectural register may be accessed by microcode 234 as one of the non-architected registers (also referred to as a temporary register). Conversely, the store_PRAM microinstruction instruction storage unit 416 stores a data from one of the temporary registers in the scratchpad file 106 to one of the specified addresses in the indirect storage 1002.

Referring to FIGS. 11A and 11B, FIGS. 11A and 11B are flowcharts showing the operation of the microprocessor 100 in FIG. 10 of the present invention, the flow beginning at step 1102.

In step 1102, the hardware command translator 104 detects a request to switch from the current processing mode to the new processing mode, and responsively enters the trap and proceeds to the appropriate program in the microcode 234 of FIG. 2, which is used for setting. The requirement to manage the processing mode switching. The command translator 104 can detect the switching processing mode requirements in different ways, but is not limited to the methods described below. First, the instruction translator 104 may encounter an ISA instruction 124 that explicitly requires a switch processing mode, such as an ARM ISA switch processing status instruction. (CPS), Manager Call (SVC) command, Security Monitor Call (SMC) command or move to Special Register (MSR). Second, the instruction translator 104 may encounter an ISA instruction 124 that implicitly handles mode switching requirements, such as an ARM ISA self-exception event return (RFE) instruction, load multiple (from exception event return), SUBS PC, LR, or breakpoint ( BKPT) instruction. Third, the instruction translator 104 may encounter an undefined ISA instruction 124 caused by an Undefined instruction exception. Fourth, the instruction translator 104 may receive a signal from the microprocessor 100 of another unit that an exception event has been encountered. For example, the instruction translator 104 may receive a signal from a memory subsystem (not shown) of the microprocessor 100 indicating that an instruction requires an access action that is not in access rights, such as when processing micro-processing When a device is not in a privileged mode but requests access to a privileged access memory block, a Data Abort exception condition is established; or when an instruction is fetched and requested When an invalid instruction is executed, the instruction translator 104 may receive an indication that a memory termination has occurred and establish a prefetching exception condition (Prefetch Abort exception condition); or the instruction translator 104 may be from the microprocessor 100. The bus interface unit receives a signal indicating that an interrupt operation (IRQ or FIQ) is required. Fifth, the instruction translator 104 may encounter an x86 RDMSR/WRMSR instruction 124, or x86 launch-ARM, for accessing the global configuration register 122 as previously described, or reset-to as previously described. -ARM instruction 124. The microcode 234 performs a number of actions based on the type of the particular mode transition, such as preparing to update the interrupt mask bit, the condition flag, or other bits in the CPSR. Also, at the step Prior to 1114 updating the direct memory 106 CPSR, the microcode 234 can store the current direct memory 106 CPSR value to the location of the SPSR in the indirect register 1002 that is associated with the new processing mode. Further, the ARM SIT 224 can perform other actions before entering the trap to the microcode 234. For example, in the case of the ARM ISA LDM (Self-Exception Event Reply) instruction 124, the ARM SIT 224 can send a load micro-instruction 126 to request that a particular scratchpad be loaded from the memory, and then proceeds to step 1104.

In step 1104, the microcode 234 determines whether the new processing mode required in step 1102 is the same as the current processing mode. If the same, the flow ends; if not, the process proceeds to step 1106.

At step 1106, the microcode 234 stores the values of the registers R13 and R14 of the direct memory 106 in the indirect storage 1002 in relation to the location corresponding to the current processing mode. For example, if the current processing mode is the manager mode, the microcode 234 stores the value of R13/R14 of the direct memory 106 to the location of R13/R14 in the SVC portion of the indirect storage 1002, as indicated by the arrow in FIG. (1) shown. In another example, if the current processing mode is FIQ mode, the microcode 234 stores the R13/R14 value of the direct memory 106 to the R13/R14 position of the FIQ portion of the indirect storage 1002, as indicated by the arrow in FIG. (5) is shown. Advantageously, the microcode can include a sequence of store_PRAM microinstructions 126 to store values from the direct store 106 to the indirect storage 1002. Then proceed to step 1108.

At step 1108, the microcode 234 determines if the current processing mode is the FIQ processing mode, and if so, proceeds to step 1112; otherwise, proceeds to step 1114.

At step 1112, the microcode 234 will directly store the register of the memory 106. The value of R8-R12 is stored in the indirect storage 1002 in relation to the position corresponding to the FIQ mode, as indicated by the arrow (6) in Fig. 12. In addition, the microcode 234 returns the value of the non-FIQ mode associated with the global domain in the indirect storage 1002 to the registers R8-R12 of the direct storage 106, as indicated by arrow (7) in FIG. Advantageously, the microcode that performs the reply may include a sequence of load_PRAM microinstructions 126 to load values from the indirect storage 1002 to the direct store 106. Then proceed to step 1114.

In step 1114, the microcode 234 updates the mode bit of the CPSR 106 with the new processing mode required in step 1102. The writing of CPSR 106 further includes updates to other bits of CPSR 106 next to the mode bits. Then proceed to step 1116.

In step 1116, the microcode 234 returns the value of the indirect storage 1002 associated with the corresponding location of the new processing mode to the R13 and R14 registers of the direct storage 106. For example, if the new processing mode is FIQ mode, the microcode 234 returns the value of the R13/R14 position of the FIQ portion of the indirect storage 1002 to the R13/R14 of the direct storage 106, as indicated by the arrow in FIG. ) shown. For example, if the new processing mode is the UND mode, the microcode 234 returns the value of the R13/R14 position of the UND portion of the indirect storage to the R13/R14 of the direct storage 106, as indicated by the arrow (8) in FIG. Show. Then proceed to step 1118.

At step 1118, the microcode 234 determines if the new processing mode is FIQ mode, and if so, proceeds to step 1122; otherwise, proceeds to step 1124.

At step 1122, the microcode 234 stores the value of the R8-R12 register of the direct memory 106 to a location in the indirect storage 1002 that is associated with the non-FIQ mode of the global domain, as indicated by arrow (3) in FIG. Shown. In addition, The microcode 234 returns from the corresponding position value of the FIQ mode in the indirect storage 1002 to the R8-R12 register of the direct storage 106, as indicated by the arrow (4) in Fig. 12, and proceeds to step 1124.

In step 1124, the microcode 234 performs more actions based on the particular mode switch type. For example, if an exception event occurs, the microcode 234 fills an updated value into the R14 temporary storage of the direct memory 106. In the device (that is, the LR register), the updated value is based on the B1-3 in the ARM manual and the table B1-4 in the B1-35 page, and then jump to the typical exception event management program. Control is also returned to the ARM ISA program. The process ends at step 1124.

It can be observed from Fig. 12 that even if a switching from the first processing mode (e.g., SVC) to the FIQ mode is performed, then switching to the third processing mode (e.g., UND) is performed without immediately returning to the first processing mode. In this case, the advantage of using the location of the global indirect storage 1002 is that the microprocessor 100 can still maintain the correct value in the R8-R12 register of the direct storage 106, thereby emulating the ARM ISA backup register.

As can be seen from the foregoing, a blueprint for the simulation of the ARM ISA backup register is as follows. When the microprocessor 100 switches to a new processing mode, the microprocessor 100 stores the correct value in the direct memory 106, which is a backup register for the new processing mode in the conventional ARM processor. For example, after switching to the FIQ mode, the R0-R14 register of the direct memory 106 has the contents of R0_usr-R7_usr and R8_fiq-R14_fiq of the conventional ARM processor. Therefore, the arithmetic elements of the FIQ processing mode can be directly supplied to the ALU unit 412/414/418 from the direct memory 106 to enable the microprocessor 100 (i.e., FIQ) in the FIQ mode. The exception event manager command) can execute microinstructions 126 that are translated from the ARM ISA data processing instructions 124. In another example, after switching to the UND mode, the R0-R14 register of the direct memory 106 will have the contents of the R0_usr-R12_usr and R13_und-R14_und of the conventional ARM processor, and therefore, the operand of the UND processing mode The ALU unit 412/414/418 can be supplied directly from the direct storage 106 such that the microprocessor 100 in UND mode can execute the microinstructions 126 that are translated from the ARM ISA data processing instructions 124. In order to achieve this effect, the microcode stores the appropriate existing values in the direct memory to the location planned in the indirect storage 1002 (to be replied upon subsequent mode switching) and from the indirect storage 1002. The previously stored values are returned to the direct storage 106 in other planned locations. In general, the current or old values in R13 and R14 of the direct storage 106 can be stored to the position of the old processing mode in the indirect storage 1002, and the position of the new processing mode in the indirect storage 1002 is restored to the direct R13 and R14 of the reservoir 106. However, there are more processing requirements when switching to FIQ mode or switching from FIQ mode. When switching from mode X to FIQ mode and then switching from FIQ mode to mode Y, the value in the R8-R12 register of direct memory 106 must be the same as in mode Y, although they all switch from mode X, And mode X may have a different value than mode Y. Thus, in this case, the global location in the indirect storage 1002 facilitates storing and recovering values from the R8-R16 registers of the direct storage 106.

As can be seen from the foregoing, the analog backup register described herein may be stored and replied between the direct storage 106 and the indirect storage 1002 by using microcode in the switching processing mode. Design The metering method will result in a slight extra load. However, the potential advantages of this potential additional burden allow the direct storage 106 to have faster access than conventional designs. This is because, in the embodiments described herein, additional transfer delays due to the use of processing modes for relatively less frequent backup registers must be avoided in conventional designs due to the hardware multiplexer. Since the hardware multiplexer is typically located in an important timing path, it is important that the hardware multiplexer accelerates the operation to facilitate the clock. Moreover, the number of registers in direct storage 106 will be less than conventional designs, which can reduce the time to access direct storage 106. In addition, another advantage of the embodiment is that it only needs to make minor modifications to the existing micro-architecture to support the ARM ISA backup register. Still further, another advantage of the embodiment is that it reduces the burden of the dependency checker in the RAT 106 when distinguishing between processing modes. Another advantage is that it can also reduce the size of the register rename table, or avoid serialization (such as update pipelines, ie RAT and ROB) in partial processing mode switching. Finally, another advantage of the embodiment is that the flexibility of switching an architecture to an ARM ISA backup register can be increased because the switching utilizes microcode implementation rather than hardware switching. In summary, the embodiments described herein, although it is possible to increase the time required for processing mode switching, relatively mode switching is relatively infrequent, and can be exchanged for higher performance in general. Wherein, the general case described herein refers to accessing the primary register for obtaining an ALU operand.

Although in the foregoing embodiments, the microcode system performs a storage and reply function between the direct storage and the indirect storage, in other embodiments, a microprocessor having a hardware combined logic gate is used to perform the response. deal with The mode switching requires the storage and reply functions between the direct storage and the indirect storage instead of using microcode. Further, although in the foregoing embodiments, the storage device for storing the old processing mode value is a PRAM, in other embodiments, the hardware temporary storage device is used as an indirect storage, but the system cannot be used. The ALU unit directly accesses it. Still further, while the foregoing embodiments are directed to the ARM ISA, in other embodiments are applied to other ISAs associated with particular backup registers of different processing modes.

Load Multiple/Store Multiple ARM ISA Instructions

Another feature of the ARM ISA is the Load Multiple (LDM) and Store Multiple (STM) instructions. Loading multiple instructions loads each of the general-purpose registers specified in the instruction from the memory, as described in pages A8-110 through A8-116 of the ARM manual. Conversely, STM instructions are stored in memory from each of the general-purpose registers assigned to the instructions, as described in pages A8-374 through A8-381 of the ARM manual. The embodiment described herein implements the LDM instruction and the STM instruction on the super-scaling non-sequential execution micro-architecture of the microprocessor 100 as described above. More specifically, the ARM ISA specifies the version of the LDM instruction and STM instruction from the exception event mode access architecture user mode register (ie, when the microprocessor 100 is not in user mode). These instruction versions correspond to LDM (User Scratchpad) instructions and STM (User Scratchpad) instructions, such as pages B6-7 to B6-8 and B6-22 to B6- in the ARM manual. Said in 23. In the embodiment described herein, the LDM (User Scratch) command and the STM (User Scratch) command are executed on the micro-architecture of the microprocessor 100, and the microprocessor 100 The micro-architecture includes an inter-reservoir storage 1002 for simulating the aforementioned backup register.

Please refer to FIGS. 13A and 13B, which are flowcharts showing the execution of an LDM instruction by the microprocessor 100 of FIG. 1 in the present invention, starting from step 1302.

In step 1302, the software instruction translator 204 of FIG. 2 receives an LDM instruction 124. In particular, the instruction mode indicator 132 indicates that the ARM ISA and the ARM SIT 224 of FIG. 2 decode the LDM instruction 124. The LDM instruction 124 specifies a set of general purpose registers for loading data and a contiguous memory address to be loaded into the data. In addition, the LDM instruction 124 specifies that the instruction is an LDM (User Scratch) instruction 124. Then proceed to step 1304.

In step 1304, ARM SIT 224 considers the next (or first) register assigned to LDM instruction 124, and proceeds to step 1306.

In step 1306, ARM SIT 224 determines if instruction 124 is an LDM (user register) instruction 124, and if so, proceeds to step 1312; if not, proceeds to step 1308.

At step 1308, the ARM SIT 224 issues a load microinstruction 126 to load data from the next (or first) location in the memory designated by the LDM instruction 124 and to the direct storage 106 as in FIG. A particular register (which is considered in step 1306). The load microinstruction 126 will be sent to the execution pipeline 112 and executed by the load unit 416. Then proceed to step 1318.

At step 1312, the ARM SIT 224 determines if the scratchpad is one of R8-R12 and if the current processing mode is FIQ mode. If yes, go to step 1314; if no, go to step 1316.

At step 1314, the ARM SIT 224 issues a load microinstruction 126 to load data from the next (or first) location in the memory specified by the LDM instruction 124 and to the non-architected, or temporary, direct storage. The register of the device 106. The load microinstruction 126 will be sent to the execution pipeline 112 and executed by the load unit 416. As will be described later, step 1324, the data will continue to be stored in the temporary scratchpad from the temporary scratchpad 1002. Then proceed to step 1318.

At step 1316, the ARM SIT 224 determines if the register is an R13 or R14 register, and if so, proceeds to step 1314; if not, proceeds to step 1308.

At step 1318, the ARM SIT 224 determines if there are other registers associated with the LDM instruction 124 that have not been considered, i.e., the associated microinstructions 126 that the hardware instruction translator 104 has not sent. If there are other registers, then return to step 1304 to consider the next register designated by the LDM instruction 124; if not, proceed to step 1322.

At step 1322, ARM SIT 224 determines if any microinstructions 126 have been sent to the temporary registers 106 in step 1314, and if so, proceeds to step 1324; if not, the flow ends.

At step 1324, SIT 204 transfers control to complex instruction translator (CIT) 206 of FIG. 2, which is based on microcode 234 to generate store_PRAM microinstructions 126 for use in loading the data loaded in step 1314. The temporary register 106 is stored in a suitable location in the indirect storage 1002. More specifically, the appropriate locations in the indirect storage 1002 refer to the R13 and R14 locations associated with the user mode, and the R8-R12 locations that are globally related to the non-FIQ processing mode. The store microinstruction 126 will be sent to the execution pipeline 112 and executed by the storage unit 416, and the process ends. Step 1324.

Please refer to FIGS. 14A and 14B, which show another flow chart of the microprocessor 100 of FIG. 1 for executing an LDM instruction. In steps 14A and 14B, many steps are similar to the steps of FIGS. 13A and 13B. And have the same label. However, in the 14A and 14B diagrams, if the ARM SIT 224 determines in step 1318 that there are no other registers to be considered, the flow ends; therefore, in the flow of the 14A and 14B processes, there is no step 1322 and Step 1324. In addition, there is a new step 1424 from step 1314, and a flow from step 1418 to step 1318.

In step 1424, the ARM SIT 224 sends a store_PRAM microinstruction 126 to store the data loaded in step 1314 from the temporary scratchpad 106 to a suitable location in the indirect storage 1002.

As can be seen from Figures 14A and 14B, an advantage in this embodiment is that the execution of the LDM (User Scratchpad) microinstruction does not require the transfer of control to the microcode 234. The downside is that it adds to the complexity of the ARM SIT224. In particular, under the premise that the ARM SIT 224 must send the store_PRAM microinstruction 126, the ARM SIT 224 must know about the appropriate location in the indirect storage 1002, and the information that the data must be stored there, and therefore with the 13A The embodiment of Figure 13B differs.

Referring to Figures 15A and 15B, there is shown a flow chart of the microprocessor 100 of Figure 1 of the present invention executing an STM instruction beginning at step 1502.

In step 1302, the software instruction translator 204 of FIG. 2 receives an STM instruction 124. In particular, the command mode indicator 132 indicates the ARM ISA and the ARM SIT 224 of FIG. 2 performs the STM instruction 124. decoding. The STM instruction 124 specifies the general purpose register to store and the contiguous memory address where the data will be stored. In addition, the STM instruction 124 specifies that the instruction is an STM (user register) instruction 124. Then proceed to step 1504.

In step 1504, ARM SIT 224 considers the next (or first) register assigned to STM instruction 124, and proceeds to step 1506.

In step 1506, ARM SIT 224 determines if instruction 124 is an SDM (user register) instruction 124, and if so, proceeds to step 1512; if not, proceeds to step 1508.

At step 1508, the ARM SIT 224 issues a store microinstruction 126 to store the data from the particular scratchpad of the direct store 106 of FIG. 10 to the next (or first) of the memory designated for the STM instruction 124. Location (which has been considered in step 1504). The store microinstruction 126 will be sent to the execution pipeline 112 and executed by the storage unit 416. Then proceed to step 1518.

At step 1512, the ARM SIT 224 determines if the scratchpad is one of R8-R12 and if the current processing mode is FIQ mode. If yes, go to step 1514; if no, go to step 1516.

At step 1514, ARM SIT 224 skips the particular register and then processes it at microcode 234 in step 1524, and proceeds to step 1518.

At step 1516, the ARM SIT 224 determines if the register is an R13 or R14 register, and if so, proceeds to step 1514; if not, proceeds to step 1508.

At step 1518, the ARM SIT 224 determines if there are other registers designated for the STM instruction 124 that have not been considered, i.e., the hardware instruction translator 104 has not sent the associated microinstruction 126 (or skipped in step 1514). If still If there are other registers, then return to step 1504 to consider the next register designated by the STM instruction 124; if not, proceed to step 1522.

At step 1522, the ARM SIT 224 determines if any of the registers are skipped in step 1514, and if so, proceeds to step 1524; if not, the flow ends.

In step 1524, SIT 204 transfers control to complex instruction translator (CIT) 206 of FIG. 2, which is based on microcode 234 to generate a microinstruction 126 pair (pair) for each register skipped by step 1514. ). Specifically, the microinstruction 126 loads the micro-instruction load_PRAM microinstruction 126 with a stored microinstruction 126, the load_PRAM microinstruction 126 loads the data from the appropriate location in the indirect storage 1002, to a non-architectural, or temporary The scratchpad of the direct storage 106. The store microinstruction 126 stores the data of the temporary scratchpad to a location in the memory designated by the STM instruction 124. More specifically, the appropriate locations in the indirect storage 1002 refer to the R13 and R14 locations associated with the user mode and the R8-R12 locations associated with the global non-FIQ processing mode. The load_PRAM and store microinstructions 126 will be sent to the execution pipeline 112 and executed by the storage unit 416 and the load unit 416, respectively, and the process ends at step 1524.

Please refer to FIGS. 16A and 16B, which are another flow chart showing the execution of an STM instruction by the microprocessor 100 of FIG. 1 of the present invention. In steps 16A and 16B, many steps are similar to the steps of FIGS. 15A and 15B. And have the same reference numerals. However, in the 16A and 16B diagrams, if the ARM SIT 224 determines in step 1518 that there are no other registers to be considered, the flow ends; therefore, in the flow of the 16A and 16B processes, there are no steps 1522 and steps. 1524. Further, it is judged as "Yes" at steps 1512 and 1516. The process has a new process, which proceeds to a new step 1624, and from a new step 1624 to a new step 1614, and a new step 1624 to step 1518.

In step 1624, the ARM SIT 224 sends a load_PRAM microinstruction 126 to load data from the appropriate location in the indirect storage 1002 to the temporary scratchpad 106, and then proceeds to step 1614.

In step 1614, the ARM SIT 224 sends a store microinstruction 126 to store the data that has been loaded in the temporary register 106 in step 1624 to the next one of the STM instructions 124 in the memory (or a) Position, then proceeds to step 1518.

As can be seen from Figures 16A and 16B, the advantage in this embodiment is that the execution of the STM (User Scratchpad) microinstruction does not require the transfer of control to the microcode 234, but the disadvantage is that it adds ARM. The complexity of the SIT224. In particular, under the premise that the ARM SIT 224 must send the load microinstruction 126/store_PRAM microinstruction 126, the ARM SIT 224 must know about the appropriate location in the indirect storage 1002 and the information to which the data must be stored. The information is therefore different from the embodiment of Figures 15A and 15B.

As previously described, the ARM SIT 224 has the advantage of including a state machine to transmit multiple microinstructions 126 to implement the ISA instructions 124 during multiple clock cycles.

The ARM ISA also includes a store reply status (SRS) instruction 124 that stores the LR and SPSR registers of the current processing mode in a memory stack of the target processing mode specified by the SRS instruction 124, where the SRS instruction The 124 Series can be different from the current processing mode. Therefore, the SRS instruction 124 requires the microprocessor 100 to load the target processing mode of the architecture SP. The value of the scratchpad to access its memory stack. In one embodiment, when the ARM SIT 224 decodes an ARM ISA SRS instruction 124, it generates a load_PRAM microinstruction 126 to load the SP value of the target mode from the R13 position of the target mode portion of the indirect storage 1002 and send To the temporary register of the direct memory 106 to access the memory stack of the target mode.

However, various embodiments of the present invention have been described in detail herein, and it should be fully understood how to implement and not be limited to these embodiments. Various other modifications and changes can be made by those skilled in the art in the light of the above-described embodiments of the invention. For example, the software can initiate devices and methods as described herein, such as function, manufacture, model, simulation, description, and/or testing. This can be achieved by using general programming languages (such as C and C++), Hardware Description Languages (HDL), or other available programs. Hardware Description languages (HDL) include Verilog HDL, VHDL. And other hardware description languages. Such software can be executed in any known computer usable medium, such as tape, semiconductor, disk or optical disc (such as CD-ROM and DVD-ROM), network, cable, wireless network or other communication medium. . Embodiments of the apparatus and method described herein may be included in a smart core semiconductor and converted into hardware of an integrated circuit product, such as a microprocessor core (such as in a hardware description language) Implementation or setting). Furthermore, the devices and methods described herein can be implemented by a combination of hardware and software. Therefore, the present invention is not limited to the embodiments of the invention, but is defined by the scope of the following patents and equivalents. In particular, the present invention can be implemented in a commonly used microprocessor device. Finally, those skilled in the art should be able to appreciate them. The same objects as those of the present invention can be made by designing or modifying other structures without departing from the scope of the invention as set forth in the appended claims.

100‧‧‧Microprocessor (Processing Core)

102‧‧‧ instruction cache

104‧‧‧ hardware instruction translator

106‧‧‧Scratch file

108‧‧‧ memory subsystem

112‧‧‧Execution pipeline

114‧‧‧Command Capture Unit and Branch Predictor

116‧‧‧ARM Program Counter (PC) Register

118‧‧‧x86 instruction index (IP) register

122‧‧‧Configuration register

124‧‧‧ISA Directive

126‧‧‧ microinstructions

128‧‧‧ Results

132‧‧‧instruction mode indicator

134‧‧‧Select address

136‧‧‧Environment mode indicator

202‧‧‧Instruction Formatter

204‧‧‧Simple Instruction Translator (SIT)

206‧‧‧Complex Instruction Translator (CIT)

212‧‧‧Multiplexer (mux)

222‧‧‧x86 Simple Instruction Translator

224‧‧‧ARM Simple Instruction Translator

232‧‧‧micro-program counter (micro-PC)

234‧‧‧microcode read-only memory

236‧‧‧microprogrammer (microsequencer)

235‧‧‧Instruction indirection register (IIR)

237‧‧‧microtranslator

242‧‧‧Format ISA instructions

244‧‧‧implementing microinstructions

246‧‧‧ Micro-instructions

248‧‧‧Select input

252‧‧‧ microcode address

254‧‧‧Read-only memory address

255‧‧‧ISA Command Information

302‧‧‧Pre-decoder

304‧‧‧Command byte array (IBQ)

306‧‧‧length decoders and ripple logic

308‧‧‧Multiplexer queue (mux queue, MQ)

312‧‧‧Multiplexer

314‧‧‧formatted instruction queue (FIQ)

322‧‧‧ARM instruction set status

401‧‧‧Micro-instruction queue

402‧‧‧register allocation table (RAT)

404‧‧‧instruction dispatcher

406‧‧‧reservation station

408‧‧‧instruction issue unit

412‧‧‧integer/branch unit

414‧‧‧media unit

416‧‧‧Load/store unit

418‧‧‧floating point unit

422‧‧‧reorder buffer (ROB)

424‧‧‧ execution unit

502‧‧‧ARM specific register

504‧‧‧86 specific register

506‧‧‧Shared register

700‧‧‧Dual Core Microprocessor

892‧‧‧Micro-instruction cache

902‧‧‧ Hardware Register File

904‧‧‧ Hardware multiplexed logic gate

906‧‧‧ hardware register

908‧‧‧ hardware multiplexed logic gate

912‧‧‧Scratchpad address

914‧‧‧ Processing mode

1004, 1006, 1008, 1014, 1016, 1018‧‧‧ multiplexers

1 is a block diagram of an embodiment of a microprocessor for executing an x86 program architecture and an ARM program architecture machine language program; and FIG. 2 is a block diagram showing the hardware instruction translator of FIG. 1 in detail; Figure 3 is a block diagram showing the instruction formatter (Fig. 2) in detail; Figure 4 is a block diagram showing the execution pipeline of Figure 1 in detail; Figure 5 is a block diagram showing the details. Figure 1 is a register file; Figure 6 (including Figures 6A and 6B) is a flow chart showing the operation steps of the microprocessor of Figure 1; Figure 7 is a dual core microprocessor of the present invention. Figure 8 is a block diagram of another embodiment of a microprocessor executing the x86 ISA and ARM ISA machine language programs of the present invention; and Figure 9 is a schematic diagram of a conventional hardware register file structure; 10 is a system block diagram of the present invention, showing the microprocessor of FIG. 1 in detail; FIG. 11 (including FIG. 11A and FIG. 11B) is shown in the present invention, and the microprocessor 100 is operated as shown in FIG. Flow chart; Fig. 12 is a flow chart showing the microprocessor of Fig. 10 according to Fig. 11 Also, the flow of information between the direct and indirect storage reservoir; FIG. 13 (comprising FIG. 13A, FIG. 13B and the second) -based a flow chart showing In the present invention, the microprocessor 100 of FIG. 1 executes a flowchart of an LDM instruction; and FIG. 14 (including FIG. 14A and FIG. 14B) is a flowchart showing the micrograph as shown in FIG. 1 in the present invention. Another flowchart of the processor 100 executing an LDM instruction; FIG. 15 (including FIG. 15A and FIG. 15B) is a flowchart showing that the microprocessor 100 as shown in FIG. 1 executes an STM instruction in the present invention. FIG. 16 and FIG. 16 (including FIGS. 16A and 16B) are flowcharts showing another flow chart of the microprocessor 100 executing an STM instruction as shown in FIG. 1 in the present invention.

100‧‧‧Microprocessor

102‧‧‧ instruction cache

104‧‧‧ hardware instruction translator

106‧‧‧Scratch file

108‧‧‧ memory subsystem

112‧‧‧Execution pipeline

114‧‧‧Command Capture Unit and Branch Predictor

116‧‧‧ARM Program Counter (PC) Register

118‧‧‧x86 instruction index (IP) register

122‧‧‧Configuration register

124‧‧‧ISA Directive

126‧‧‧ microinstructions

128‧‧‧ Results

132‧‧‧instruction mode indicator

134‧‧‧Select address

136‧‧‧Environment mode indicator

Claims (42)

A microprocessor includes: a plurality of processing modes including a user mode and a plurality of exception event modes; at least one execution unit configured to perform a complex arithmetic operation on an operand specified by the program instruction; a first storage element group And coupled to the execution unit, wherein the first storage element group includes a first subset of operation elements, and provides the first operation element subset to the execution unit; and a second storage element group associated with each processing mode The second storage element group includes a second subset of operation elements, wherein the second storage element group cannot directly provide the second operation element subset to the execution unit; and a logic unit, wherein, when When one of the processing modes enters a new processing mode, the logic unit stores the first subset of the operating elements in the first storage element group to the second storage element group associated with the current processing mode And reverting the second subset of operands in the second set of storage elements associated with the new processing mode to the first set of storage elements. The microprocessor of claim 1, further comprising: a third storage element group coupled to the execution unit, wherein the third storage element group includes a third subset of operation elements and provides the third a subset of operands to the execution unit; wherein the new processing mode is one of the first exception event modes of the exception event patterns; a fourth storage element group associated with the first exception event pattern, wherein the fourth storage element group includes a fourth subset of operation elements, wherein the fourth storage element group cannot directly provide the fourth operation element subset to The execution unit; and a fifth storage element group are globally associated with all of the processing modes except the first exception event mode, wherein the fifth storage element group includes a fifth subset of operation elements, wherein The fifth storage element group cannot directly provide the fifth operation element subset to the execution unit; wherein, when entering the new processing mode or the first exception event mode from the current processing mode, the logic unit additionally adds the The third subset of operands of the third storage unit group is stored to the fifth storage unit, and the fourth subset of operation elements in the fourth storage element group is returned to the third storage element group; When the first exception event mode enters one of the exception event modes, the second exception event mode, the logic unit stores the fourth operand subset of the third storage unit group to the fourth storage Means associated with the storage element and the fifth group of the new processing mode of operation of the third set is returned to the subspace third storage element group. The microprocessor of claim 2, wherein the microprocessor utilizes one of the first storage element groups to store a stacked index indicator operand of the ARM ISA, and utilizes the One of the first storage element groups, the second storage element, is configured to store one of the ARM ISAs that perform the arithmetic operations by the execution unit, and the second storage element group includes a first storage element to save One An ARM ISA stacked index register operand, and a second storage element to store an ARM ISA linked register operand for correlating processing modes; wherein the microprocessor utilizes the third storage element group to save The execution unit executes the arithmetic elements of the ARM ISA R8-R12 general-purpose register of the arithmetic operations; wherein the fourth storage element group includes a plurality of storage elements for storing the ARM ISA R8-R12 universal register operand. Corresponding to the ARM ISA FIQ exception event mode; wherein the fifth storage component group includes a plurality of storage elements for holding the ARM ISA R8-R12 general register operand to correspond to the globality except the ARM ISA FIQ exception event mode. ARM ISA processing mode. The microprocessor of claim 1, wherein the microprocessor utilizes the first storage element of the first storage element group to save a stacked index register operand of the ARM ISA, and utilize the first The second storage element of a storage element group is coupled to the register operand by one of the ARM ISAs that hold the execution unit to perform the arithmetic operations. The microprocessor of claim 1, wherein the first storage element group comprises a plurality of hardware registers, wherein the second storage element group comprises a random access memory (RAM). The microprocessor of claim 5, wherein the random access memory system can be loaded or written by using a microcode of the microprocessor; wherein the random access memory system is not ISA machine language Let it be loaded or written. The microprocessor of claim 1, further comprising: a super-quantity non-sequential execution pipeline, comprising: at least one execution unit; and a loading unit coupled to the first storage component group, wherein the The second set of storage elements provides the second subset of operands to the load unit, wherein the load unit provides the second subset of operands to the execution unit. The microprocessor of claim 1, wherein the exception event mode includes the ARM ISA exception event mode. A microprocessor as claimed in claim 1, wherein the logic unit comprises a microcode of the microprocessor. A microprocessor as claimed in claim 1, wherein the logic unit comprises a hardware combination logic unit. The microprocessor of claim 1, further comprising: an instruction translator for translating the instructions of the ARM ISA mechanical language to the plurality of microinstructions, wherein at least one ARM ISA instruction indicates the microprocessor from the current Processing mode entering the new processing mode; and an execution pipeline for executing the microinstructions to store the first subset of operating elements of the first set of storage elements to the second storage element associated with the current processing mode Grouping, and replying the second subset of operands of the second set of storage elements associated with the new processing mode to the first set of storage elements. Such as the microprocessor of claim 11th, wherein the instruction translator The instructions of the x86 ISA machine language instructions are further translated into a plurality of microinstructions, wherein the microinstructions are encoded in an instruction encoding manner different from the x86 ISA instruction set, wherein the execution pipeline further executes the microinstructions to generate the x86 ISA instructions. The result of the definition. A method of operating a microprocessor, the microprocessor comprising a plurality of processing modes, the processing mode having a user mode and a plurality of exception event modes, wherein the microprocessor further comprises at least one execution unit, the execution unit Performing a complex arithmetic operation on the operand through a specific program instruction, the method comprising: providing a first operand from a first set of storage elements when the microprocessor is operating in one of the processing modes Subsetting to the execution unit to perform the arithmetic operations; when entering the new processing mode from the current processing mode, the method includes the step of: dividing the first operational element subset of the first storage element group Storing to a second storage unit group associated with one of the current processing modes; reverting the second subset of operation elements associated with one of the third storage element groups associated with the new processing mode to the first storage element group; The microprocessor, when operating in the new processing mode, provides the second subset of operands from the first set of storage elements to the execution unit to perform the calculations Operation. The method of claim 13, further comprising: when the microprocessor operates in the current processing mode, providing a third subset of operands from a fourth storage component group to the execution unit to perform the Arithmetic operation When the current processing mode enters the new processing mode, the method further includes: storing the third subset of the operating elements of the fourth storage element group to a fifth storage element group associated with the new processing mode; Returning, to the fourth storage element group, a fourth operational element subset of a sixth storage element group, and the sixth storage element group is globally associated with the processing modes except the first exception event mode; When the microprocessor is operating in the new processing mode, the fourth subset of operands is provided from the fourth set of storage elements to the execution unit to perform the arithmetic operations; when the processing is entered from the new processing mode And a mode of the third processing mode, comprising: storing a fourth subset of operation elements from the fourth storage element group to the sixth storage element group; and the third subset of operation elements of the fifth storage element group Reverting to the fourth storage element group: and when the microprocessor is operating in the third processing mode, providing the third subset of operands from the fourth storage element group to the execution unit to perform the arithmetic operations . The method of claim 14, wherein the first storage element of the first storage element group has an ARM ISA stacked register operand and the first storage element group has a second storage element The execution unit performs the ARM ISA connection register operand of the arithmetic operations; wherein the second storage element group and the third storage element group each comprise one of the ARM ISA stacked index register operands First store And a second storage element associated with the processing mode and having an ARM ISA connection register operand; wherein the fourth storage element group has an ARM ISA R8- that performs the arithmetic operations on the execution unit An R12 general register; wherein the fifth storage element group has a storage element of an ARM ISA R8-R12 general register operand to correspond to an ARM ISA FIQ exception event mode; wherein the sixth storage element group includes The storage elements of the ARM ISA R8-R12 Universal Scratchpad operand are globally aligned to all of the ARM ISA processing modes except the ARM ISA FIQ exception event mode. The method of claim 13, wherein the first storage element of the first storage element group has one of the ARM ISA stacked index register operands, and the second storage of the first storage element group The component has one of the ARM ISAs that the execution unit performs the arithmetic operations to connect to the scratchpad operand. The method of claim 13, wherein the exception event pattern includes the ARM ISA exception event pattern. The method of claim 13, further comprising: translating instructions of the ARM ISA machine instruction language to the plurality of microinstructions, wherein the at least one ARM ISA instruction instructs the microprocessor to enter the new processing mode from the current processing mode; And executing the microinstructions to store the first subset of operands of the first set of storage elements to the second set of storage elements associated with the current processing mode, and to associate the second storage associated with the new processing mode element The second subset of operands of the group is returned to the first set of storage elements. The method of claim 18, further comprising: translating instructions of the x86 ISA machine instruction language into the microinstructions, wherein the microinstructions are encoded in an instruction encoding manner different from the x86 ISA instruction set. A computer program product encoded in at least one computer readable storage medium for use in an computing device, the computer program product comprising: computer readable code for the medium, designated for use in a microprocessor The method includes: a first code for specifying a plurality of processing modes, the processing mode includes a user mode and a plurality of exception event modes; and a second code for specifying at least one execution unit, The execution unit performs a complex arithmetic operation on the operand through a specific program instruction; a third code is used to designate a first storage element group, the first storage element group is coupled to the execution unit, wherein the first storage The component group has a first subset of operation elements and provides the first subset of operation elements to the execution unit; a fourth code for specifying a second storage element group associated with one of the processing modes; The second storage element group has a second subset of operation elements, wherein the second operation element cannot directly provide the second operation element subset to the execution unit; and a fifth code A logic unit for specifying, from which a current processing mode when entering a new one of the plurality of processing modules processing mode In the formula, the logic unit stores the first subset of the operation elements of the first storage element group to the second storage element group associated with the current processing mode, and returns the second storage element group associated with the new processing mode The second subset of operands is coupled to the first set of storage elements. The computer program product of claim 20, wherein the at least one computer readable storage medium is selected from the group consisting of a disc, a magnetic tape, or other magnetic, optical or electronic storage medium and a network, cable, wireless or A group of other communication media. A microprocessor that supports an ISA that specifies a plurality of processing modes and specifies a complex architecture register, and wherein the architectural registers are associated with each processing mode, and a load multiple instruction is specified, Loading multiple instructions instructs the microprocessor to load data from memory and pass in one or more architectural registers designated for the load multiple instructions, the microprocessor comprising: a direct storage with associated The first part of the architecture register is coupled to at least one execution unit of the processor to provide the data to the execution unit; and an indirect storage associated with the architecture register The data of the second part, wherein the indirect storage cannot directly provide the data associated with the second part of the architecture register to the execution unit; wherein the architecture registers are in accordance with the processing modes One of the current processing modes is dynamically distributed between the first portion of the architectural register and the second portion of the architectural register; and wherein each architectural register is assigned to the load Instruction: If the architecture register is located in the first portion, the microprocessor loads data from the memory and transfers the data to the direct storage; and if the architecture register is located in the second portion, The microprocessor loads the data from the memory and transfers it to the direct storage, and then transfers the data of the direct storage to the indirect storage. The microprocessor of claim 22, wherein the ISA supported by the microprocessor comprises an ARM ISA, wherein the processing modes specified in the ISA comprise an ARM ISA user, a system, a manager, a termination, an undetermined , IRQ, and FIQ processing modes, wherein the architecture register specified for the ISA includes an ARM ISA R0-R14 register associated with the user processing mode, and associated with the manager, terminated, undecided, IRQ, and FIQ A backup buffer for processing mode in which the load multiple instructions specified for the ISA include ARM ISA load multiple instructions. The microprocessor of claim 22, further comprising: an instruction translator for translating the load multiple instructions into a plurality of micro instructions executable by the microprocessor, wherein each architecture register is specified Loading multiple instructions: if the architecture register is located in the first portion, the instruction translator sends a micro-instruction to transfer data from the memory to the direct storage; The memory is located in the second portion, the instruction translator sends a first micro-instruction to transfer data from the memory to the direct storage, and sends a second micro-instruction to the direct storage The data is transferred to the indirect storage. Such as the microprocessor of claim 24, wherein the instruction translator The first part includes: sending the micro-instruction to load data from the memory and feeding the data into the direct storage, and sending the first micro-instruction to load data from the memory and send the data to the direct storage device, wherein The first portion includes a hardware state machine; and a second portion transmits the second microinstruction to transfer the direct memory data to the indirect storage, wherein the second portion includes a microcode. The microprocessor of claim 24, wherein the hardware instruction translator translates instructions of the x86 ISA machine language instruction ARM ISA machine language instruction into the micro instructions, wherein the micro instructions are different from x86 ISA and ARM The instruction encoding mode of the ISA instruction set is encoded, wherein the microprocessor further includes an execution pipeline coupled to the hardware instruction translator, wherein the execution pipeline executes the micro instructions to generate instructions by the x86 ISA and ARM ISA instructions. The result of the definition. The microprocessor of claim 22, wherein if the current processing mode is the ARM ISA user mode, the direct storage has data associated with the user mode architecture register, and the indirect The memory has information about the R13-R14 architecture register associated with the ARM ISA exception event pattern and the R8-R12 architecture register associated with the ARM ISA FIQ mode, if the current processing mode is the ARM ISA FIQ In the mode, the direct storage has information associated with the FIQ architecture register, and the indirect storage device is related to the R13-R14 architecture register connected to the ARM ISA user mode and the non-FIQ exception event mode. And the data associated with the R8-R12 architecture register of the ARM ISA mode prior to the current processing mode; wherein if the current processing mode is an ARM ISA non-FIQ exception event mode, the direct storage The device has information associated with the non-FIQ exception event mode architecture register, and the indirect storage has information about the R13-R14 architecture register associated with the ARM ISA user mode and the non-current exception event pattern. And the information associated with the R8-R12 architecture register for the ARM ISA FIQ mode. A method for operating a microprocessor that supports an ISA that specifies a plurality of processing modes and specifies a complex architecture register, and wherein the architectural registers are associated with respective processing modes, and Specifying a load multiple instruction that instructs the microprocessor to load data from memory and pass one or more architectural registers designated for the load multiple instructions, the method comprising: The architecture register is configured to load the multiple instructions: if the architecture register is located in a first portion, the data is loaded from the memory and passed to the direct memory of the microprocessor; The architecture register is located in a second portion, and the data is loaded from the memory and transmitted to the direct storage, and then the data of the direct storage is transferred to the indirect storage; wherein the direct storage has Corresponding to the first portion of the architecture register and coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; wherein the indirect storage device is associated with the One register configuration information of a second portion, wherein the reservoir can not provide indirect directly linked to And the data of the second part of the architecture register is sent to the execution unit; wherein the architecture registers are dynamically distributed in the architecture register according to the current processing mode in the processing modes Part of this second part of the architecture register. The method of claim 28, wherein the ISA supported by the microprocessor comprises an ARM ISA, wherein the processing modes specified in the ISA comprise an ARM ISA user, system, manager, termination, pending, IRQ And an FIQ processing mode, wherein the architecture register specified for the ISA includes an ARM ISA R0-R14 register associated with the user processing mode, and associated with the manager, termination, pending, IRQ, and FIQ processing modes The backup scratchpad, wherein the load multiple instructions specified for the ISA include ARM ISA load multiple instructions. The method of claim 29, further comprising: translating, by the microprocessor, the load multiple instructions into a plurality of micro instructions executable by the microprocessor, wherein each architecture register is assigned to the load multiple Instruction: if the architecture register is located in the first portion, the instruction translator sends a microinstruction to transfer data from the memory to the direct storage; if the architecture register is located in the In the second part, the instruction translator sends a first micro-instruction to transfer data from the memory to the direct storage, and sends a second micro-instruction to transfer the direct storage data to the indirect Storage. The method of claim 30, wherein the microinstruction is sent through a hardware state machine to load data from the memory and feed the straight And storing the second microinstruction through a microcode to transfer the data of the direct storage to the indirect storage. The method of claim 29, wherein if the current processing mode is the ARM ISA user mode, the direct storage has information associated with the user mode architecture register, and the indirect storage Information on the R13-R14 architecture register associated with the ARM ISA exception event pattern and the R8-R12 architecture register associated with the ARM ISA FIQ mode. If the current processing mode is the ARM ISA FIQ mode, The direct storage device has information associated with the FIQ architecture register, and the indirect storage device relates to the R13-R14 architecture register connected to the ARM ISA user mode and the non-FIQ exception event mode, and Data relating to the R8-R12 architecture register of the ARM ISA mode prior to the current processing mode; wherein the direct memory is associated if the current processing mode is an ARM ISA non-FIQ exception event mode Information about the non-FIQ exception event mode architecture register, and the indirect storage has information about the R13-R14 architecture register associated with the ARM ISA user mode and the non-current exception event pattern. And the information associated with the R8-R12 architecture register for the ARM ISA FIQ mode. A microprocessor that supports an ISA that specifies a plurality of processing modes and a specified complex architecture register, and wherein the architectural registers are associated with each processing mode, and a storage multiple instruction is specified, the storage The multi-instruction command instructs the microprocessor to transfer data from the one or more architectural registers designated to store the multiple instructions to the memory. The microprocessor includes: a direct storage having data associated with a first portion of one of the architecture registers and coupled to at least one execution unit of the processor to provide the data to the execution unit; An indirect storage having information associated with a second portion of one of the architectural registers, wherein the indirect storage cannot directly provide information associated with the second portion of the architectural register to the execution unit; The architecture registers are dynamically distributed between the first portion of the architecture register and the second portion of the architecture register in accordance with the current processing mode of the processing modes; and wherein each architecture temporarily The storage system is specific to the storage multiple instructions: if the architecture register is located in the first portion, the microprocessor transfers data from the direct storage to the memory; and if the architecture is temporarily stored Located in the second portion, the microprocessor loads data from the indirect storage and passes it to the direct storage, and then transfers the data from the direct storage to the memory. The microprocessor of claim 33, wherein the ISA supported by the microprocessor comprises an ARM ISA, wherein the processing modes specified in the ISA comprise an ARM ISA user, a system, a manager, a termination, an undetermined , IRQ, and FIQ processing modes, wherein the architecture register specified for the ISA includes an ARM ISA R0-R14 register associated with the user processing mode, and associated with the manager, terminated, undecided, IRQ, and FIQ A backup buffer for processing mode, wherein the store multiple instructions specified for the ISA include an ARM ISA store multiple instructions. Such as the microprocessor of claim 34, including An instruction interpreter for translating the stored multiple instructions into a plurality of microinstructions executable by the microprocessor, wherein each architectural register is assigned to the stored multiple instructions: if the architectural register is located in the In the first part, the instruction translator sends a micro-instruction to transfer data from the direct storage to the memory; if the architecture register is located in the second part, the instruction translator sends a first micro-instruction Loading data from the indirect storage and passing it to the direct storage, and then transferring the data from the direct storage to the memory. The microprocessor of claim 34, wherein if the current processing mode is the ARM ISA user mode, the direct storage has data associated with the user mode architecture register, and the indirect storage The device has information about the R13-R14 architecture register associated with the ARM ISA exception event pattern and the R8-R12 architecture register associated with the ARM ISA FIQ mode; if the current processing mode is the ARM ISA FIQ Mode, the direct storage has information associated with the FIQ architecture register, and the indirect storage device has information about the R13-R14 architecture register connected to the ARM ISA user mode and the non-FIQ exception event mode. And data relating to the R8-R12 architecture register of the ARM ISA mode prior to the current processing mode; wherein the direct memory is if the current processing mode is an ARM ISA non-FIQ exception event mode Having information associated with the non-FIQ exception event mode architecture register, and the indirect storage has associated with the ARM ISA user mode and a non-current exception event pattern Information on the R13-R14 architecture register and information on the R8-R12 architecture register associated with the ARM ISA FIQ mode. A method for operating a microprocessor that supports an ISA that specifies a plurality of processing modes and specifies a complex architecture register, and wherein the architectural registers are associated with respective processing modes, and Specifying a store multiple instruction to store the data instruction to the microprocessor to transfer data from the one or more architectural registers designated to store the multiple instructions to the memory, the method comprising: each architecture register Designating the store multiple instructions: if the architecture register is located in the first portion, transferring data from the direct storage of the microprocessor to the memory; and if the architecture register is located The second part loads data from the indirect storage and transfers the data to the direct storage, and then transfers the data from the direct storage to the memory; wherein the direct storage has a correlation with the architecture And the at least one execution unit of the microprocessor is coupled to the execution unit; wherein the indirect storage device is temporarily connected to the architecture The data of the second part, wherein the indirect storage cannot directly provide the data associated with the second part of the architecture register to the execution unit; wherein the architecture registers are in accordance with the processing modes The current processing mode is dynamically distributed between the first portion of the architectural register and the second portion of the architectural register. The method of claim 37, wherein the ISA supported by the microprocessor comprises an ARM ISA, wherein the processing modes specified by the ISA are The system includes an ARM ISA user, system, manager, termination, pending, IRQ, and FIQ processing modes, wherein the architecture register specified for the ISA includes an ARM ISA R0-R14 temporary storage associated with the user processing mode. And a backup register associated with the manager, termination, pending, IRQ, and FIQ processing modes, wherein the stored multiple instructions specified for the ISA include an ARM ISA store multiple instructions. The method of claim 38, further comprising translating, by the microprocessor, the stored multiple instructions into a plurality of micro instructions executable by the microprocessor, wherein each architectural register is assigned to the stored multiple instructions: When the architecture register is located in the first portion, the instruction translator sends a microinstruction to transfer data from the direct storage to the memory; if the architecture register is located in the second portion, The instruction translator sends a first microinstruction to load data from the indirect storage and pass it to the direct storage, and then transfer the data from the direct storage to the memory. The method of claim 37, wherein if the current processing mode is the ARM ISA user mode, the direct storage has information associated with the user mode architecture register, and the indirect storage has Information about the R13-R14 architecture register associated with the ARM ISA exception event pattern and the R8-R12 architecture register associated with the ARM ISA FIQ mode; if the current processing mode is the ARM ISA FIQ mode, The direct storage has information associated with the FIQ architecture register. And the indirect storage device is related to the R13-R14 architecture register of the ARM ISA user mode and the non-FIQ exception event mode, and the R8-R12 associated with the ARM ISA mode earlier than the current processing mode. The data of the architecture register; wherein, if the current processing mode is an ARM ISA non-FIQ exception event mode, the direct storage has information associated with the non-FIQ exception event mode architecture register, and the The indirect storage has information about the R13-R14 architecture register associated with the ARM ISA user mode and the non-current exception event mode, and the R8-R12 architecture register associated with the ARM ISA FIQ mode. A computer program product encoded in at least one computer readable storage medium for use in an computing device, the computer program product comprising: a computer readable code for the medium, for specifying a microprocessor, The microprocessor supports an ISA that specifies a plurality of processing modes and specifies a complex architecture register, and the architectural registers are associated with each processing mode, and a load multiple instruction is specified, the loading The multi-instruction instruction instructs the microprocessor to load data from the memory and pass in one or more architectural registers designated for loading the multi-instruction, the computer-loadable code comprising: a first code, Used to specify a direct storage having information associated with a first portion of one of the architecture registers and coupled to at least one execution unit of the processor to provide the data to the execution a second code that is assigned to an indirect storage having a second portion associated with one of the architectural registers The indirect storage is incapable of directly providing the data associated with the second portion of the architecture register to the execution unit; wherein the architectural registers are based on the current processing in the processing modes a mode, dynamically distributed in the first portion of the architectural register and the second portion of the architectural register; wherein each architectural register is assigned to the load multiple instruction: if the architectural register Located in the first portion, the microprocessor loads data from the memory and is passed to the direct storage; and if the architecture register is located in the second portion, the microprocessor is self-memory The data is loaded and passed to the direct storage, and then the data of the direct storage is transferred to the indirect storage. The computer program product of claim 41, wherein the at least one computer readable storage medium is selected from the group consisting of a disc, a magnetic tape, or other magnetic, optical or electronic storage medium and a network, a cable, a wireless device. Or a group of other communication media.