TWI476774B - Shift register - Google Patents

Description

Shift register

The invention relates to a shift register, in particular to a shift register applied to a light-sensing touch panel.

At present, the design trend of the display panel is to integrate the shift register in the gate driving circuit on the display panel to replace the external driving chip, thereby reducing the manufacturing process, increasing the integration of the display panel, and reducing the manufacturing cost.

Since each stage of the shift register circuit in the general shift register only outputs one gate signal to drive the pixel array of the general display panel. However, if the light-sensing touch panel formed after the light-sensing touch function is added to the display panel, in addition to receiving the gate signal from the shift temporary storage circuit, another signal different from the gate signal needs to be received. Normal operation, in other words, receiving two output signals from two different pulse widths of the shift register circuit. If the external driving chip provides another signal to the light sensing touch panel, the advantages of the integrated shift register on the display panel cannot be extended to the light sensing touch panel.

Therefore, the prior art also develops a shift register that can provide two output signals of different pulse widths. This type of shift register includes at least a driving circuit and a pull-down circuit and a driving circuit to According to the driving signal, two dual output signals of different pulse widths, namely gate signal and sensing signal, are provided. However, since only a single high frequency clock signal is received in the driving circuit and no other high frequency clock signals are received, the sensing signal will be in a floating state. If the sensing signal in the floating state is offset from the process, there will be a serious leakage phenomenon, and here in the floating state The sensing signal is also susceptible to interference from other signals.

Embodiments of the present invention disclose a shift register having a complex stage shift register circuit. The Nth stage shift register circuit includes a driving unit, a first pull down unit, and a main pull down unit. The driving unit is configured to provide an Nth primary gate signal and an Nth secondary gate signal according to the Nth driving signal and the plurality of high frequency clock signals. The driving unit includes a first transistor, a second transistor, and a plurality of switching units. The first transistor has a control end for receiving the Nth stage driving signal, a first end for receiving the first high frequency clock signal, and a second end for providing the Nth stage main gate signal. The second transistor has a control end electrically connected to the control end of the first transistor, a first end, and a second end for providing an Nth-order secondary gate signal. The plurality of switching units have a first end receiving the corresponding k high frequency clock signals and a second end electrically connected to the first end of the second transistor. The first pull-down unit is electrically connected to the driving unit for pulling down the Nth driving signal, the Nth main gate signal and the Nth secondary gate signal. The main pull-down unit is electrically connected to the control end of the first transistor in the driving unit and the second end of the second transistor for pulling down the potential of the control end of the first transistor according to the N+k-level main gate signal and The potential of the second end of the second transistor. The pulse widths of the Nth primary gate signal and the Nth secondary gate signal are different.

The shift register in the integrated gate driving circuit of the present invention is on the light sensing touch panel, and the Nth stage shift register circuit can generate two different pulse width output signals for providing the light sensing touch. The signal required by the panel does not require an external driver chip, thereby reducing the manufacturing process of the light-sensitive touch panel and improving the integration degree, and also integrating the shift register in the gate driving circuit into the light-sensing touch panel. Light sensing The space around the touch panel allows the space to be narrowed, reducing the number of processes and reducing manufacturing costs.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

FIG. 1A is a schematic diagram of a shift register 101 and a pixel array 110 of the light-sensitive touch panel 100 of the present invention. As shown in FIG. 1A, the shift register 101 includes a plurality of stages of shift register circuits 102, 104, and 10n. Each stage shift register circuit in the shift register 101 outputs two gate signals to drive the pixel array 110. For example, the Nth stage shift register circuit 10n outputs the Nth stage main gate signal G. (n) and the Nth secondary gate signal S(n) to the pixel array 110.

The pixel array 110 of the light-sensitive touch panel 100 has n main gate lines G(1), G(2), ..., G(n), n sub-gate lines S(1), S (2),...,S(n), m data lines D(1), D(2),...,D(m),p read lines R(1),R(2) , ..., R (p), a plurality of pixel circuits 112, and a plurality of light sensing circuits 114, wherein the main gate lines G (1), G (2), ..., G (n) are electrically First connected to the first end of the plurality of pixel circuits 112 and the first of the plurality of light sensing circuits 114 The second and second gate lines S(1), S(2), ..., S(n) are electrically connected to the second ends of the plurality of light sensing circuits 114 of each column, respectively, and the data line D(1) D(2), ..., D(m) are electrically connected to the second ends of the plurality of pixel circuits 112 of each row, respectively, and the readout lines R(1), R(2), ... R(p) is electrically connected to the third ends of the plurality of light sensing circuits 114 of each row, respectively, and the number of readout lines p is substantially no greater than the number of main gate lines n.

FIG. 1B is a schematic diagram of a pixel circuit 112 and a light sensing circuit 114 corresponding to the light-sensitive touch panel 100 of the present invention. As shown in FIG. 1B, the pixel circuit 112 includes a pixel transistor 120 and a liquid crystal capacitor 122. The gate of the pixel transistor 120 is electrically connected to the first-level main gate signal G(1). The source is electrically connected to the first data line D(1). The liquid crystal capacitor 122 is electrically connected to the drain of the pixel transistor 120 for storing electric charge to enable the liquid crystal to be turned over. The light sensing circuit 114 includes an optoelectronic transistor 132, a read transistor 134, and a read capacitor 136. In addition, a processing unit 116 has an amplifier 140. The positive terminal of the amplifier 140 is electrically connected to the first readout line R(1) and the read transistor 134, and the negative terminal is electrically connected to the reference. Voltage Vref. Photoelectric crystal 132 is used to receive an optical signal and is turned on. The first stage primary gate signal G(1) is input to the gate of the photovoltaic transistor 132, and the first stage gate signal S(1) is input to the source of the photovoltaic transistor 132. The charge stored in the capacitor 136 is discharged through the path formed by the photovoltaic transistor 132. The magnitude of the discharge current is determined by the illumination intensity of the photovoltaic transistor 132 and the gate-source voltage (Vgs) clamping setting. The read transistor 134 is turned on in response to the first stage main gate signal G(1), so that the processing unit 116 can periodically detect the voltage Va of the read capacitor 136. The processing unit 116 reads out the final read voltage Va after one frame period discharge via the first read line R(1) and the read transistor 134, and the processing unit 116 will read during the read cycle. Voltage Va The final value is converted into an output voltage Vout output, which is determined to be a light-sensing state by determining whether the photo-electric crystal 132 receives a high-intensity optical signal.

Fig. 2 is a view showing the shift register circuit of the first embodiment of the present invention, showing the Nth stage shift register circuit 10n of the shift register 100 in Fig. 1. As shown in FIG. 2, the Nth stage shift register circuit 200 includes a driving unit 202, a first pull-down unit 204, a first pull-down control unit 206, a main pull-down unit 208, a pull-up unit 210, and a second pull-down unit. 212, a second pull-down control unit 214 and a capacitor 216.

The driving unit 202 is configured to receive and according to the Nth driving signal Q(n), the first high frequency clock signal HC1, and the second high frequency clock signal HC2, to provide the Nth main gate signal G(n) and The Nth secondary gate signal S(n). The first pull-down control unit 206 is configured to generate a first pull-down control signal K(n) according to the N-th driving signal Q(n) and the first low-frequency clock signal LC1.

The first pull-down unit 204 is electrically connected to the driving unit 202 and the first pull-down control unit 206 for pulling down the N-th driving signal Q(n) and the N-th main according to the first pull-down control signal K(n) Gate signal G(n) and Nth gate signal S(n).

The main pull-down unit 208 is electrically connected to the driving unit 202 for pulling down the Nth driving signal Q(n) and the Nth secondary gate signal S according to the N+2 main gate signal G(n+2). n).

The second pull-down control unit 214 is configured to generate a second pull-down control signal P(n) according to the N-th driving signal Q(n) and the second low-frequency clock signal LC2.

The second pull-down unit 212 is electrically connected to the driving unit 202 and the second pull-down control unit 214 for pulling down the N-th driving signal Q(n) and the N-th main gate signal according to the second pull-down control signal P(n) G(n) and the Nth secondary gate signal S(n).

The pull-up unit 210 is electrically connected to the driving unit 202 for providing the N+1th driving signal Q(n+1) to the N+1th shift temporary storage circuit according to the Nth driving signal Q(n). Drive unit.

The driving unit 202 includes a first transistor T1, a second transistor T2, a fifth transistor T5, and a plurality of switching units. In this embodiment, the switching unit is composed of a third transistor T3 and a fourth transistor T4. The pull up unit 210 includes a sixth transistor T6. The main pull-down unit 208 includes a seventh transistor T7 and an eighth transistor T8. The first pull-down unit 204 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The first pull-down control unit 206 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The second pull-down unit 212 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The second pull-down control unit 214 includes a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22.

The first transistor T1 has a control terminal for receiving the Nth stage driving signal Q(n) for receiving the first end of the first high frequency clock signal HC1, and for providing the Nth stage main gate signal G The second end of (n). The second transistor T2 has a control end electrically connected to the control end of the first transistor, a first end, and a second end for providing an Nth-order secondary gate signal S(n). The third transistor T3 has a control end for receiving the first high frequency clock signal HC1, a first end electrically connected to the control end of the third transistor T3, and a first end electrically connected to the second transistor T2. The second end of the end. The fourth transistor T4 has a control end for receiving the second high frequency clock signal HC2, a first end electrically connected to the control end of the fourth transistor T4, and a first end electrically connected to the second transistor T2. The second end of the end. The fifth transistor T5 has a signal for receiving the Nth stage driving signal Q(n) The control terminal is configured to receive a first end of the first high frequency clock signal HC1 and a second end to output an Nth level control signal ST(n).

The sixth transistor T6 has a control end electrically connected to the second end of the fifth transistor T5, electrically connected to the first end of the second end of the first transistor T1, and used to provide the N+1th driving signal The second end of Q(n+1).

The seventh transistor T7 has a control end for receiving the N+2 main gate signal G(n+2), is electrically connected to the first end of the second end of the second transistor T2, and is configured to receive the first A second end of the low voltage VSS_S. The eighth transistor T8 has a control end electrically connected to the control end of the seventh transistor T7, electrically connected to the first end of the control end of the first transistor T1, and a second end for receiving the second low voltage VSS_G .

The ninth transistor T9 has a control terminal for receiving the first pull-down control signal K(n), a first end electrically connected to the second end of the second transistor T2, and a first low voltage VSS_S for receiving Second end. The tenth transistor T10 has a control end electrically connected to the control terminal of the ninth transistor T9, electrically connected to the first end of the second end of the first transistor T1, and the second terminal for receiving the second low voltage VSS_G end. The eleventh transistor T11 has a control end electrically connected to the control end of the ninth transistor T9, and is electrically connected to the first end of the control end of the first transistor T1, and the second end is electrically connected to the first end The second end of the transistor T1 or the second end of the tenth transistor T10.

The twelfth transistor T12 has a control end for receiving the first low frequency clock signal LC1, a first end electrically connected to the control end of the twelfth transistor T12, and a second end. The thirteenth transistor T13 has a control end for receiving the Nth stage driving signal Q(n), is electrically connected to the first end of the second end of the twelfth transistor T12, and is electrically connected to the tenth transistor. The second end of the second end of T10. The fourteenth transistor T14 has The control terminal electrically connected to the second end of the twelfth transistor T12 is electrically connected to the first end of the control end of the twelfth transistor T12, and is electrically connected to the second end of the control end of the ninth transistor T9. . The fifteenth transistor T15 has a control end electrically connected to the control end of the thirteenth transistor T13, is electrically connected to the first end of the second end of the fourteenth transistor T14, and is electrically connected to the tenth transistor. The second end of the second end of T10.

The sixteenth transistor T16 has a control terminal for receiving the second pull-down control signal P(n), a first end electrically connected to the second end of the second transistor T2, and a first low voltage VSS_S for receiving Second end. The seventeenth transistor T17 has a control end electrically connected to the control end of the sixteenth transistor T16, is electrically connected to the first end of the second end of the first transistor T1, and is configured to receive the second low voltage VSS_G. Second end. The eighteenth transistor T18 has a control end electrically connected to the control end of the sixteenth transistor T16, and is electrically connected to the first end of the control end of the first transistor T1, and the second end is electrically connected to the first end A second end of the transistor T1 or a second end of the seventeenth transistor T17.

The nineteenth transistor T19 has a control end for receiving the second low frequency clock signal LC2, a first end electrically connected to the control end of the nineteenth transistor T19, and a second end. The twentieth transistor T20 has a control end for receiving the Nth stage driving signal Q(n), is electrically connected to the first end of the second end of the nineteenth transistor T19, and is electrically connected to the seventeenth electric The second end of the second end of the crystal T17. The twenty-first transistor T21 has a control end electrically connected to the second end of the nineteenth transistor T19, electrically connected to the first end of the control end of the nineteenth transistor T19, and electrically connected to the sixteenth The second end of the control end of the transistor T16. The twenty-second transistor T22 has a control end electrically connected to the control end of the twentieth transistor T20, and is electrically connected to the second eleventh a first end of the second end of the crystal T21 and a second end electrically connected to the second end of the seventeenth transistor T17.

The capacitor 216 is electrically connected between the control end and the second end of the first transistor T1. The first low voltage VSS_S and the second low voltage VSS_G are voltage levels less than 0 volts and the first low voltage VSS_S may be higher than the second low voltage VSS_G.

FIG. 3 is a schematic diagram of signal waveforms during operation of the Nth stage shift register circuit 200 of FIG. 2, wherein the horizontal axis t is a time axis. In Fig. 3, the signals from top to bottom are the first high frequency clock signal HC1, the second high frequency clock signal HC2, the N-1th main gate signal G(n-1), the Nth The primary gate signal G(n), the Nth drive signal Q(n), the Nth secondary gate signal S(n), and the N+2 primary gate signal G(n+2). The N-1 stage main gate signal G(n-1) is electrically connected to the Nth stage shift register circuit 200 through the pull-up unit T6 _N-1 of the N-1th stage shift register circuit, The Nth stage driving signal Q(n) of the Nth stage shift register circuit 200 is provided. The frequencies of the first high frequency clock signal HC1 and the second high frequency clock signal HC2 are higher than the first low frequency clock signal LC1 and the second low frequency clock signal LC2. The first high frequency clock signal HC1 and the second high frequency clock signal HC2 are clock signals that can be sequentially applied to the same stage shift register circuit and one of the high frequency clock signals is higher in phase than the previous one. The frequency clock signal is late. For example, the Nth stage shift register circuit 200 can be electrically connected to the second transistor T2 as in the third transistor T3 and the fourth transistor T4, and sequentially after the fourth transistor T4. The other transistors are connected to receive the first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3 and the fourth high frequency clock signal HC4, and so on.

As shown in Fig. 3, during the t1 period, the N-1th main gate signal G(n-1) is switched from a low potential to a high potential, since the N-1th main gate signal G(n-1) can be The pull-up unit T6 _N-1 through the N-1th stage shift register circuit is electrically connected to the control terminal of the first transistor T1 of the Nth stage shift register circuit 200, so the capacitor 216 is charged to make the Nth The stage driving signal Q(n) rises to the first high potential VH1, and turns on the first transistor T1, the second transistor T2 and the fifth transistor T5, and turns on the twentieth transistor T20, the twenty-second The transistor T22, the thirteenth transistor T13, and the fifteenth transistor T15 further pull down the first pull-down control signal K(n) and the second pull-down control signal P(n) to the second low voltage VSS_G to cut off Sixteenth transistor T16, seventeenth transistor T17, eighteenth transistor T18, ninth transistor T9, tenth transistor T10 and eleventh transistor T11.

Then, in the period t2, the N-1th main gate signal G(n-1) is switched from a high potential to a low potential, so that the sixth transistor T6 of the pull-up unit of the N-1th stage shift register circuit can be made. _{N-1 is} turned off, so the low potential of the N-1th main gate signal G(n-1) cannot be changed via the sixth transistor T6 _N-1 of the pull-up unit of the N-1th stage shift register circuit. The Nth stage drive signal Q(n). At this time, the first high frequency clock signal HC1 is switched from a low potential to a high potential, and the coupling of the capacitor 216 pulls the Nth stage driving signal Q(n) from the first high potential VH1 to the second high potential VH2, which will have The high-frequency first high-frequency clock signal HC1 outputs an N-th stage main gate signal G(n), and outputs a first high-frequency clock signal HC1 having a high potential to the second end of the fifth transistor T5. The third transistor T3 and the sixth transistor T6 are turned on. The Nth main gate signal G(n) can output the N+1th driving signal Q(n+1) to the N+1th shift temporary storage circuit through the sixth transistor T6. The first high frequency clock signal HC1 having a high potential outputs a Nth-order secondary gate signal S(n) having a third high potential VH3 through the third transistor T3 and the second transistor T2.

During the t3 period, the first high frequency clock signal HC1 is switched from a high potential to a low potential, and the coupling of the capacitor 216 causes the Nth stage driving signal Q(n) to be pulled down again from the second high potential VH2 to the first high potential VH1. The Nth main gate signal G(n) and the second end of the fifth transistor T5 are lowered to a low potential to turn off the third transistor T3. The third transistor T3 after the cutoff isolates the low-frequency first high-frequency signal HC1, but at this time, the second high-frequency signal HC2 is switched from a low potential to a high potential, and is output through the fourth transistor T4 and the second transistor T2. The Nth secondary gate signal S(n) having the fourth high potential VH4, so the Nth secondary gate signal S(n) is in a charged state. In this way, the Nth secondary gate signal S(n) does not fall to a low potential with the change of the first high frequency clock signal HC1 during the t3 period, and can be maintained at the fourth high potential VH4, and the fourth high potential VH4 can be Higher than the third high potential VH3.

Until the time period t4, the N+2 main gate signal G(n+2) is switched from the low potential to the high potential, and the seventh transistor T7 and the eighth transistor T8 are turned on, and the Nth stage driving signal Q(n) is pulled down. And the Nth secondary gate signal S(n). The first high frequency clock signal HC1 and the second high frequency clock signal HC2 are high frequency clock signals having the same pulse width and can be sequentially applied to the Nth stage shift register circuit 200. Therefore, in this embodiment, the time when the Nth secondary gate signal S(n) is maintained at a high potential is higher than the temperature at which the Nth primary gate signal G(n) is maintained at a high potential. Time, but the invention is not limited thereto, and any output signal that can output two or more different pulse widths is within the scope of the invention.

In the above embodiment, the time when the Nth-level secondary gate signal S(n) is maintained at the high potential is longer than the time when the N-th stage main gate signal G(n) is maintained at the high potential. So integrated in light The driving unit 202 of the Nth stage shift register circuit 200 of the inductive touch panel can output two output signals with different pulse widths, that is, the Nth level gate signal S(n) and the Nth stage with different pulse widths. The main gate signal G(n) is used to provide a light-sensitive touch panel.

4 is a schematic diagram of an Nth stage shift register circuit 400 according to a second embodiment of the present invention. The circuit connection relationship between the Nth stage shift register circuit 400 and the Nth stage shift register circuit 200 of FIG. 2 is substantially the same, and it is worth mentioning that the connection relationship of the pull-up unit 410 in FIG. 4 is the second. The figure is different, that is, the sixth transistor T6 of the pull-up unit 410 has a control terminal for receiving the N-1th main gate signal G(n-1), and is electrically connected to the sixth transistor T6. The first end of the end is electrically connected to the second end of the control end of the first transistor T1. In this embodiment, the N-1th main gate signal G(n-1) is electrically connected to the Nth stage shift register circuit 400 through the pull-up unit 410 of the Nth stage shift register circuit 400. The control terminal of the first transistor T1 provides the Nth stage driving signal Q(n) of the Nth stage shift register circuit 400. The driving unit 202, the first pull-down unit 204, the first pull-down control unit 206, the main pull-down unit 208, the second pull-down unit 212, the second pull-down control unit 214, and the capacitor 216 of the remaining Nth stage shift register circuit 400 The structure, the driving method, and the signal output are similar to those described in FIGS. 2 to 3 and the previous embodiment, and are not described herein again.

FIG. 5 is a schematic diagram of an Nth stage shift register circuit 500 according to a third embodiment of the present invention. The circuit connection relationship between the Nth stage shift register circuit 500 and the Nth stage shift register circuit 200 of FIG. 2 is substantially the same, the only difference is that the switch unit in the drive unit 502 in FIG. 5 has k switches. The unit is electrically connected to the second transistor T3 and the fourth transistor T4, and is sequentially connected to the second transistor T2. A total of k transistors are serially connected after the crystal T4 to sequentially receive the first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3, and the fourth high frequency clock. The signal HC4, ... to the kth high frequency clock signal HCk, and the pulse width of all the high frequency clock signals is the sum of the pulse widths of the high frequency clock signals without overlapping pulse widths, and The seven transistor T7 and the eighth transistor T8 have control terminals for receiving the N+kth main gate signal G(n+k). In this embodiment, the driving unit 502 is coupled to k transistors having high frequency clock signals respectively connected to k such that the output secondary gate signal S(n) also has k high frequency clock signal widths. The first pull-down unit 204, the first pull-down control unit 206, the main pull-down unit 208, the pull-up unit 210, the second pull-down unit 212, the second pull-down control unit 214, and the capacitor of the remaining Nth stage shift register circuit 500 The structure, working mode and signal output of 216 are similar to those described in FIGS. 2 to 3 and the first embodiment, and will not be described herein. k is a natural number not less than 2.

The shift register in the integrated gate driving circuit of the present invention is on the light sensing touch panel, and the Nth stage shift register circuit can generate two different pulse width output signals for providing the light sensing touch panel. The required signal does not require an external driver chip, thereby reducing the manufacturing process and improving the integration of the light-sensitive touch panel, and also integrating the shift register in the gate drive circuit into the light-sensing touch panel. The space can be made around the light-sensing touch panel to achieve a narrow border effect, reducing the number of processes and reducing the manufacturing cost.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. Modifications and refinements are made without departing from the spirit and scope of the present invention. It belongs to the patent protection scope of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

100‧‧‧Light-sensitive touch panel

101‧‧‧Shift register

102‧‧‧First stage shift register circuit

104‧‧‧Second stage shift register circuit

10n, 200, 400, 500‧‧‧Nth stage shift register circuit

110‧‧‧ pixel array

112‧‧‧pixel circuit

114‧‧‧Light sensing circuit

116‧‧‧Processing unit

202‧‧‧ drive unit

204‧‧‧First pulldown unit

206‧‧‧First pull-down control unit

208‧‧‧Main drop-down unit

210, 410‧‧‧ Pull-up unit

212‧‧‧Secondary pull-down unit

214‧‧‧Second pull-down control unit

216‧‧‧ Capacitance

Q(n)‧‧‧N-level drive signal

Q(n+1)‧‧‧N+1 level drive signal

G(1)‧‧‧first-level main gate signal

G(n)‧‧‧Nth primary gate signal

G(n+2)‧‧‧N+2 main gate signal

G(n+k)‧‧‧N+k level main gate signal

G(n-1)‧‧‧N-1 main gate signal

S(1)‧‧‧First-level secondary gate signal

S(n)‧‧‧Nth secondary gate signal

ST(n)‧‧‧N level control signal

K(n)‧‧‧First pulldown control signal

P(n)‧‧‧second pulldown control signal

HC1‧‧‧ first high frequency clock signal

HC2‧‧‧Second high frequency clock signal

HC3‧‧‧ third high frequency clock signal

HC4‧‧‧ fourth high frequency clock signal

HCk‧‧‧ kth high frequency clock signal

LC1‧‧‧ first low frequency clock signal

LC2‧‧‧ second low frequency clock signal

VSS_S‧‧‧ first low voltage

VSS_G‧‧‧ second low voltage

VH1‧‧‧ first high potential

VH2‧‧‧ second high potential

VH3‧‧‧ third high potential

VH4‧‧‧ fourth high potential

T‧‧‧ timeline

T1, t2, t3, t4‧‧‧

T1-T24,...,Tk‧‧‧O crystal

G(1), G(2),..., G(n)‧‧‧ main gate line

S(1), S(2), ..., S(n) ‧ ‧ gate lines

D(1), D(2), ..., D(m)‧‧‧ data lines

R(1), R(2), ..., R(p)‧‧‧ readout lines

120‧‧‧pixel crystal

122‧‧‧Liquid Crystal Capacitor

132‧‧‧Photoelectric crystal

134‧‧‧Reading the crystal

136‧‧‧Read capacitance

140‧‧‧Amplifier

Va‧‧‧ reading voltage

Vgs‧‧‧ gate-source voltage

Vout‧‧‧ output voltage

Vref‧‧‧reference voltage

FIG. 1A is a schematic diagram of a shift register and a pixel array of the light-sensitive touch panel of the present invention.

FIG. 1B is a schematic diagram of a pixel circuit and a light sensing circuit corresponding to the light-sensitive touch panel of the present invention.

2 is a schematic diagram of an Nth stage shift temporary storage circuit according to the first embodiment of the present invention.

Fig. 3 is a schematic diagram showing the waveform of the signal when the Nth stage shift register circuit of Fig. 2 operates.

4 is a schematic diagram of an Nth stage shift temporary storage circuit according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of an Nth stage shift temporary storage circuit according to a third embodiment of the present invention.

200‧‧‧Nth stage shift register circuit

202‧‧‧ drive unit

204‧‧‧First pulldown unit

206‧‧‧First pull-down control unit

208‧‧‧Main drop-down unit

210‧‧‧Upper unit

212‧‧‧Secondary pull-down unit

214‧‧‧Second pull-down control unit

216‧‧‧ Capacitance

Q(n)‧‧‧N-level drive signal

Q(n+1)‧‧‧N+1 level drive signal

G(n)‧‧‧Nth primary gate signal

G(n+2)‧‧‧N+2 main gate signal

S(n)‧‧‧Nth secondary gate signal

ST(n)‧‧‧N level control signal

K(n)‧‧‧First pulldown control signal

P(n)‧‧‧second pulldown control signal

HC1‧‧‧ first high frequency clock signal

HC2‧‧‧Second high frequency clock signal

LC1‧‧‧ first low frequency clock signal

LC2‧‧‧ second low frequency clock signal

VSS_S‧‧‧ first low voltage

VSS_G‧‧‧ second low voltage

T1-T22‧‧‧O crystal

Claims (12)

A shift register having a plurality of stages of shift register circuits, wherein the Nth stage shift register circuit comprises: a driving unit for providing one according to an Nth stage driving signal and a plurality of high frequency clock signals An Nth primary gate signal and an Nth secondary gate signal; a first pulldown unit electrically connected to the driving unit for pulling down the Nth driving signal and the Nth primary gate signal And the Nth secondary gate signal; and a main pull-down unit electrically connected to the driving unit, wherein the main pull-down unit is electrically connected to one of the control terminals of the first transistor and a second transistor a second end, configured to pull down a potential of the control end of the first transistor and a potential of the second end of the second transistor according to an N+k-level main gate signal; wherein the driving unit comprises: the first a transistor having a control terminal for receiving the Nth stage driving signal, a first terminal for receiving a first high frequency clock signal, and a first terminal for providing the Nth stage main gate signal a second end; the second transistor having the control electrically connected to the first transistor a control terminal, a first terminal, and the second terminal for providing the Nth secondary gate signal; and a plurality of switch units having the corresponding k high frequency clock signals a first end and a second end electrically connected to the first end of the second transistor, wherein k is a positive integer not less than 2 and N is Natural number. The shift register according to claim 1, wherein each switch unit is a transistor having a control end, a first end, and a second end, the control end of each switch unit and each The first end of the switch unit is electrically connected to receive the corresponding high frequency clock signals, and the second end of each switch unit is electrically connected to the first end of the second transistor, and the One of the high frequency clock signals is delayed in phase from the previous high frequency clock signal. The shift register according to claim 1, further comprising: a pull-up unit electrically connected to the driving unit; and a first pull-down control unit electrically connected to the first pull-down unit Generating a first pull-down control signal to control operation of the first pull-down unit according to the N-th driving signal and a first low-frequency clock signal; wherein the first pull-down unit is electrically connected to the first The control terminal of the first transistor, the second terminal of the first transistor, and the second terminal of the second transistor are configured to pull down the control terminal of the first transistor according to the first pull-down control signal a potential, a potential of the second end of the first transistor, and a potential of the second end of the second transistor. The shift register according to claim 3, wherein the first pull-down unit comprises: a ninth transistor, the ninth transistor has a control terminal for receiving the first pull-down control signal, and is electrically connected a first end of the second end of the second transistor, and a second end; a tenth transistor, the tenth transistor having the first pull-down control signal a control end electrically connected to a first end of the second end of the first transistor, and a second end; and an eleventh transistor having a first a control terminal of the pull-down control signal, a first end electrically connected to the control end of the first transistor, and a second end, wherein the control end of the ninth transistor, the tenth transistor The control terminal and the control terminal of the eleventh transistor are electrically connected to each other. The shift register according to claim 3, wherein the first pull-down control unit comprises: a twelfth transistor, the twelfth transistor having a control end for receiving the first low frequency clock signal, Electrically connected to a first end and a second end of the control end of the twelfth transistor; a thirteenth transistor having a control end for receiving the Nth stage driving signal a first end electrically connected to the second end of the twelfth transistor, and a second end electrically connected to the second end of the tenth transistor; a fourteenth transistor, the first The fourteenth transistor has a control end electrically connected to the second end of the twelfth transistor, a first end electrically connected to the control end of the twelfth transistor, and electrically connected to the first end a second end of the control terminal of the nine-electrode; and a fifteenth transistor, the fifteenth transistor having a control end electrically connected to the control end of the thirteenth transistor, electrically connected to the a first end of the second end of the fourteenth transistor, and electrically connected to the tenth transistor A second end of the second end. The shift register according to claim 1, wherein the driving unit further comprises a fifth transistor having a control terminal for receiving the Nth driving signal and receiving the first high frequency clock signal One end and one second end are used to output an Nth level control signal. The shift register of claim 3, wherein the pull-up unit comprises a sixth transistor having a control end electrically connected to the second end of the fifth transistor, electrically connected to the first a first end of the second end of the transistor and a second end for providing an N+1th driving signal. The shift register of claim 3, wherein the pull-up unit comprises a sixth transistor having a control terminal for receiving an N-1th main gate signal, electrically connected to the first A first end of the control end of the sixth transistor and a second end electrically connected to the control end of the first transistor. The shift register of claim 1, further comprising a capacitor electrically connected between the control end of the first transistor and the second end of the first transistor. The shift register of claim 1, further comprising: a second pull-down unit electrically connected to the control end of the first transistor, the second end of the first transistor, and the second The second end of the transistor is configured to pull down the potential of the control end of the first transistor, the potential of the second end of the first transistor, and the second of the second transistor according to a second pull-down control signal a potential of the terminal; and a second pull-down control unit electrically connected to the second pull-down unit for generating the second according to the Nth-level driving signal and a second low-frequency clock signal Pull down the control signal. The shift register according to claim 10, wherein the second pull-down unit comprises: a sixteenth transistor, the sixteenth transistor has a control end for receiving the second pull-down control signal, and is electrically connected a first end of the second end of the second transistor, and a second end; a seventeenth transistor, the seventeenth transistor having a control terminal for receiving the second pull-down control signal, electrical a first end and a second end connected to the second end of the first transistor; and an eighteenth transistor having a control end for receiving the second pull-down control signal, Electrically connected to a first end of the control end of the first transistor, and a second end, wherein the control end of the sixteenth transistor, the control end of the seventeenth transistor, and the first The control terminals of the eighteenth transistor are electrically connected to each other. The shift register according to claim 10, wherein the second pull-down control unit comprises: a nineteenth transistor, the nineteenth transistor having a control terminal for receiving the second low frequency clock signal, a first end and a second end of the control terminal of the nineteenth transistor; a twentieth transistor having a control end for receiving the Nth stage driving signal, a first end electrically connected to the second end of the nineteenth transistor, and a second end electrically connected to the second end of the tenth transistor; a second eleven transistor, the first The twenty-one transistor has an electrical connection to the a control end of the second end of the nineteenth transistor, a first end electrically connected to the control end of the nineteenth transistor, and a first end electrically connected to the control end of the sixteenth transistor a second end; and a twenty-two transistor having a control end electrically connected to the control end of the twentieth transistor, electrically connected to the second eleven transistor a first end of the second end and a second end electrically connected to the second end of the tenth transistor.