TWI475568B - Method of improving power efficiency of memory - Google Patents

Description

Method for improving memory power efficiency

The invention relates to a method for improving the power efficiency, in particular to a method for improving the performance of a memory power source.

At present, the number of memory DIMMs (Dual In-line Memory Modules) in the server is increasing. Therefore, the output design of the VRD (Voltage Regulator Down) for buck is also getting larger and larger, and the fixing is not flexible. Thus, whenever fewer DIMMs are installed in the server, the efficiency of the VRD becomes poorer, that is, more energy is wasted.

In view of the above, it is necessary to provide a method for improving the performance of the memory power supply.

A method for improving power efficiency of a memory, comprising the steps of: a ground pin of a memory slot is connected to a pull-up resistor to pull its voltage to a power supply voltage, and is connected to a substrate management controller; when in the memory slot After the memory is installed, the ground pin of the memory slot is detected as a low level signal, and the substrate management controller receives the low level signal when the memory is not installed in the memory slot. Detecting that the ground pin of the memory slot is a high level signal, the substrate management controller receives the high level signal; after the substrate management controller receives the corresponding high level signal, sends the signal The command is applied to a buck regulator that turns off power to the memory slot.

Compared with the prior art, in the method for improving the performance of the memory power supply of the present invention, the buck regulator closes the power supply to the memory slot according to the command, so that the output of the buck regulator is at an optimum efficiency.

Referring to FIG. 1 , a preferred embodiment of the method for improving the power performance of the memory of the present invention includes a buck regulator (VRD), a plurality of memory DIMM slots (DIMM1, DIMM2, ..., DIMM N), and a substrate management. Controller (Baseboard Management Controller, BMC). The buck regulator is connected to a plurality of high-end FETs and a driver for controlling the high-side FET switch, and each of the high-side FET and the driver for controlling the high-side FET switch is connected to an inductor, and each inductor is connected to a DIMM slot. Power pin. The ground pin of each DIMM slot is connected to the substrate management controller by a pull-up resistor R to pull the voltage up to the power supply voltage. It is then connected to the buck regulator by an I2C bus (Inter-Integrated Circuit). Each high-side FET and driver that controls the high-side FET switch acts as a switch.

In another embodiment, the substrate management controller may be replaced with a south bridge wafer integrated with the substrate management controller. A low side field effect transistor and a driver controlling the low side field effect transistor switch replace the high side field effect transistor and the driver that controls the high side field effect transistor switch. An SMBus bus (System Management Bus) replaces the I2C bus.

Referring to FIG. 2, the working principle of the preferred embodiment of the method for improving the performance of the memory power supply of the present invention is as follows:

Step 1: The ground pin of each DIMM slot outputs a mounting signal and is pulled up to the power supply voltage by the pull-up resistor. After the DIMM is mounted on the DIMM slot, the installation signal is a low level signal, and the substrate management controller receives the low level signal when the DIMM is not mounted on the DIMM slot. The installation signal is a high level signal, and the substrate management controller receives the high level signal.

Step 2: Input all the installation signals into the baseboard management controller by serial to parallel or parallel.

Step 3: The baseboard management controller obtains all the installation signals, and according to the VRD efficiency curve, sends the command to the buck regulator through the I2C bus bar or the SMBus bus bar, and the buck regulator will not be installed therein. The high-side FET transistor of the DIMM and its driver are turned off, thereby making the output of the buck regulator optimally efficient, thereby achieving the purpose of improving performance and reducing unnecessary power consumption.

The VRD efficiency curve is a curve in which the buck regulator changes according to the DIMM output current load. The buck regulator is less efficient when the output current load is lighter. Therefore, the output of the buck regulator is at optimum efficiency only when the DIMM is fully loaded with all of the DIMM slots installed. In this way, after the substrate management controller obtains all the installation signals, the buck regulator is sent to the buck regulator through the I2C bus bar or the SMBus bus bar, and the buck regulator will have a high-end field effect in which the DIMM is not installed. The transistor and its driver are turned off, so that the DIMM slot is in a relatively full load condition. According to the VRD efficiency curve, the output of the buck regulator is in an optimum efficiency, thereby achieving the purpose of improving performance and reducing unnecessary energy consumption. .

In summary, the present invention is in accordance with the conditions of the invention patent application, and the patent application is filed according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art to the spirit of the present invention should be included in the following claims.

1 is a circuit diagram of a preferred embodiment of a method for improving the power efficiency of a memory of the present invention.

2 is a flow chart showing the operation of a preferred embodiment of the method for improving the power efficiency of the memory of the present invention.

Claims (9)

A method for improving power efficiency of a memory, comprising the steps of: a ground pin of a memory slot is connected to a pull-up resistor to pull its voltage to a power supply voltage, and is connected to a substrate management controller; when in the memory slot After the memory is installed, the ground pin of the memory slot is detected as a low level signal, and the substrate management controller receives the low level signal when the memory is not installed in the memory slot. Detecting that the ground pin of the memory slot is a high level signal, the substrate management controller receives the high level signal; after the substrate management controller receives the corresponding high level signal, sends the signal The command is applied to a buck regulator that turns off power to the memory slot. The method for improving the power efficiency of a memory according to claim 1, wherein after the substrate management controller receives the corresponding high level signal, issuing a command according to the efficiency curve of the buck regulator The buck regulator. The method for improving the power efficiency of a memory according to claim 1, wherein after the substrate management controller receives the corresponding high level signal, the command is sent to the bus by an internal integrated circuit. The buck regulator is described. The method for improving the power efficiency of a memory according to claim 1, wherein after the substrate management controller receives the corresponding high level signal, the system manages the bus to send the command to the step-down. Regulator. The method for improving the power efficiency of a memory according to claim 1, wherein a switch is connected to the buck regulator for turning off power supply to the memory slot. The method for improving the power efficiency of a memory according to claim 5, wherein the switch is a field effect transistor and a driver module. The method of improving the power efficiency of a memory as described in claim 6 wherein the field effect transistor is a high side field effect transistor. The method of improving the power efficiency of a memory as described in claim 6, wherein the field effect transistor is a low side field effect transistor. The method of improving the power efficiency of a memory according to claim 5, wherein an inductance is connected between the switch and the memory slot.