TWI475354B - Method and apparatus for performing clock extraction - Google Patents

Description

Method and apparatus for clock extraction

The present invention relates to the control of electronic devices conforming to the Universal Serial Bus (USB) 3.0 standard, and more particularly to a method for performing Clock Extraction and related devices.

Portable electronic devices with a Universal Serial Bus Port (USB Port) (eg, a flash drive, an external hard drive, a memory card reader that conforms to one or more standards) Very convenient; in response to user needs, there are many related products on the market to choose from.

According to the related art, in the case where some types of oscillators need to be set in the portable electronic devices, the problems caused by the oscillators will appear one by one. For example, setting up multiple crystal oscillators can make the portable electronic device incapable of having a compact form factor/size. For another example, when the portable electronic device can adopt a high-accuracy voltage-controlled oscillator, the related cost is high. Therefore, there is a need for a novel method for implementing an electronic device having a universal serial bus bar (such as a universal serial bus mass storage device) without setting any oscillator that would hinder cost reduction or hinder the reduction of the size/size. ).

It is an object of the present invention to provide a method for performing Clock Extraction and related devices to solve the above problems.

Another object of the present invention is to provide a method for performing clock extraction and related devices, which can be implemented without setting any voltage-controlled oscillator with high precision. An electronic device of a Universal Serial Bus Port (USB Port) (for example, a universal serial bus mass storage device).

In a preferred embodiment of the present invention, a method for clock extraction is provided, the method being applied to an electronic device, the method comprising: receiving a group of universal serial buss received from the electronic device The training sequence equalization pattern (TSEQ Pattern) carries out an edge analysis to obtain a plurality of edge number estimates; and based on the plurality of edge number estimates and a predetermined threshold value to generate a plurality of The analysis result, wherein the edge quantity estimates are obtained by estimating an edge number corresponding to the plurality of time intervals respectively for the training sequence equalization pattern; and outputting a clock to one of the oscillators according to the plurality of analysis results The frequency is frequency corrected to utilize the output clock as a reference clock after the frequency correction is completed. In particular, the oscillator can be a Numerically Controlled Oscillator (NCO).

While providing the above method, the present invention also correspondingly provides a device for performing clock extraction, the device comprising at least a portion of an electronic device. The device includes: an edge analysis circuit; and a reference clock generator coupled to the edge analysis circuit; wherein the reference clock generator comprises an oscillator and a frequency correction unit, and the frequency correction unit is coupled Connected to the edge analysis circuit and the oscillator. The edge analysis circuit is configured to compare a plurality of edge quantity estimates with a predetermined threshold value in sequence, and receive a training sequence, such as a training sequence received by a group of received signals from a universal serial bus of the electronic device. Performing an edge analysis to obtain a plurality of edge number estimates, and generating a plurality of analysis results based on the plurality of edge number estimates and a predetermined threshold value, wherein the edge number estimates are taken from the training The sequence equalization pattern is performed to estimate the number of edges corresponding to a plurality of time intervals, respectively. Additionally, the reference clock generator is used to generate a reference clock. In addition, the oscillator is used to generate an output clock, and the frequency correcting unit is configured to perform frequency correction on the frequency of the output clock of the oscillator according to the plurality of analysis results, so as to complete the frequency correction. The output clock is used as the reference clock. In particular, the oscillator can be a numerically controlled oscillator.

One of the advantages of the present invention is that the reference clock generator can perform the frequency correction on the frequency of the output clock of the oscillator according to the frequency at which the different types of analysis results alternate among the plurality of analysis results. The device uses the output clock as the reference clock after the frequency correction is completed, whereby the electronic device does not need to set any voltage controlled oscillator having an accuracy corresponding to a frequency offset ratio of less than 10%. Since there is no need to set a high-precision voltage-controlled oscillator, the method and apparatus of the present invention can save associated costs. In addition, since it is not necessary to provide a plurality of crystal oscillators, the method and apparatus of the present invention can save the associated cost, and the electronic device implemented in accordance with the method and apparatus of the present invention can have a compact appearance/size.

100‧‧‧Devices for clock extraction

110‧‧‧ Clock data recovery circuit

110PD‧‧‧ phase detector

110PFD‧‧‧ phase frequency detector

110SW‧‧‧Switch unit

112‧‧‧ comparator

114‧‧‧Solution multiplexer

116‧‧‧Variable Control Oscillator

118‧‧‧Transition module

120‧‧‧Edge analysis circuit

122‧‧‧ Training sequence equalization edge calculator

124‧‧‧Comparative unit

130‧‧‧Reference clock generator

132‧‧‧ Frequency Correction Unit

134‧‧‧Numerical Controlled Oscillator

150‧‧‧Microprocessor

200‧‧‧Methods for clock extraction

210,220‧‧ steps

510-1, 510-2, 510-3, ... 510-39‧‧‧ Mutual or arithmetic unit

520‧‧‧Addition unit

CLK, TSEQ_CLK‧‧‧ clock

D0, D1, D2, D3, ... D38, D39‧‧‧ correspond to the complex multiplex signal of multiple bits

Edge_No‧‧‧Edge Estimate

Edge_Density‧‧‧ corresponds to the analysis of edge density

PTSEQ‧‧‧ training sequence equalization pattern

REF_CLK‧‧‧ reference clock

RXP, RXN‧‧‧ receive signal

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an apparatus for performing Clock Extraction in accordance with a first embodiment of the present invention.

2 is a flow chart of a method for performing clock extraction in accordance with an embodiment of the present invention.

Figure 3 illustrates the edge analysis involved in the method of Figure 2 in one embodiment.

FIG. 4 is a diagram showing related parameters and related signals involved in the method shown in FIG. 2 in an embodiment.

FIG. 5 is a diagram showing the implementation details of the training sequence equalization pattern (TSEQ Pattern) edge calculator shown in FIG. 1 in one embodiment.

Figure 6 is a diagram showing the implementation details of the method shown in Figure 2 in one embodiment.

1 is a schematic diagram of an apparatus 100 for performing Clock Extraction in accordance with a first embodiment of the present invention. The device 100 can include at least a portion (eg, a portion or all) of an electronic device, wherein examples of the electronic device can include, but are not limited to, a flash drive, an external hard drive, and a memory card that conforms to one or more standards. Card machine. For example, device 100 can include a portion of the electronic device, such as control circuitry for the electronic device. For another example, the device 100 can include all of the electronic device, that is, the entirety of the electronic device. According to this embodiment, the electronic device can conform to a universal serial bus (Universal Serial Bus, which can be simply referred to as "USB"). 3.0 standard or derivative version of the USB 3.0 standard.

As shown in FIG. 1, the device 100 includes a comparator 112, a De-Multiplexer 114, a Voltage Controlled Oscillator (hereinafter referred to as "VCO") 116, and an edge analysis circuit. 120, and a reference clock generator 130, wherein the edge analysis circuit 120 includes a training sequence equalization pattern (TSEQ Pattern) edge calculator 122 (hereinafter referred to as "TSEQ type edge calculator"; In the first figure, it is labeled "P _TSEQ edge calculator", wherein the symbol "P _TSEQ " represents the training sequence equalization pattern) and a comparison unit 124 (labeled as ">30" in the first figure, wherein the symbol ">30" represents a comparison with a predetermined value of 30 as the threshold value, and the reference clock generator 130 includes a frequency correcting unit 132, and further includes an oscillator such as a numerically controlled oscillator (hereinafter referred to as a numerically controlled oscillator). "NCO") 134. The device 100 can receive a set of receiving signals RXP and RXN from the Universal Serial Bus Port (hereinafter referred to as “USB埠”) by using the comparator 112, and utilize the architecture shown in FIG. The reference clock REF_CLK is obtained from the information received by the group receiving signals RXP and RXN without setting any VCO with high precision.

According to the embodiment, the edge analysis circuit 120 is configured to receive a training sequence equalization type P _TSEQ (hereinafter referred to as "TSEQ type" for the set of received signals RXP and RXN received from the USB port of the electronic device. Performing an edge analysis to obtain a plurality of edge number estimates, and dynamically generating a plurality of analysis results according to the plurality of edge number estimates and a predetermined threshold value (eg, 30), wherein the number of edge numbers is estimated The TSEQ pattern is taken from an estimate of the number of edges corresponding to a plurality of time intervals, respectively. Additionally, reference clock generator 130 is used to generate reference clock REF_CLK. In addition, the NCO 134 is used to generate an output clock, and the frequency correcting unit 132 is configured to perform the frequency of the output clock of the NCO 134 according to the frequency at which the different types of analysis results of the plurality of analysis results alternate. Frequency correction is used to use the output clock as the reference clock REF_CLK after the frequency correction is completed. In practice, the reference clock REF_CLK and the output clock of the NCO 134 can be the same signal, wherein the device 100 can complete the frequency correction after being controlled by a microprocessor (not shown in FIG. 1). Start using the reference clock REF_CLK to avoid taking the frequency of unfinished correction from the reference clock REF_CLK before the frequency correction is completed. For the sake of simplicity, the reference clock REF_CLK and the output clock of the NCO 134 may be collectively labeled as "REF_CLK" in FIG.

Please note that there may be no VCO having an accuracy corresponding to a frequency offset ratio of less than 10% in the electronic device; this means that the frequency offset ratio of any VCO in the electronic device of the embodiment is 10% or more. For example, the clock CLK of the VCO 116 has a frequency of about 5 GHz (Gigahertz, ie, a billion Hz), especially in the interval [(5 GHz)*(1-10%), (5 GHz)*(1+) The range of 10%)] has a corresponding frequency offset ratio of 10%. By utilizing the architecture shown in FIG. 1, the device 100 can receive information from the group of received signals RXP and RXN, such as the TSEQ type P _TSEQ, accurately without locking the phase of the set of received signals RXP and RXN. A frequency of 15.625 MHz (Megahertz, megahertz) is obtained to generate a reference clock REF_CLK having a frequency of 15.625 MHz for the device 100 to perform at least a portion of a series of preparatory operations for clock data recovery (eg, a portion or All), without the need to use any high-precision VCO such as any VCO with an accuracy corresponding to a frequency offset ratio of less than 10%. For example, the series of preparatory operations may include: the device 100 performs phase frequency detection to lock the frequency of the group of receiving signals RXP and RXN; and after locking the frequency of the group of receiving signals RXP and RXN, the device 100 further performs phase detection. The phase of the group receiving signals RXP and RXN is locked; wherein after the phase of the group receiving signals RXP and RXN is locked, the device 100 can correctly obtain the data carried by the group of receiving signals RXP and RXN. For further details on the operation of device 100, please refer to Figure 2 for further explanation.

2 is a flow chart of a method 200 for performing clock extraction in accordance with an embodiment of the present invention. The method 200 described above can be applied to the apparatus 100 shown in Fig. 1; the method is described as follows:

In step 210, the edge analysis circuit 120 receives the training sequence equalization pattern received by the group of the USB ports received from the electronic device, such as the TSEQ type P carried by the group of received signals RXP and RXN. _TSEQ , performing edge analysis to dynamically generate a plurality of analysis results. In particular, the edge analysis circuit 120 performs edge analysis on the TSEQ type P _TSEQ carried by the group of received signals RXP and RXN to obtain a plurality of edge number estimates, and based on the plurality of edge number estimates and a predetermined threshold Values such as those described above (eg, 30; again, for example, a positive integer close to 30) to dynamically generate a plurality of analysis results, wherein the estimate of the number of edges is taken from the TSEQ pattern corresponding to a plurality of time intervals, respectively. Estimated number of edges.

In step 220, the frequency correcting unit 132 performs the above-mentioned frequency correction on the frequency of the output clock of the NCO 134 according to the frequency at which the different types of analysis results among the plurality of analysis results alternately occur, so as to be utilized after the frequency correction is completed. This output clock is used as the reference clock REF_CLK.

According to this embodiment, the comparator 112 can compare the group of receiving signals RXP and RXN with each other to generate a non-differential receiving signal corresponding to one of the group of receiving signals RXP and RXN, and the demultiplexer 114 can receive the non-differential receiving. The signal performs a multiplex operation to generate a set of demultiplexed signals respectively corresponding to the plurality of bits, wherein the order of the plurality of bits corresponds to the order in which the pre-multiplexed original information is received in the non-differential signal. For example, the group of multiplexed signals may be forty multiplexed signals corresponding to forty bits {B0, B1, ..., B39}, which are forty-bit parallel transmission signals. For the sake of brevity, such a 40-bit parallel transmission signal can be simply labeled "40b" in FIG. Please note that the bit information such as the above-mentioned forty bits {B0, B1, ..., B39} is originally contained in the group of receiving signals RXP and RXN, and can be solved by the solution multiplexer 114. The operation obtains the multiplex signal {D0, D1, ..., D39} and then the multiplex signal {D0, D1, ..., D39} can be transmitted in parallel to the TSEQ pattern edge calculator 122. In addition, the TSEQ type edge calculator 122 can compare each of the two adjacent bits in the plurality of bits (such as the forty bits {B0, B1, ..., B39}). The voltage levels of the multiplexed signals are resolved to perform the edge analysis described above. The advantage of demultiplexing the received signals RXP and RXN to generate the multiplexed signals {D0, D1, ..., D39} can reduce the operating frequency of subsequent circuits to reduce the complexity of subsequent circuits.

Please note that FIG. 2 depicts the workflow including step 210 and step 220. This is for illustrative purposes only and is not a limitation of the invention. This workflow can be varied in accordance with various variations of this embodiment. For example, at least a portion of the operation of step 210 and/or at least a portion of the operation of step 220 can be performed repeatedly. For another example, at least a portion of the operation of step 210 and at least a portion of the operation of step 220 can be performed simultaneously.

Please refer to Figure 3. Figure 3 illustrates the edge analysis involved in the method 200 of Figure 2 in one embodiment. When the edge analysis circuit 120 performs the edge analysis, the TSEQ pattern edge calculator 122 therein is based on the plurality of bits (such as the forty bits {B0, B1, ..., B39}). The voltage level of each of the demultiplexed signals corresponding to each two adjacent bits generates an edge number estimate Edge_No corresponding to each time interval for the TSEQ type P _TSEQ , such as shown in FIG. 3, for The use of the plurality of analysis results. For example, under ideal conditions, when the logical value of the TSEQ type P _TSEQ is the column of each column shown in FIG. 3 {{0011111010}, {0101001110}, {0001011011}, {0110000110}}, {{0010111011 },{0100111010},{0001110001},{1011010100}},...,and{{0101010101},{0101010101},{0101010101},{0101010101}} (ie, starting from the upper left corner, from left to right The top-down row of bits, the TSEQ-type edge calculator 122 may generate edge number estimates Edge_No such as {20, 22, 20, 26, 39, 39, 39, respectively, corresponding to respective time intervals. 39, 21, ..., 39}, wherein any one of the above-mentioned columns of bits can be regarded as one of the above-mentioned forty bits {B0, B1, ..., B39}. Then, the comparing unit 124 sequentially compares the edge number estimation value {Edge_No} with the predetermined threshold value, such as the predetermined value 30, to generate a comparison signal carrying the plurality of analysis results, wherein the comparison signal The frequency at which different levels alternately represents the frequency at which the different types of analysis results alternate between the plurality of analysis results, and the frequency should be a certain value according to the USB 3.0 standard, so it can be used to generate the reference clock REF_CLK.

In practice, the comparison signal can be the clock TSEQ_CLK shown in FIG. 1 , which can be at a high voltage level or a low voltage level. For example, the high voltage level can be used to indicate that the edge number estimate Edge_No is greater than the predetermined threshold value, and the low voltage level can be used to indicate that the edge number estimate Edge_No is less than or equal to the predetermined threshold value. However, this is for illustrative purposes only. It is not intended to limit the invention. According to a variant of this embodiment, the low voltage level can be used to indicate that the edge number estimate Edge_No is greater than the predetermined threshold value, and the high voltage level can be used to indicate that the edge number estimate Edge_No is less than or equal to the predetermined threshold value.

As shown in FIG. 3, based on the comparison operation disclosed above, the plurality of analysis results may include two analysis results Edge_Density corresponding to the edge density, such as an analysis result corresponding to 50% of the edge density and 100% corresponding to the edge density. The analysis results, wherein the former and the latter can be represented by the low voltage level and the high voltage level, respectively. Thus, in the case where the TSEQ type P _TSEQ conforms to the USB 3.0 standard, the frequency at which the different levels of the clock TSEQ_CLK alternate may approach 15.625 MHz. Thus, the device 100 can perform the above-described frequency correction according to the frequency at which the different levels of the clock TSEQ_CLK alternately occur to correctly generate the reference clock REF_CLK. This is for illustrative purposes only and is not a limitation of the invention. According to some variations of the embodiment shown in FIG. 3, the edge analysis circuit 120 may first calculate an estimate of the edge number {Edge_No} corresponding to the plurality of edges (for example, the edge number estimate {20 shown in FIG. 3, 22,20,26,39,39,39,39,21,...,39}) edge density, such as edge density {20/40, 22/40, 20/40, 26/40, 39/40 , 39/40, 39/40, 39/40, 21/40, ..., 39/40}, ie {50%, 55%, 50%, 65%, 97.5%, 97.5%, 97.5%, 97.5%, 52.5%, ..., 97.5%}. In addition, the edge analysis circuit 120 can sequentially apply the edge densities such as {50%, 55%, 50%, 65%, 97.5%, 97.5%, 97.5%, 97.5%, 52.5%, ..., 97.5%}. Comparing with another predetermined threshold value (eg, 75%; for example, a positive number close to 75%) to generate the plurality of analysis results, wherein the other predetermined threshold value corresponds to the embodiment shown in FIG. The predetermined threshold value is described. For example, in the case where the predetermined threshold value described in the embodiment shown in FIG. 2 is equal to 30, the other predetermined threshold value may be 30/40, that is, 75%. Note that the denominator "40" used in calculating the edge density can be changed as long as it does not affect the implementation of the present invention.

FIG. 4 is a diagram showing related parameters and related signals involved in the method 200 shown in FIG. 2 in an embodiment. As shown in FIG. 4, the related parameters include an edge result of Edge_Density corresponding to the edge density and an edge number estimate Edge_No, and the related signal includes the clock TSEQ_CLK and the group of received signals carrying the TSEQ type P _TSEQ RXP and RXN, where the latter is designated herein as "P _TSEQ " to emphasize the TSEQ type P _TSEQ contained in the set of received signals RXP and RXN.

Note that under ideal conditions, the plurality of analysis results may correspond exactly to a series of edge densities of the TSEQ type P _TSEQ . Under actual conditions, although the edge number estimation value Edge_No may have some errors, if the threshold value of the comparison unit 124 is appropriately selected, the errors may be reduced, so that the errors are insufficient to cause the clock TSEQ_CLK to be abnormally reversed. It does not interfere with the above frequency correction.

Figure 5 is a diagram showing the implementation details of the TSEQ-type edge calculator 122 shown in Figure 1 in an embodiment, wherein the symbols {D0, D1, D2, D3, ..., D38, D39} represent Solve the multiplex signal. The TSEQ-type edge calculator 122 includes a plurality of exclusive OR (XOR) operation units {510-1, 510-2, 510-3, ..., 510-39} coupled to the demultiplexer 114. Addition unit 520. According to this embodiment, the multiplexed signal {D0, D1, ..., D39} can be used as an example of the above forty multiplexed signals.

As shown in FIG. 5, the mutually exclusive or arithmetic unit {510-1, 510-2, 510-3, ..., 510-39} can solve the multiplexed signals {D0, D1, ..., D39} multiple times. The voltage levels are mutually exclusive or operational to produce complex arrays of mutually exclusive or operational results corresponding to different points in time. The adding unit 520 may calculate the sum of the mutually exclusive or operational results of each group, and use the respective sums respectively corresponding to the time points as the estimated number of edges corresponding to the different time intervals for the TSEQ type P _TSEQ respectively {Edge_No} for the purpose of generating the plurality of analysis results. For example, the logical values of the demultiplexed signals {D0, D1, ..., D39} are respectively equal to the forty bits of the first column of the TSEQ type P _TSEQ shown in FIG. 3 {{0011111010} In the case of {0101001110}, {0001011011}, {0110000110}}, the edge number estimate Edge_No generated by the architecture shown in Fig. 5 is equal to the value 20. For another example, the logical values of the multiplexed signal {D0, D1, ..., D39} are respectively equal to the forty bits of the last column of the TSEQ type P _TSEQ shown in FIG. 3 {{0101010101} In the case of {0101010101}, {0101010101}, {0101010101}}, the edge number estimate Edge_No generated by the architecture shown in Fig. 5 is equal to the value 39.

FIG. 6 illustrates implementation details of the method 200 shown in FIG. 2 in an embodiment. As shown in FIG. 6, the device 100 includes a clock data recovery circuit (hereinafter referred to as "CDR circuit") 110 and a control logic circuit 150. In addition to the comparator 112, the demultiplexer 114, and the VCO 116 shown in FIG. 1, the CDR circuit 110 may further include a conversion module 118, a switching unit 110SW, a phase frequency detector 110PFD, And a phase detector 110PD.

According to the embodiment, the control logic circuit 150 can control the switching unit 110SW to switch to output one of the first detection signals output by the phase frequency detector 110PFD and the second detection signal output by the phase detector 110PD. One of them is provided to the conversion module 118. In addition, the conversion module 118 can adjust the input voltage level of the VCO 116 according to the first detection signal or the second detection signal received by the switching unit 110SW to control the frequency of the clock CLK. In practice, the conversion module 118 can be provided with a charge pump (not shown) and associated control circuitry for generating the input voltage level of the VCO 116.

First, in the case that the switching unit 110SW provides the first detection signal to the conversion module 118, the phase frequency detector 110PFD can perform phase frequency detection according to the reference clock REF_CLK and the clock CLK to generate the first detection. Test signal. Thus, by utilizing the architecture shown in Figure 1, device 100 locks the frequency of the set of received signals RXP and RXN. After the device 100 locks the frequency of the group receiving signals RXP and RXN, the control logic circuit 150 controls the switching unit 110SW to switch to receive the second detection signal. In the case that the switching unit 110SW provides the second detection signal to the conversion module 118, the phase detector 110PD can perform phase detection according to the clock CLK and the group of receiving signals RXP and RXN to generate the second detection. Signal. Thus, the CDR circuit 110 locks the phase of the set of received signals RXP and RXN. In this case, since the frequency and phase of the clock CLK coincide with the frequency and phase of the group of received signals RXP and RXN, the device 100 can use the CDR circuit 110 correctly after locking the phases of the group of received signals RXP and RXN. The information received by the group receiving signals RXP and RXN is obtained.

Based on the above various embodiments, the reference clock generator 130 can perform the plurality of analyses according to the plurality of The frequency at which the different types of analysis results alternate occurs to correct the frequency of the output clock of the NCO 134, so that the device 100 uses the output clock as the reference clock REF_CLK after completing the frequency correction. Therefore, when the frequency correction is completed, the CDR circuit 110 does not need to first lock the phase of the group of received signals RXP and RXN. In particular, when the frequency correction is completed, the CDR circuit 110 has not locked the phase of the set of received signals, and it is not necessary for some conventional electronic devices to lock the phase of the set of received signals. Therefore, the electronic device implemented in accordance with the method and apparatus of the present invention can avoid unnecessary waiting by the user.

Please note that the device 100 uses the output clock as the reference clock REF_CLK after the frequency correction is completed, whereby the CDR circuit 110 can perform at least a part (eg, part or all) of the series of preparatory operations described above. As a result of the preliminary operation of the series, the device 100 can use the CDR circuit 110 to lock the frequency and phase of the set of received signals RXP and RXN and correctly obtain the data contained in the set of received signals RXP and RXN.

One of the advantages of the present invention is that the reference clock generator 130 can perform the frequency correction on the frequency of the output clock of the NCO 134 according to the frequency at which the different types of analysis results alternate among the plurality of analysis results. The device 100 uses the output clock as the reference clock REF_CLK after the frequency correction is completed, whereby the electronic device does not need to set any VCO having an accuracy corresponding to a frequency offset ratio of less than 10%. Since there is no need to set a high precision VCO, the associated method and apparatus can be used to save associated costs. In addition, since it is not necessary to provide a plurality of crystal oscillators, the method and apparatus of the present invention can save the associated cost, and the electronic device implemented in accordance with the method and apparatus of the present invention can have a compact appearance/size.

100‧‧‧Devices for clock extraction

112‧‧‧ comparator

114‧‧‧Solution multiplexer

116‧‧‧Variable Control Oscillator

120‧‧‧Edge analysis circuit

122‧‧‧ Training sequence equalization edge calculator

124‧‧‧Comparative unit

130‧‧‧Reference clock generator

132‧‧‧ Frequency Correction Unit

134‧‧‧Numerical Controlled Oscillator

CLK, TSEQ_CLK‧‧‧ clock

REF_CLK‧‧‧ reference clock

RXP, RXN‧‧‧ receive signal

Claims (20)

A method for performing Clock Extraction, the method being applied to an electronic device, the method comprising: receiving a Universal Serial Bus Port (USB Port) received from the electronic device A training sequence equalization pattern (TSEQ Pattern) carried out by one of the group receiving signals performs edge analysis to obtain a plurality of edge number estimates; and based on the plurality of edge number estimates and a predetermined threshold value And generating a plurality of analysis results, wherein the edge quantity estimates are obtained by estimating an edge number corresponding to the plurality of time intervals respectively for the training sequence equalization pattern; and performing an oscillator according to the plurality of analysis results The frequency of an output clock is frequency corrected to utilize the output clock as a reference clock after completion of the frequency correction. The method of claim 1, further comprising: comparing the set of received signals to each other to generate a non-differential receiving signal corresponding to one of the group of received signals; and demultiplexing the non-differential receiving signal Operating to generate a set of demultiplexed signals respectively corresponding to a plurality of bits, wherein the order of the plurality of bits corresponds to an order in which the pre-multiplexed original information is received in the non-differential signal; wherein the pair is received from the electronic device The step of performing the edge analysis to obtain the plurality of edge number estimates according to the training sequence equalization type carried by the group of received signals of the universal sequence bus includes: comparing the plurality of bits The edge analysis is performed for each voltage level of each of the two multiplexed signals corresponding to the multiplexed signals. The method of claim 2, wherein the edge analysis is performed on the training sequence equalization type contained in the group of received signals received from the universal sequence bus of the electronic device to obtain the plurality of The step of estimating the number of edges further includes: performing multiple exclusive OR (XOR) operation on the voltage levels of the demultiplexed signals corresponding to each of the two adjacent bits of the plurality of bits, Generating a complex array of mutually exclusive or operational results corresponding to different points in time; and calculating a sum of each set of mutually exclusive or operational results, and using the sum corresponding to the respective time points as an equalization pattern for the training sequence Corresponding to the estimated number of edges of different time intervals, respectively, for generating the plurality of analysis results. The method of claim 3, wherein the step of generating the plurality of analysis results according to the plurality of edge number estimates and the predetermined threshold value further comprises: sequentially determining the edge quantity estimates and the predetermined threshold Comparing values to generate a comparison signal carrying the plurality of analysis results, wherein the frequency at which the different levels of the comparison signal alternately represents a frequency at which different types of analysis results alternate among the plurality of analysis results, and the frequencies The frequency at which the different types of analysis results alternate appears to be used to correct the frequency of the output clock of the oscillator. The method of claim 2, wherein the edge analysis is performed on the training sequence equalization type contained in the group of received signals received from the universal sequence bus of the electronic device to obtain the plurality of The step of estimating the edge number further includes: when performing the edge analysis, generating a uniformity for the training sequence according to respective voltage levels of the demultiplexed signals corresponding to each of the two adjacent bits of the plurality of bits The samples respectively correspond to edge quantity estimates of different time intervals for generating the plurality of analysis results; wherein the plurality of edge number estimates and the predetermined threshold value are used to generate a plurality of analyses The step of the result further comprises: sequentially comparing the edge quantity estimates with the predetermined threshold value to generate a comparison signal carrying the plurality of analysis results, wherein the frequency of the different levels of the comparison signal alternately appears The frequencies at which the different types of analysis results alternate between the plurality of analysis results, and the frequencies at which the different types of analysis results alternate appear to be used to correct the frequency of the output clock of the oscillator. The method of claim 1, further comprising: calculating an edge density respectively corresponding to the plurality of edge number estimates; and sequentially comparing the edge densities with the predetermined threshold to generate the Multiple analysis results. The method of claim 1, wherein the clock data recovery circuit (CDR Circuit) of the electronic device has not locked the phase of the group of received signals when the frequency correction is completed. The method of claim 1, further comprising: using the output clock as the reference clock after the frequency correction is completed, whereby one of the electronic devices is when the frequency correction is completed The Clock Data Recovery Circuit (CDR Circuit) does not need to lock the phase of the received signal. The method of claim 1, wherein in the electronic device, there is no voltage controlled oscillator having an accuracy corresponding to a frequency offset ratio of less than 10%. The method of claim 1, wherein the method further comprises: The output clock is used as the reference clock after the frequency correction is completed, whereby the electronic device does not need to set any voltage controlled oscillator having an accuracy corresponding to a frequency offset ratio of less than 10%. A device for performing Clock Extraction, the device comprising at least a portion of an electronic device, the device comprising: an edge analysis circuit for receiving a common sequence bus from the electronic device ( One of the groups of the Universal Serial Bus Port (USB Port) receives a training sequence equalization pattern (TSEQ Pattern) for edge analysis to obtain a plurality of edge number estimates, and according to the plurality of An edge number estimate and a predetermined threshold value to generate a plurality of analysis results, wherein the edge number estimates are obtained from edge quantity estimates corresponding to the plurality of time intervals respectively for the training sequence equalization pattern; and a reference a clock generator coupled to the edge analysis circuit for generating a reference clock, wherein the reference clock generator comprises: an oscillator for generating an output clock; and a frequency correction unit coupled The edge analysis circuit and the oscillator are configured to output the clock of the oscillator according to the plurality of analysis results Frequency correction rate, the clock as the reference clock time to completion after the frequency correction utilizing the output. The device of claim 11, further comprising: a comparator coupled to the universal sequence bus 埠 for comparing the set of received signals with each other to generate one of the received signals corresponding to the group a differential multiplexer coupled to the comparator for demultiplexing the non-differential received signal to generate a set of multiplexed signals corresponding to the plurality of bits, wherein The plural The order of the bits corresponds to the sequence of the pre-multiplexed original information in the non-differential receiving signal; wherein the edge analysis circuit comprises: a training sequence equalization type edge calculator coupled to the demultiplexer, The edge analysis is performed by comparing the respective voltage levels of the demultiplexed signals corresponding to each of the two adjacent bits of the plurality of bits. The device of claim 12, wherein the training sequence equalization edge calculator comprises: a plurality of exclusive OR (XOR) operation units coupled to the demultiplexer for Multipleiating or operating the respective voltage levels of the demultiplexed signals corresponding to each of the two adjacent bits of the plurality of bits to generate a complex array mutual exclusion or operation result corresponding to different time points respectively And an addition unit coupled to the plurality of mutually exclusive or arithmetic units for calculating a sum of each group of mutually exclusive or operational results, and using the sum corresponding to the respective time points as equalization for the training sequence The patterns correspond to edge quantity estimates for different time intervals, respectively, for use in generating the plurality of analysis results. The apparatus of claim 13 , wherein the edge analysis circuit further comprises: a comparison unit coupled to the training sequence equalization edge calculator for sequentially estimating the number of edges Comparing the predetermined threshold values to generate a comparison signal carrying the plurality of analysis results, wherein the frequency at which the different levels of the comparison signal alternately represents a frequency at which different types of analysis results alternate among the plurality of analysis results, The frequencies at which the different types of analysis results alternate appear to be used to correct the frequency of the output clock of the oscillator. The device of claim 12, wherein the edge sequence analysis circuit performs the edge analysis, wherein the training sequence equalization edge calculator is based on each two adjacent bits of the plurality of bits The respective voltage levels of the multiplexed signals corresponding to the meta-response generate an estimate of the edge number corresponding to the different time intervals for the training sequence equalization type for generating the plurality of analysis results; and the edge analysis The circuit further includes: a comparison unit coupled to the training sequence equalization edge calculator for sequentially comparing the edge number estimates with the predetermined threshold to generate the plurality of analysis results a comparison signal, wherein the frequency at which the different levels of the comparison signal alternately represents a frequency at which different types of analysis results alternate among the plurality of analysis results, and the frequencies of the different types of analysis results alternately appear to be used The frequency of the output clock of the oscillator performs this frequency correction. The apparatus of claim 11, wherein the edge analysis circuit calculates edge densities respectively corresponding to the plurality of edge number estimates, and sequentially compares the edge densities with the predetermined threshold values to generate The plurality of analysis results. The device of claim 11, wherein the clock data recovery circuit (CDR Circuit) of the electronic device has not locked the phase of the group of received signals when the frequency correction is completed. The device of claim 11, wherein the device uses the output clock as the reference clock after completing the frequency correction, thereby, when the frequency correction is completed, the clock data of the electronic device The Clock Data Recovery Circuit (CDR Circuit) does not need to lock the phase of the received signal. The device of claim 11, wherein the electronic device does not exist There is a voltage controlled oscillator corresponding to an accuracy of a frequency offset ratio of less than 10%. The device of claim 11, wherein the device uses the output clock as the reference clock after completing the frequency correction, whereby the electronic device does not need to be provided with any corresponding frequency offset ratio less than 10 % precision voltage controlled oscillator.