TWI474333B - Single-ended multi-port storage device - Google Patents

Description

Single-ended multi-storage storage device

The present invention relates to a storage device, and more particularly to a storage device for single-ended multi-turns.

According to the development of multi-core system single-chip, more and more memory will be integrated into the system chip to help the core operations, so the memory must occupy most of the area on the future wafer, and become A very important factor affecting system chip performance, and will consume a lot of energy; therefore, how to effectively reduce the memory area and its power consumption must become an important issue.

Please refer to the first figure, which is a circuit diagram of a storage device of the prior art. As shown, the prior art storage device includes a first inverter 10', a second inverter 20' and an access port 30'. The input end of the first inverter 10' is coupled to the output end of the second inverter 20'; the output end of the first inverter 10' is coupled to the input end of the second inverter 20', and the access port 30 is accessed. 'coupled to the second inverter 20' and a bit line (Bitline, BL), and coupled with a word line (Wordline, WL), the access port 30' is an N-type gold oxygen half field Effect transistor (NMOS), so when the bit line is high, the access port 30' is turned on, and there will be a threshold voltage across the access port 30', so that the effective voltage of the bit line voltage to the storage device is reduced. Therefore, please refer to the second figure, which is a circuit diagram of another conventional storage device. As shown, the access port 30' is replaced by a P-type metal oxide half field effect transistor (PMOS). Therefore, when the bit line is high, after the access port 30' is turned on, the voltage of the bit line will be transferred to the storage device without loss.

When the general bit line reads and writes the logic value "1" in the single-ended memory device, the bit line will remain at the high level first, and the word line will be turned on. Thus, single-ended storage The device cannot know whether the bit line and the word line are moving to read or write a logical value of "1". Therefore, the storage device is designed to write data or read data according to bit lines of different levels. When the storage device reads, the bit line must be converted to a voltage level slightly lower than the voltage level. Reading the data stored in the first inverter 10' and the second inverter 20' through the access port 30; when the storage device performs writing, the bit line must be converted to a high voltage level to The storage unit formed by the first inverter 10' and the second inverter 20' is written through the access port 30'. However, if the architecture has a low static noise margin (SNM), it must pay attention to the size of the transistor of the storage device, and it is difficult to extend multiple access ports.

In addition, the storage device has another design to maintain good static noise boundaries and use different levels of word lines for writing and reading storage devices that use low-level word lines to read Storage device data: Use high-level word lines to write data to the storage device. However, this method must additionally use a DC-DC converter or a charging pump, which increases the complexity of the circuit and increases the power consumption.

Therefore, how to solve the above problems and propose a novel single-ended multi-storage storage device, which can utilize the high-density advantage of single-ended memory components, for reading and writing to speed up memory efficiency, and writing to memory cells. Improvements in speed and power consumption further improve the performance of memory on a single-chip multi-core system.

One of the objectives of the present invention is to provide a single-ended multi-turn storage device with an equalizer and a virtual ground in a memory unit to reduce the power consumption required when data is written into the storage device.

One of the objects of the present invention is to provide a single-ended multi-turn storage device that accelerates the writing of data to a storage device by using an equalizer and a virtual ground in a memory unit.

One of the objects of the present invention is to provide a single-ended multi-turn storage device that simplifies the complexity of the storage device and thereby saves costs.

The memory unit in the single-ended multi-device storage device of the present invention comprises a first inverter, a second inverter, an equalizer and a complex access port. The first inverter has a first input end and a first output end, and is coupled to a power supply and a virtual ground. The second inverter has a second input end and a second output end coupled to the second input end. a first output end, the second output end is coupled to the first input end, and the second inverter is coupled to the power source and the virtual ground, and the equalizer is coupled to the first inverter and the second inverter to control the first reverse The potential of the phase comparator and the second phase comparator, the plurality of access ports are coupled to the first inverter and the second inverter, and coupled to the one bit line and the one word line.

Furthermore, the single-ended multi-turn storage device of the present invention further includes a blocking unit coupled between the virtual ground and the ground to prevent large data from being written into the storage device due to an unstable state in the storage device. Current flows through the storage device.

Moreover, the single-ended multi-port storage device of the present invention can read data at the same time, but if the data is to be written into the storage device, only one data is written, and the other devices must be in the off state ( Not for reading and writing).

The third figure is a block diagram of a preferred embodiment of the present invention. As shown in the figure, the single-ended multi-port storage device of the present invention can be any device having a storage function, such as: a state random access memory (SRAM), a file register (Register). File, a buffer, a Context Addressable Memory (CAM); and the storage device includes a plurality of memory cells, the memory cells including a first inverter 10, The second inverter 20, an equalizer 30 (Equalizer) and a plurality of access ports 40, 42, 44. The first inverter 10 has a first input end and a first output end, and is coupled to a power source Vdd and a virtual ground V_Gnd, and the second inverter 20 has a second input end and a second output end. The second input end is coupled to the first output end, the second output end is coupled to the first input end, and the second inverter 20 is coupled to the power supply Vdd and the virtual ground V_Gnd, such that the first inverter 10 and the second reverse Phaser 20 forms an inverter pair to store data for access to 40, 42, 44 to read or write data. The fourth embodiment is a circuit diagram of a storage device according to a preferred embodiment of the present invention. As shown, the first inverter 10 and the second inverter 20 are a Complemental Metal Oxide Semiconductor Field Effective Transistor (CMOSFET). The first inverter 10 includes a first transistor 12 and a second transistor 14. That is, one end of the first transistor 12 is coupled to the power source Vdd, one end of the second transistor 14 is coupled to the virtual ground V_Gnd, the other end is connected in series with the first transistor 12, and the gate of the first transistor 12 is The gate of the second transistor 20 is coupled; the second inverter 20 includes a third transistor 22 and a fourth transistor 24. The third transistor 22 has one end coupled to the power source Vdd, one end of the fourth transistor 24 is coupled to the virtual ground V_Gnd, and the other end of the fourth transistor 24 is connected in series with the third transistor 22, and the third transistor 22 is connected. The gate is coupled to the gate of the fourth transistor 24, wherein the series connection of the first transistor 12 and the second transistor 14 is coupled to the gates of the third transistor 22 and the fourth transistor 24. The series connection ends of the third transistor 22 and the fourth transistor 24 are coupled to the gates of the first transistor 12 and the second transistor 14 to form an inverter pair. In addition, the first inverter 10 formed by the first transistor 12 and the second transistor 14 and the second inverter 20 formed by the third transistor 22 and the fourth transistor 24 are only one of the present inventions. A preferred embodiment, but not limited to the first inverter 10 and the second inverter 20 formed by the above circuit, may be formed by any other form of inverter circuit.

The equalizer 30 is coupled between the first inverter 10 and the second inverter 20 to control the potential between the first inverter 10 and the second inverter 20, that is, when the equalizer 30 receives a control signal, The potential between the first inverter 10 and the second inverter 20 is the same to enter a meta-stable state, wherein the equalizer 30 is a switching circuit, such as a field effect transistor (Field Effect Transistor) , FET), as shown in the third figure, the equalizer 30 is used as a switch. When receiving the control signal (EQ), the equalizer 30 is turned on to make the voltage of the N1 point and the N2 point of the inverter pair. The same level.

The access ports 40, 42 and 44 are coupled to the first inverter 10 and the second inverter, and are respectively coupled to the bit line BL_1, the bit line BL_2 and the bit line BL_n, and the word line WL_1, and the word. The source line WL_2 and the word line WL_n are used as a read/write shared 埠, a read 埠 or a write 埠, so that the data in the inverter pair of the memory unit can be accessed, but if there is data to be written When the device is stored, it is only for one file to be written, and the other ports must be off (not for reading and writing). Thus, when the operation of writing data into the memory unit is performed, in the initial stage, the equalizer 30 will bring the memory unit into a quasi-stable state; when the memory has entered the quasi-stable state, the equalizer 30 is turned off, and the access is turned on. The memory unit will sense the signal on the bit line BL_1 for writing data; at the same time, the voltage of the virtual ground V_Gnd will also increase, causing the threshold voltage of the first inverter 10 and the second inverter 20 to rise. Therefore, the present invention can perform data writing only by using half of the power supply Vdd on the bit line BL_1, thereby reducing the power consumption required when the data is written into the memory unit of the storage device. In addition, the access ports 40, 42, 44 described above are a switching circuit and are field effect transistors.

Referring to FIG. 5, it is a circuit diagram of a memory unit of a storage device according to a preferred embodiment of the present invention. As shown in the figure, when the data is written, if the voltage of the virtual ground terminal V_Gnd is zero potential, And when the equalizer 30 is turned on, a large current will flow through the first inverter 10 and the second inverter 20, thereby increasing power consumption. Therefore, the single-ended multi-turn storage device of the present invention provides a blocking unit 50 between the virtual ground V_Gnd and the ground in the memory cells of each column to avoid large current generation and reduce power consumption. The blocking unit 50 includes a transistor 51, 52, a first logic gate 53, and a second logic gate 54. The transistor 51 and the transistor 52 are connected to each other and coupled between the virtual ground V_Gnd and the ground. The output of the first logic gate 53 is coupled to the gate of the transistor 52, and the output of the second logic gate 55 is coupled to the output. The gate of the crystal 51, and the first logic gate 53 and the second logic gate 54 respectively receive a blocking signal (PG) and an inverted blocking signal, and the blocking unit 50 is turned off when the storage device performs writing to block the virtual ground and The connection of the grounding ends allows the virtual ground to float to avoid large currents. In addition, the structure of the foregoing blocking unit 50 is only a preferred embodiment of the present embodiment, but is not limited to the blocking unit 50 formed by the above circuit, and may be other structures, such as a P-type gold-oxygen half field effect transistor power gate ( PMOS power gate), an N-type MOS power gate or a data retention power gate.

Please refer to a sixth diagram, which is a timing diagram of data written in a storage device according to a preferred embodiment of the present invention. As shown in the figure, when the storage device is to write data, the control signal (EQ) and the blocking signal (PG) will be converted to a high level, and the equalizer 30 is turned on when the control signal (EQ) transitions to the high level. And destroying the data stored in the memory unit, the virtual ground V_Gnd will change from the zero potential of the ground to the floating potential. At this time, the N1 and N2 points between the first inverter 10 and the second inverter 20 are accurate. The bits are the same. At this time, when the equalizer 30 is turned off, the memory unit of the storage device enters a quasi-stable state, and one of the access ports 40, 42, 44 will be turned on, and the signal on the bit line is sensed, after which The word line will be set to a high level and the blocking unit 50 will be turned on to complete the writing operation.

In summary, the single-ended multi-turn storage device of the present invention enters a quasi-stable state by an equalizer and a virtual ground to control the inverter pair formed by the first inverter and the second inverter. After the status, the access is accessed by multiple accesses. In this way, the power consumption required for writing data to the storage device is reduced, and the speed of writing data to the storage device is accelerated. Further, since the present invention is a single-ended storage device, the area of the storage device can be reduced and the storage device can be reduced. The winding area of the Yuan line.

The invention is a novel, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10’. . . First inverter

20’. . . Second inverter

30’. . . Access code

10. . . Inverter

20. . . Second inverter

30‧‧‧Equalizer

40‧‧‧ access point

42‧‧‧Access rights

44‧‧‧ access point

50‧‧‧Block unit

51‧‧‧Optoelectronics

52‧‧‧Optoelectronics

53‧‧‧First Logic Gate

54‧‧‧Second logic gate

Vdd‧‧‧ power supply

V_Gnd‧‧‧virtual ground

1 is a circuit diagram of a storage device of a prior art; FIG. 2 is a circuit diagram of another conventional storage device; and FIG. 3 is a block diagram of a storage device according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a circuit diagram of a memory device of a memory device according to a preferred embodiment of the present invention; and FIG. 6 is a preferred embodiment of the present invention A timing diagram of the data written by the storage device.

10. . . First inverter

20. . . Second inverter

30. . . Equalizer

40. . . Access code

42. . . Access code

44. . . Access code

Claims (10)

A storage device for a single-ended multi-turn, comprising a plurality of memory cells, the memory unit comprising: a first inverter having a first input end and a first output end coupled to a power source and a virtual ground, the virtual ground is a floating voltage; a second inverter has a second input end and a second output end, the second input end is coupled to the first output end, the second output end The second inverter is coupled to the power source and the virtual ground; an equalizer is coupled to the first inverter and the second inverter to control the first inverter And a potential of the second inverter; a plurality of access ports coupled to the first inverter and the second inverter, and coupled to a bit line and a word line; and a blocking unit, including a plurality of logic gates coupled between the virtual ground and a ground, and the input ends of the logic gates are coupled to a blocking signal, and the blocking unit receives signals and blocks the memory unit when the data is written The virtual ground is coupled to the ground to float the virtual ground. The storage device of claim 1, wherein the first inverter comprises: a first transistor coupled to the power source at one end; and a second transistor coupled to the virtual body at one end thereof Grounded, the other end is connected in series with the other end of the first transistor, and the gate of the first transistor is coupled to the gate of the second transistor; the second inverter comprises: a third a crystal, one end of which is coupled to the power source; and a fourth transistor, one end of which is coupled to the virtual ground, the other end of which is coupled in series with the third transistor, and the gate of the third transistor and the fourth The gate of the transistor is coupled to the gate of the second transistor and the gate of the fourth transistor, the third transistor The serial end of the fourth transistor is coupled to the a gate of the first transistor and the second transistor. The storage device of claim 1, wherein the equalizer receives a control signal such that the first inverter and the second inverter have the same potential to enter a quasi-stable state (meta-stable) State). The storage device of claim 1, wherein the blocking unit further comprises: a second transistor coupled between the virtual ground and the ground and connected to each other; a first logic gate coupled a gate of one of the two transistors; and a second logic gate coupled to the gate of another transistor of the second transistor, the input of one of the first logic gate and the input of the second logic gate The end is coupled to the blocking signal. A storage device for a single-ended multi-turn, comprising a plurality of memory cells, the memory unit comprising: a first inverter having a first input end and a first output end coupled to a power source and a virtual ground, the virtual ground is a floating voltage; a second inverter has a second input end and a second output end, the second input end is coupled to the first output end, the second output end The second inverter is coupled to the power source and the virtual ground; an equalizer is coupled to the first inverter and the second inverter to control the first inverter And a potential of the second inverter; a plurality of access ports coupled to the first inverter and the second inverter, and coupled to a bit line and a word line; and a blocking unit, including a transistor and a logic gate coupled between the virtual ground and a ground. The output of the logic gate is coupled to the transistor to receive a signal when the memory unit is written. The virtual ground is blocked from the ground, and the virtual ground is floated. The storage device of claim 1, wherein the blocking unit is a P-type MOS power gate and an N-type MOS power gate (NMOS power gate). ) or a data retention power gate Gate). The storage device of claim 1, wherein the equalizer is a switching circuit. The storage device of claim 1, wherein the access ports are a switch circuit. The storage device of claim 1, wherein the access ports are a read/write shared port, a read port, or a write port. The storage device of claim 1, wherein the storage device is a State Random Access Memory (SRAM), a Register File, a Buffer, A content Contextable Memory (CAM).