TWI469266B - Worm memory device and process of manufacturing the same - Google Patents
Worm memory device and process of manufacturing the same Download PDFInfo
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Description
本發明係有關於一種單次寫入多次讀取（Write-Once-Read-Many-times, WORM）記憶體及其製造方法，尤指涉及一種在Al2
O3
中藉由沉積一由Al2
O3
雙層夾持之矽/鍺（Si/Ge），與隨後之熱退火形成SiGe奈米晶體結構（SiGe nanocrystals），特別係指可通過Si/Ge雙層各別之厚度調整，使其成為一種可靠之方式以在一電介質中實現理想之SiGe奈米晶體構成嵌入在Al2
O3
之WORM記憶體裝置。
The present invention relates to a Write-Once-Read-Many-times (WORM) memory and a method of fabricating the same, and more particularly to a method for depositing Al in Al 2 O 3 2 O 3 double-layered 矽/锗 (Si/Ge), followed by thermal annealing to form SiGe nanocrystals, especially the thickness adjustment of the Si/Ge double layer It is a reliable way to implement an ideal SiGe nanocrystal in a dielectric to form a WORM memory device embedded in Al 2 O 3 .
單次寫入多次讀取（Write-Once-Read-Many-times, WORM）記憶體係一種允許訊息被寫入一次，但多次讀取之資料儲存媒體類型。這類型之記憶體廣泛地應用於其訊息不能被篡改或銷毀之應用程式，如電子投票，事故記錄器，不得編輯之資料庫，以及無線射頻識別（Radio Frequency Identification, RFID）系統之標籤。由於應用程式之蓬勃發展，各種材料已在文獻中被提議形成記憶體之主動層，且有機或高分子材料最近已引起強烈興趣，因為這些材料能夠使其以符合成本效益之方式實現大面積之WORM記憶體陣列。然而這些顯示出巨大潛力之材料，現階段與目前需要工藝兼容之無機材料之超大型積體電路（Ultra-Large Scale Integration, ULSI）技術不相容。基於這種需求，鋁奈米晶體嵌入在氮化鋁（AlN）或氧化鋁（Al2
O3
），已有報告顯示有利於實現以奈米晶體為基礎之WORM記憶體。然而，該WORM裝置亦在報告中指出經由富鋁Al2
O3
形成之奈米晶體係隨機分佈在Al2
O3
，然而該Al2
O3
具有高度缺陷。因為電荷可能被儲存在奈米晶體及/或在Si基板附近有缺陷之Al2
O3
中，被儲存之電荷受制於高溫下之損失，並可能導致持久性下降。此外，因為Al之低熔點，Al奈米晶體之密度與形狀能被高溫熱處理改變，通常使用在ULSI技術，因此裝置之性能將可能受到影響。
事實上，由於較小之能隙，以鍺（Ge）之奈米晶體為基礎之快閃記憶體已被證明相較以矽之奈米晶體為基礎之快閃記憶體具有理想之持久性特徵。雖然Ge奈米晶體容易地在一氧化矽（SiO2
）基材中形成，然欲成核在高介電常數（high-κ）介電材料，必須減少操作電壓卻係極其困難，除非使用一特殊製程，如脈衝雷射沉積（Pulsed Laser Deposition, PLD）。故，ㄧ般習用者係無法符合使用者於實際使用時之所需。
Write-Once-Read-Many-times (WORM) memory system A type of data storage medium that allows messages to be written once but read multiple times. This type of memory is widely used in applications where messages cannot be tampered with or destroyed, such as electronic voting, accident recorders, non-editable databases, and tags for Radio Frequency Identification (RFID) systems. Due to the booming applications, various materials have been proposed in the literature to form active layers of memory, and organic or polymeric materials have recently attracted strong interest because these materials enable them to achieve large areas in a cost-effective manner. WORM memory array. However, these materials, which show great potential, are currently incompatible with Ultra-Large Scale Integration (ULSI) technology, which currently requires process-compatible inorganic materials. Based on this demand, aluminum nanocrystals are embedded in aluminum nitride (AlN) or aluminum oxide (Al 2 O 3 ), and it has been reported to be advantageous for realizing nanocrystal-based WORM memory. However, the WORM device also indicates in the report that the nanocrystalline system formed via the aluminum-rich Al 2 O 3 is randomly distributed in Al 2 O 3 , however, the Al 2 O 3 has a high defect. Since the charge may be stored in the nanocrystals and/or in the Al 2 O 3 which is defective near the Si substrate, the stored charge is subject to loss at high temperatures and may cause a decrease in durability. In addition, because of the low melting point of Al, the density and shape of Al nanocrystals can be altered by high temperature heat treatment, which is commonly used in ULSI technology, so the performance of the device may be affected.
In fact, due to the smaller energy gap, flash memory based on germanium (Ge) nanocrystals has been shown to have ideal persistence characteristics compared to flash memory based on nanocrystals. . Although Ge nanocrystals are easily formed in a cerium oxide (SiO 2 ) substrate, it is extremely difficult to reduce the operating voltage in order to nucleate a high-k dielectric material, unless one is used. Special processes such as Pulsed Laser Deposition (PLD). Therefore, the user-like users cannot meet the needs of the user in actual use.
本發明之主要目的係在於，克服習知技藝所遭遇之上述問題並提供一種藉由沉積一由Al2
O3
雙層夾持之Si/Ge，與隨後之熱退火形成SiGe奈米晶體結構，其可通過Si/Ge雙層各別之厚度調整，使其成為一種可靠之方式以在一電介質中實現理想之SiGe奈米晶體構成嵌入在Al2
O3
之WORM記憶體裝置。
本發明之次要目的係在於，提供一種在負脈衝下可通過電洞編程儲存在奈米晶體中，電流位準可經由應用-10V/1s脈衝增加104
倍，即使是-5V/1μs脈衝，仍可獲得足夠大之電流比來區分邏輯狀態之WORM記憶體裝置。
本發明之另一目的係在於，提供一種透過使用SiGe奈米晶體嵌入雙層Al2
O3
作為WORM記憶體之主動層而具有高熱穩定性，可達到低操作電壓、快速寫入、理想之讀取耐久性與高溫之持久性，並可在高溫下有效讀取資料之高可靠度之記憶性能之WORM記憶體裝置。
本發明之再一目的係在於，提供一種讀取壽命能力可達105
次與超過100年之優秀持久性，可適用於高性能歸檔儲存應用之WORM記憶體裝置。
為達以上之目的，本發明係一種單次寫入多次讀取記憶體及其製造方法，係至少包含下列步驟：（Ａ）係提供一基板，作為下電極；（Ｂ）於該基板上沉積一第一氧化層；（Ｃ）於該第一氧化層上沉積至少一以上之Si/Ge層；（Ｄ）於該至少一以上之Si/Ge層上沉積一第二氧化層；（Ｅ）進行一快速熱退火（Rapid Thermal Annealing, RTA）製程，以氮氣（N2
）稀釋氧氣（O2
），於600～800°C下反應80～100秒（s）後使該Si/Ge層形成一嵌入在該第一、二氧化層中之SiGe奈米晶體結構；以及（Ｆ）於該第二氧化層上沉積一導電層作為上電極。
於本發明一實施例中，更包括在該導電層上沉積一保護層。
於本發明一實施例中，該基板係為矽基板。
於本發明一實施例中，該第一、二氧化層係為高介電常數（high-k）無結晶材料，並可選自三氧化二鋁（Al2
O3
）。
於本發明一實施例中，該第一氧化層之厚度係介於5.0～7.4奈米（nm）。
於本發明一實施例中，該Si/Ge層中每一Si層與Ge層各自之厚度係介於2.1～3.1nm。
於本發明一實施例中，該Si/Ge層係由一層Si與一層Ge為一個循環，連續沉積至少一個循環以上。
於本發明一實施例中，該Si/Ge層係由一層Ge與一層Si為一個循環，連續沉積至少一個循環以上。
於本發明一實施例中，該第二氧化層之厚度係介於4.2～6.2nm。
於本發明一實施例中，該矽鍺奈米晶體結構嵌入Al2
O3
之方式係由連續沉積在該基板之Al2
O3
/Si/Ge/Al2
O3
之疊層結構與一隨後之快速熱退火製程所形成。
於本發明一實施例中，該Al2
O3
/Si/Ge/Al2
O3
之疊層結構係由電子束蒸鍍依次沉積。
於本發明一實施例中，該導電層係可選自鋁（Al）。
於本發明一實施例中，該矽鍺奈米晶體結構係由該Si/Ge層中Si提供額外之成核點並結合Ge調整能隙。
The main object of the present invention is to overcome the above problems encountered in the prior art and to provide a SiGe nanocrystal structure by depositing a Si/Ge sandwiched by a double layer of Al 2 O 3 and subsequently thermally annealing. It can be adjusted by the thickness of the Si/Ge double layer, making it a reliable way to realize the ideal SiGe nanocrystal in a dielectric to form a WORM memory device embedded in Al 2 O 3 .
A secondary object of the present invention is to provide a nano-crystal that can be stored in a nanocrystal under a negative pulse, and the current level can be increased by a factor of 10 4 , or even a -5 V/1 μs pulse, by applying a -10 V/1 s pulse. A WORM memory device with a sufficiently large current ratio to distinguish the logic state is still available.
Another object of the present invention is to provide a high thermal stability by embedding a double layer of Al 2 O 3 as an active layer of a WORM memory by using a SiGe nanocrystal, which can achieve low operating voltage, fast writing, and ideal reading. A WORM memory device that takes durability and high temperature durability and can efficiently read data with high reliability and memory performance at high temperatures.
A further object of the present invention is based is to provide a method of reading the life and capacity of up to 105 times more than 100 years of outstanding persistence, applicable to WORM archival storage applications of high-performance memory device.
For the above purposes, the present invention is a single-write multiple read memory and a method of fabricating the same, comprising at least the following steps: (A) providing a substrate as a lower electrode; (B) on the substrate Depositing a first oxide layer; (C) depositing at least one Si/Ge layer on the first oxide layer; (D) depositing a second oxide layer on the at least one Si/Ge layer; Performing a Rapid Thermal Annealing (RTA) process, diluting oxygen (O 2 ) with nitrogen (N 2 ), and reacting at 600-800 ° C for 80-100 seconds (s) to make the Si/Ge layer Forming a SiGe nanocrystal structure embedded in the first and second oxide layers; and (F) depositing a conductive layer on the second oxide layer as an upper electrode.
In an embodiment of the invention, the method further includes depositing a protective layer on the conductive layer.
In an embodiment of the invention, the substrate is a germanium substrate.
In an embodiment of the invention, the first and second oxide layers are high-k non-crystalline materials and may be selected from the group consisting of aluminum oxide (Al 2 O 3 ).
In an embodiment of the invention, the first oxide layer has a thickness of 5.0 to 7.4 nanometers (nm).
In an embodiment of the invention, each of the Si layer and the Ge layer in the Si/Ge layer has a thickness of 2.1 to 3.1 nm.
In an embodiment of the invention, the Si/Ge layer is formed by a layer of Si and a layer of Ge as a cycle, continuously deposited for at least one cycle or more.
In an embodiment of the invention, the Si/Ge layer is formed by a layer of Ge and a layer of Si in a cycle, continuously deposited for at least one cycle or more.
In an embodiment of the invention, the thickness of the second oxide layer is between 4.2 and 6.2 nm.
In an embodiment of the invention, the nanocrystalline crystal structure is embedded in Al 2 O 3 by a stacked structure of Al 2 O 3 /Si/Ge/Al 2 O 3 continuously deposited on the substrate and a subsequent The rapid thermal annealing process is formed.
In an embodiment of the invention, the stacked structure of Al 2 O 3 /Si/Ge/Al 2 O 3 is sequentially deposited by electron beam evaporation.
In an embodiment of the invention, the conductive layer may be selected from aluminum (Al).
In an embodiment of the invention, the nanocrystalline crystal structure provides additional nucleation sites and a Ge adjustment energy gap in the Si/Ge layer.
請參閱『第１圖』所示，係本發明WORM記憶體裝置之製造流程示意圖。如圖所示：本發明係一種單次寫入多次讀取（Write-Once-Read-Many-times, WORM）記憶體及其製造方法，係至少包含下列步驟：
（Ａ）係提供一矽基板（Si Substrate）１０，作為下電極；
（Ｂ）於該Si基板１０上沉積一第一氧化層１１；
（Ｃ）於該第一氧化層１１上沉積至少一以上之矽/鍺（Si/Ge）層１２；
（Ｄ）於該至少一以上之Si/Ge層１２上沉積一第二氧化層１３；
（Ｅ）進行一快速熱退火（Rapid Thermal Annealing, RTA）製程，以氮氣（N2
）稀釋氧氣（O2
），於600～800°C下反應80～100秒（s），由該Si/Ge層１２中Si層１２１提供額外之成核點並結合Ge層１２２調整能隙，使該Si/Ge層１２形成一嵌入在該第一、二氧化層１１、１３中之矽鍺奈米晶體結構（SiGe nanocrystals）１４；以及
（Ｆ）於該第二氧化層１３上沉積一導電層１５作為上電極，以形成WORM記憶體裝置。其中，該記憶體裝置係可進一步包括在該導電層１５上再沉積一保護層１６。
上述所提之第一、二氧化層１１、１３係為高介電常數（high-k）無結晶材料，並可選自三氧化二鋁（Al2
O3
），其中該第一氧化層１１之厚度係介於5.0～7.4奈米（nm），而該第二氧化層１３之厚度係介於4.2～6.2nm。
上述所提之Si/Ge層１２係由一層Si層１２１與一層Ge層１２２為一個循環（如第１圖所示），亦或由一層Ge層與一層Si層為一個循環，連續沉積至少一個循環以上，且該Si/Ge層１２中每一Si層１２１與Ge層１２２各自之厚度係介於2.1～3.1nm。
當運用時，本發明係使用P型Si晶圓作為原料。於一較佳實施例中，藉由電子束蒸鍍依次沉積在Si基板１０之Al2
O3
（6.2 nm）１１/Si（2.6 nm）/Ge（2.6 nm）１２/Al2
O3
（5.2 nm）１３之疊層結構，然後由後續之快速熱退火製程，在N2
稀釋氧氣環境下，於700°C進行90秒（s）（1.0% O2
per volume）後形成嵌入在雙層Al2
O3
１１、１３中之SiGe奈米晶體１４。最後，沉積Al導電層１５作為上電極，以形成WORM記憶體裝置。此外，於另一實施例中，具單一17.0 nm之Al2
O3
薄膜裝置也可製備為調查SiGe奈米晶體對裝置性能之影響。
本發明所提之WORM記憶體裝置，除了使用250μm x 250μm之面積調查電特性之外，透射電子顯微鏡（TEM）、電子繞射圖、以及能量散佈分析儀（EDS）也分別使用來確認奈米晶體之形成與分析奈米晶體之組成。
請參閱『第２圖及第３圖』所示，係分別為本發明之Si/Ge奈米晶體嵌入在Al2
O3
之橫截面TEM圖、及本發明WORM記憶體裝置之能帶示意圖。如圖所示：由圖中顯示Si/Ge雙層退火後之樣本，可以觀察到表面之奈米晶體嵌入在Al2
O3
，可以推斷出奈米晶體之形成係傾向在結晶過程中之退火製程下混合矽與鍺，且在第２圖之插圖中顯示之奈米晶體之位置及奈米晶體附近上/下雙層Al2
O3
之EDS分析結果可知，Si與Ge之訊號為奈米晶體，可說明SiGe之組成。此外，在奈米晶體附近之Al2
O3
發現可忽略不計之Si與Ge訊號，該現像可以說明藉由Al2
O3
一個良好之擴散阻擋層，可從而防止Si與Ge原子向外擴散。並且，在第２圖中之插圖所示之電子衍射圖樣可知，確定係奈米晶體之結晶結構。除非另有提及，否則下面之說明中對於電氣性能僅限於嵌入式奈米晶體之裝置，由該裝置之能帶圖（如第３圖所示）可說明能帶結構如何影響下列之電氣特性。
請進一步參閱『第４圖』所示，係本發明之WORM記憶體裝置在1 MHz後應用不同之脈衝條件下之正規化CV特性示意圖。如圖所示：當測量時，中央曲線表示裝置沒有應用脈衝之初始狀態，當曲線在正或負脈衝之應用下將分別向右或向左移。其中曲線移位可歸因於電子與電洞之網絡儲存影響平帶電壓（VFB
），且由負脈衝引起之預存在SiGe奈米晶體中之移動式負電荷，該平帶電壓VFB
移位就更為明顯，此推斷可經由插圖中顯示在具有SiGe奈米晶體與不具有SiGe奈米晶體之裝置間之電容-電壓（CV）曲線比較其初始狀態而證明。在插圖中，具有SiGe奈米晶體之裝置以更多正之平帶電壓VFB
指示當Si與Ge混合時其可能會形成存在預存之負電荷。
事實上，氧原子之摻入以致氧相關缺陷之形態，如氧間隙（Oi
, O2i
）與氧空缺複合物（VO, VO2
）在Si與Ge中之形成已被揭露。在晶體矽中，該氧空缺複合物已知存在兩種電荷狀態，包含單負與中立；此外，該氧空缺複合物在晶體鍺中則有三種電荷狀態，包含雙負、單負與中立。本發明通過對奈米晶體使用EDS分析，由發出一個相對較弱之氧訊號之結果可驗證，在熱退火過程中係含有少量氧原子從Al2
O3
擴散到SiGe奈米晶體。由於氧原子被納入SiGe奈米晶體，形成氧空缺複合物之可能性係極高，因為複合物可帶負電荷之傾向，在插圖中可觀察到具有SiGe奈米晶體之裝置之一更多正之平帶電壓VFB
。如第２圖所示，在施加一負脈衝下，所述移動式負電荷從奈米晶體被移動至Si時，電洞（多數載流子）從Si基板被注入到奈米晶體，兩者係通過底部Al2
O3
穿隧。由於使電位障之厚度變薄視作對電洞之穿隧，其會導致良好之電洞穿隧，所以預存之移動式負電荷將可有效地改善能帶圖；因此，電子與電洞之穿隧有助於大平帶電壓VFB
移向負方向。另一方面，由於預存之移動式負電荷在奈米晶體將有效地提高局部之導帶，並增加電位障之厚度視作對電子穿隧，電子（少數載流子）從Si注入將變得比較不利於正偏壓下之穿隧，並因而導致一較小之平帶電壓VFB
移位。值得一提的是，電子與電洞係穿隧通過Si/Al2
O3
而非Al/Al2
O3
介面。這主要係由於N2
退火稀釋氧氣增強上層Al2
O3
之介電完整性，因此使得穿隧不易發生在Al/Al2
O3
介面。此外，應注意的是，對於沒有SiGe奈米晶體之裝置應用正或負之脈衝後，其CV曲線並未發現任何移位，這說明電荷確實儲存在SiGe奈米晶體而非Al2
O3
（圖未顯示）。
請進一步參閱『第５Ａ圖及第５Ｂ圖』所示，係分別為本發明之WORM記憶體裝置在各種脈衝條件下從0到+4 V之IV特性示意圖、及本發明之WORM記憶體裝置在各種脈衝條件下從0到-4 V之IV特性示意圖。如圖所示：由第５Ａ圖顯示本裝置在各種脈衝條件下，測量從0到+4 V之電流-電壓（IV）特性。當測量時，電流包含在這測量條件之下從 Si（少數載流子）注入之電子，並以對於應用+10V/1s電壓之裝置，其電流離初始狀態差異最小。如第４圖所述，如果預存之負電荷與注入之電子儲存在裝置之奈米晶體中，當隨一正脈衝之應用，電子之電位障厚度增加，其將抑制電子從Si注入，使電流幾乎不變或甚至略低於最初裝置狀態。相反地，對於應用-10V/1s電壓之裝置，與初始狀態相較，其電流在+1.5 V之讀取電壓下明顯地增加104
倍，具強大之讀取耐久性與良好之持久性。增強之電流位準可以被認為係編程狀態與主要來自電位障之有效變薄引起經由網絡電洞儲存在奈米晶體，通過降低編程電壓與脈衝寬度到-5V/1μs，電流仍然可以取得增強36倍，且該電流變化係足夠大以定義邏輯“1”與“0”作為記憶體器之應用，證實本裝置可低功率操作。
由第５Ｂ圖顯示本裝置在各種脈衝條件下，測量從0到-4 V之IV特性，藉與第５Ａ圖作比較。由於該測定條件下之電流主要係通過從Al電極注入之電子（多數載流子），因此，該電流位準對於裝置具有不同應用脈衝係遠高於這些從0到+4V之測量。然而，該裝置在電流應用正脈衝與負脈衝之差異不如前述測量從0到+4V之明顯。這種現象可以解釋為：該裝置之作用類似於一個肖特基二極體，因此，當它係正偏壓時，具有更大之電流在0到-4 V掃描。然而，當在0到+4 V之方向，它係反偏壓且電流較低。由於電荷在SiGe奈米晶體中，這種反偏壓電流係對障高之變化更加靈敏。本發明結果還表明WORM記憶體裝置可以只正確讀取在資料儲存以後之正電壓。
對於WORM記憶體裝置，高讀取耐久性係一個先決條件，其結果顯示於第６圖之插圖。在觀察達10個讀取週期下，其編程狀態與初始狀態間之電流比之損失很小。
請進一步參閱『第６圖』所示，係本發明之WORM記憶體裝置在室溫與100°C下測得之持久性能示意圖。如圖所示：不同於傳統描述以Al奈米晶體為基礎之WORM記憶體裝置在100°C下降低持久性，在本發明中，104
秒後即可達到穩定電流。良好之持久性可歸因於以下原因：(a)電荷儲存在SiGe奈米晶體並經由Al2
O3
而與Si基板分離；由於該Al2
O3
具有比富鋁Al2
O3
相對較好之介電完整性，使其能更有效地防止電荷損失。(b)SiGe奈米晶體與Al2
O3
之間之大價帶之補償更容易在量子井中維持儲存電洞。藉此，通過外推法，兩個狀態間之電流比基本保持不變超過100年，顯示本發明提出之WORM記憶體裝置係非常適合長時間之資料儲存，透過使用SiGe奈米晶體嵌入Al2
O3
作為WORM記憶體之主動層，只要經由微調SiGe奈米晶體之組成，即可很容易地通過調節Si層與Ge層各自之厚度而將裝置性能作進一步地優化，而提升裝置之高熱穩定性，可達到低操作電壓、快速寫入、理想之讀取壽命能力可達105
次與超過100年之優秀持久性，並可在高溫下有效讀取資料之高可靠度之記憶性能。
本發明係提供一種由SiGe奈米晶體構成嵌入在Al2
O3
之WORM記憶體裝置，由於Si可以提供額外之成核點且其能隙可以通過結合Ge而調整，使高密度之SiGe奈米晶體可以形成在一high-k介質中。該裝置在一負脈衝下可通過電洞編程儲存在奈米晶體中，電流位準可經由應用-10V/1s脈衝增加104
倍，即使是-5V/1μs脈衝，仍可獲得足夠大之電流比來區分邏輯狀態，具有良好之記憶特性。由於Al2
O3
之高完整性與大價帶可在奈米晶體與Al2
O3
之間補償，使該裝置操作電壓低、寫入快，可在高溫下有效讀取資料，進而提供了理想之讀取耐久性與高溫之持久性，使其高溫運作時之可靠度能以優異之耐高溫表現確保應用程式可靠運作，為高性能WORM記憶體之應用顯示出巨大之潛力。
綜上所述，本發明係一種單次寫入多次讀取記憶體及其製造方法，可有效改善習用之種種缺點，使之透過使用SiGe奈米晶體嵌入雙層Al2
O3
作為WORM記憶體之主動層而具有高熱穩定性，可達到低操作電壓、快速寫入、理想之讀取耐久性與高溫之持久性，並可在高溫下有效讀取資料之高可靠度之記憶性能，進而使本發明之産生能更進步、更實用、更符合使用者之所須，確已符合發明專利申請之要件，爰依法提出專利申請。
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍；故，凡依本發明申請專利範圍及發明說明書內容所作之簡單的等效變化與修飾，皆應仍屬本發明專利涵蓋之範圍內。
Please refer to FIG. 1 for a schematic diagram of the manufacturing process of the WORM memory device of the present invention. As shown in the figure: The present invention is a Write-Once-Read-Many-times (WORM) memory and a method for fabricating the same, and includes at least the following steps:
(A) provides a substrate (Si Substrate) 10 as a lower electrode;
(B) depositing a first oxide layer 11 on the Si substrate 10;
(C) depositing at least one layer of germanium / germanium (Si / Ge) layer 12 on the first oxide layer 11;
(D) depositing a second oxide layer 13 on the at least one Si/Ge layer 12;
(E) performing a Rapid Thermal Annealing (RTA) process, diluting oxygen (O 2 ) with nitrogen (N 2 ), and reacting at 600 to 800 ° C for 80 to 100 seconds (s) from the Si/ The Si layer 121 in the Ge layer 12 provides an additional nucleation point and adjusts the energy gap in combination with the Ge layer 122, so that the Si/Ge layer 12 forms a nanocrystal embedded in the first and second oxide layers 11, 13. Structure (SiGe nanocrystals) 14; and (F) depositing a conductive layer 15 on the second oxide layer 13 as an upper electrode to form a WORM memory device. The memory device can further include a protective layer 16 deposited on the conductive layer 15.
The first and second oxide layers 11, 13 mentioned above are high-k non-crystalline materials and may be selected from aluminum oxide (Al 2 O 3 ), wherein the first oxide layer 11 The thickness is between 5.0 and 7.4 nanometers (nm), and the thickness of the second oxide layer 13 is between 4.2 and 6.2 nm.
The above-mentioned Si/Ge layer 12 is composed of a layer of Si layer 121 and a layer of Ge layer 122 as a cycle (as shown in FIG. 1), or a layer of Ge layer and a layer of Si layer, and at least one layer is continuously deposited. Above the cycle, each of the Si layer 121 and the Ge layer 122 in the Si/Ge layer 12 has a thickness of 2.1 to 3.1 nm.
When used, the present invention uses a P-type Si wafer as a raw material. In a preferred embodiment, Al 2 O 3 (6.2 nm) 11/Si (2.6 nm) / Ge (2.6 nm) 12 / Al 2 O 3 (5.2) deposited on the Si substrate 10 by electron beam evaporation. The stack structure of nm) 13 is then embedded in the double layer Al by a subsequent rapid thermal annealing process in an N 2 diluted oxygen atmosphere at 700 ° C for 90 seconds (s) (1.0% O 2 per volume). SiGe nanocrystal 14 in 2 O 3 11,13. Finally, an Al conductive layer 15 is deposited as an upper electrode to form a WORM memory device. In addition, in another embodiment, a single 17.0 nm Al 2 O 3 thin film device can also be prepared to investigate the effect of SiGe nanocrystals on device performance.
In the WORM memory device of the present invention, in addition to using an area of 250 μm x 250 μm to investigate electrical characteristics, a transmission electron microscope (TEM), an electron diffraction pattern, and an energy dispersive analyzer (EDS) are also used to confirm the nanometer, respectively. Formation of crystals and analysis of the composition of nanocrystals.
Please refer to FIG. 2 and FIG. 3, which are respectively a cross-sectional TEM image of the Si/Ge nanocrystal embedded in the Al 2 O 3 of the present invention, and an energy band diagram of the WORM memory device of the present invention. As shown in the figure: From the sample after Si/Ge double-layer annealing, it can be observed that the surface nanocrystals are embedded in Al 2 O 3 , and it can be inferred that the formation of nanocrystals tends to anneal during crystallization.矽 and 锗 are mixed under the process, and the position of the nanocrystal shown in the illustration in Fig. 2 and the EDS analysis result of the upper/lower double layer Al 2 O 3 near the nano crystal show that the signal of Si and Ge is nanometer. The crystal can explain the composition of SiGe. In addition, negligible Si and Ge signals were found in Al 2 O 3 near the crystal of the nanocrystal, which shows that a good diffusion barrier layer by Al 2 O 3 can prevent the Si and Ge atoms from diffusing outward. Further, it is understood from the electron diffraction pattern shown in the inset of Fig. 2 that the crystal structure of the crystal of the nanocrystal is determined. Unless otherwise mentioned, the following description of the electrical performance is limited to embedded nanocrystal devices, the band diagram of the device (as shown in Figure 3) can explain how the band structure affects the following electrical characteristics .
Please refer to FIG. 4 for further description of the normalized CV characteristics of the WORM memory device of the present invention applied under different pulse conditions after 1 MHz. As shown in the figure: When measuring, the central curve indicates that the device has no initial state of application of the pulse, and when the curve is applied to the positive or negative pulse, it will move to the right or left, respectively. The curve shift can be attributed to the network storage of electrons and holes affecting the flat band voltage (V FB ), and the negative negative charge is pre-existing in the mobile negative charge in the SiGe nanocrystal, and the flat band voltage V FB is shifted. The position is more pronounced, and this inference can be demonstrated by comparing the initial state of the capacitance-voltage (CV) curve between a device having a SiGe nanocrystal and a device having no SiGe nanocrystal. In the inset, the device with SiGe nanocrystals indicates that there is a pre-existing negative charge when Si is mixed with Ge with more positive flat band voltage V FB .
In fact, the formation of oxygen atoms in the form of oxygen-related defects such as oxygen gaps (O i , O 2i ) and oxygen vacancy complexes (VO, VO 2 ) in Si and Ge has been revealed. In crystal ruthenium, the oxygen vacancy complex is known to have two charge states, including single negative and neutral; in addition, the oxygen vacancy complex has three charge states in the crystal enthalpy, including double negative, single negative and neutral. The present invention verifies by using EDS analysis of nanocrystals by emitting a relatively weak oxygen signal which contains a small amount of oxygen atoms diffusing from Al 2 O 3 to SiGe nanocrystals during thermal annealing. Since oxygen atoms are incorporated into SiGe nanocrystals, the possibility of forming oxygen-vacuum complexes is extremely high. Because of the tendency of the complex to be negatively charged, one of the devices with SiGe nanocrystals can be observed in the inset. Flat band voltage V FB . As shown in FIG. 2, when a negative negative charge is applied from the nanocrystal to Si when a negative pulse is applied, a hole (majority carrier) is injected from the Si substrate into the nanocrystal, both of which are It is tunneled through the bottom Al 2 O 3 . Since thinning the thickness of the potential barrier is regarded as tunneling to the hole, which leads to good tunneling of the hole, the pre-stored mobile negative charge can effectively improve the energy band diagram; therefore, the electron and the hole are worn. The tunnel helps the large flat band voltage V FB to move to the negative direction. On the other hand, since the pre-stored mobile negative charge will effectively increase the local conduction band in the nanocrystal and increase the thickness of the potential barrier as electron tunneling, electrons (minority carriers) will become implanted from Si. It is less favorable for tunneling under positive bias and thus causes a smaller flat band voltage V FB to shift. It is worth mentioning that electrons and holes are tunneled through the Si/Al 2 O 3 rather than the Al/Al 2 O 3 interface. This is mainly due to the N 2 annealing dilution of oxygen to enhance the dielectric integrity of the upper layer of Al 2 O 3 , thus making tunneling less likely to occur in the Al/Al 2 O 3 interface. In addition, it should be noted that after applying a positive or negative pulse to a device without SiGe nanocrystals, no shift is found in the CV curve, indicating that the charge is indeed stored in SiGe nanocrystals rather than Al 2 O 3 ( The figure is not shown).
Please refer to FIG. 5A and FIG. 5B for a schematic diagram of the IV characteristics of the WORM memory device of the present invention from 0 to +4 V under various pulse conditions, and the WORM memory device of the present invention. Schematic diagram of IV characteristics from 0 to -4 V under various pulse conditions. As shown in the figure: Figure 5A shows the current-voltage (IV) characteristics of the device measured from 0 to +4 V under various pulse conditions. When measured, the current contains electrons injected from Si (minority carriers) under these measurement conditions, and the difference in current from the initial state is minimized for devices applying a voltage of +10 V/1 s. As shown in Fig. 4, if the pre-stored negative charge and the injected electrons are stored in the nanocrystal of the device, when applied with a positive pulse, the thickness of the potential barrier of the electron increases, which will suppress the injection of electrons from Si to make the current Almost unchanged or even slightly lower than the initial device state. Conversely, for devices using -10 V/1 s, the current is significantly increased by a factor of 10 4 at a read voltage of +1.5 V compared to the initial state, with strong read endurance and good durability. The enhanced current level can be thought of as the programmed state and the effective thinning from the potential barrier causes storage in the nanocrystal via the network hole. By reducing the programming voltage and pulse width to -5V/1μs, the current can still be enhanced. The current variation is large enough to define logic "1" and "0" as memory applications, confirming that the device can operate at low power.
Figure 5B shows the IV characteristics of the device from 0 to -4 V under various pulse conditions, as compared to Figure 5A. Since the current under the measurement conditions is mainly through the electrons injected from the Al electrode (majority carriers), the current level has a different application pulse system for the device than these measurements from 0 to +4V. However, the difference between the positive and negative pulses applied by the device at the current is not as pronounced as the previous measurement from 0 to +4V. This phenomenon can be explained by the fact that the device acts like a Schottky diode, so that when it is positively biased, it has a larger current sweep from 0 to -4 V. However, when in the direction of 0 to +4 V, it is reverse biased and the current is low. Since the charge is in the SiGe nanocrystal, this reverse bias current is more sensitive to changes in the barrier height. The results of the present invention also show that the WORM memory device can correctly read only the positive voltage after data storage.
For WORM memory devices, high read durability is a prerequisite and the results are shown in the inset of Figure 6. The loss of current between the programmed state and the initial state is small when observed for up to 10 read cycles.
Please refer to FIG. 6 for further illustration of the long-term performance measured by the WORM memory device of the present invention at room temperature and 100 ° C. As shown in the figure: unlike the conventional description of the WORM memory device based on Al nanocrystals, the durability is lowered at 100 ° C. In the present invention, a stable current can be achieved after 10 4 seconds. Good durability can be attributed to the following reasons: (a) The charge is stored in the SiGe nanocrystal and separated from the Si substrate via Al 2 O 3 ; since the Al 2 O 3 is relatively better than the aluminum-rich Al 2 O 3 Its dielectric integrity makes it more effective in preventing charge loss. (b) The compensation of the large valence band between the SiGe nanocrystal and the Al 2 O 3 makes it easier to maintain the storage hole in the quantum well. Therefore, by extrapolation, the current ratio between the two states remains substantially unchanged for more than 100 years, indicating that the WORM memory device proposed by the present invention is very suitable for long-term data storage by embedding Al 2 through SiGe nanocrystals. O 3 as the active layer of the WORM memory, as long as the composition of the SiGe nanocrystals is fine-tuned, the device performance can be easily optimized by adjusting the thickness of each of the Si layer and the Ge layer, and the device is highly thermally stable. sex, can achieve low operating voltage, fast writes, ideal for reading the life and capacity of up to 105 times more than 100 years of excellent durability, and can effectively read memory performance data of high reliability at high temperatures.
The present invention provides a WORM memory device embedded in Al 2 O 3 from SiGe nanocrystals, since Si can provide additional nucleation sites and its energy gap can be adjusted by combining Ge to make high density SiGe nanometers. The crystals can be formed in a high-k medium. The device can be stored under a negative pulse through holes programming nanocrystals, the current level can be increased 104-fold by application of -10V / 1s pulse, even -5V / 1μs pulses of current can still obtain a sufficiently large It distinguishes the logic state and has good memory characteristics. Due to the high integrity of Al 2 O 3 with a large valence band of the compensation may be between 2 O 3 nanocrystals with Al, so that the low operating voltage device, the write speed can be effectively read data at a high temperature, thereby providing a The ideal read durability and high temperature durability make it reliable for high temperature operation to ensure reliable operation of the application with excellent high temperature performance, showing great potential for high performance WORM memory applications.
In summary, the present invention is a single-write multiple read memory and a manufacturing method thereof, which can effectively improve various disadvantages of conventional use, and embed double-layer Al 2 O 3 as a WORM memory by using SiGe nano crystals. The active layer of the body has high thermal stability, can achieve low operating voltage, fast writing, ideal read durability and high temperature durability, and can effectively read the high reliability memory performance of the data at high temperature, and then The invention can be made more progressive, more practical, and more in line with the needs of the user. It has indeed met the requirements of the invention patent application, and has filed a patent application according to law.
However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the invention are modified. All should remain within the scope of the invention patent.
10．．．Si基板10. . . Si substrate
11．．．第一氧化層11. . . First oxide layer
12．．．Si/Ge層12. . . Si/Ge layer
13．．．第二氧化層13. . . Second oxide layer
14．．．矽鍺奈米晶體結構14. . .矽锗 nano crystal structure
15．．．導電層15. . . Conductive layer
16．．．保護層16. . . The protective layer
第１圖，係本發明WORM記憶體裝置之製造流程示意圖。
第２圖，係本發明之Si/Ge奈米晶體嵌入在Al2
O3
之橫截面TEM圖。
第３圖，係本發明WORM記憶體裝置之能帶示意圖。
第４圖，係本發明之WORM記憶體裝置在1 MHz後應用不同之脈衝條件下之正規化CV特性示意圖。
第５Ａ圖，係本發明之WORM記憶體裝置在各種脈衝條件下從0到+4 V之IV特性示意圖。
第５Ｂ圖，係本發明之WORM記憶體裝置在各種脈衝條件下從0到-4 V之IV特性示意圖。
第６圖，係本發明之WORM記憶體裝置在室溫與100°C下測得之持久性能示意圖。
Fig. 1 is a schematic view showing the manufacturing process of the WORM memory device of the present invention.
Fig. 2 is a cross-sectional TEM image of the Si/Ge nanocrystal of the present invention embedded in Al 2 O 3 .
Figure 3 is a schematic diagram of the energy band of the WORM memory device of the present invention.
Fig. 4 is a schematic diagram showing the normalized CV characteristics of the WORM memory device of the present invention applied under different pulse conditions after 1 MHz.
Figure 5A is a graphical representation of the IV characteristics of a WORM memory device of the present invention from 0 to +4 V under various pulse conditions.
Figure 5B is a graphical representation of the IV characteristics of the WORM memory device of the present invention from 0 to -4 V under various pulse conditions.
Figure 6 is a graph showing the long-lasting performance of the WORM memory device of the present invention measured at room temperature and 100 °C.
10．．．Si基板10. . . Si substrate
11．．．第一氧化層11. . . First oxide layer
12．．．Si/Ge層12. . . Si/Ge layer
121．．．Si層121. . . Si layer
122．．．Ge層122. . . Ge layer
13．．．第二氧化層13. . . Second oxide layer
14．．．矽鍺奈米晶體結構14. . .矽锗 nano crystal structure
15．．．導電層15. . . Conductive layer
16．．．保護層16. . . The protective layer
Claims (10)
（Ａ）係提供一基板，作為下電極；
（Ｂ）於該基板上沉積一第一氧化層；
（Ｃ）於該第一氧化層上沉積至少一以上之矽/鍺（Si/Ge）層；
（Ｄ）於該至少一以上之Si/Ge層上沉積一第二氧化層；
（Ｅ）進行一快速熱退火（Rapid Thermal Annealing, RTA）製程，以氮氣（N2 ）稀釋氧氣（O2 ），於600～800°C下反應80～100秒（s）後使該Si/Ge層形成一嵌入在該第一、二氧化層中之矽鍺奈米晶體結構（SiGe nanocrystals）；以及
（Ｆ）於該第二氧化層上沉積一導電層作為上電極。A method for manufacturing a single write multiple read memory includes at least the following steps:
(A) providing a substrate as a lower electrode;
(B) depositing a first oxide layer on the substrate;
(C) depositing at least one layer of germanium/iridium (Si/Ge) on the first oxide layer;
(D) depositing a second oxide layer on the at least one Si/Ge layer;
(E) performing a Rapid Thermal Annealing (RTA) process, diluting oxygen (O 2 ) with nitrogen (N 2 ), and reacting at 600-800 ° C for 80-100 seconds (s) to make the Si/ The Ge layer forms a SiGe nanocrystals embedded in the first and second oxide layers; and (F) deposits a conductive layer on the second oxide layer as an upper electrode.
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| US20070037095A1 (en) * | 2005-07-28 | 2007-02-15 | Noboru Sasa | Write-once-read-many optical disk having low-to-high recording property accommodating short wavelength recording |
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| TW201426911A (en) | 2014-07-01 |
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