TWI469219B - A method for reducing a roughness of a surface of a metal thin film - Google Patents

Description

Method for reducing surface roughness of metal film

The invention is a method for reducing the surface roughness of a metal film, thereby improving the reliability of the component.

The multilayer interconnection of the core of the integrated circuit component is usually formed by filling with a conductive material. Traditional methods of filling internal wires include chemical vapor deposition (CVD) and physical vapor deposition (PVD). However, as the inner wire size and line width shrink below 0.25 microns, it is very difficult to fill the inner wires with a conventional technique using void-free.

Therefore, in the integrated circuit fabrication process, electroplating techniques are used to effectively fill the conductive material into 0.25 micron pores. In the case of electrochemical plating, the process includes forming a seed layer prior to the surface of the substrate, and then immersing the substrate in an electrolyte for electroplating. The electrolyte is generally rich in ions to be electroplated onto the surface of the substrate. Therefore, an electrical bias is applied to drive the reduction reaction to reduce the metal ions and precipitate the metal onto the seed layer to form a metal coating layer. However, as the line width of the integrated circuit continues to shrink, the miniaturization of the semiconductor element has entered the nanometer level, the thickness of the seed layer is reduced to below several tens of nanometers and the surface roughness must be less than 1 nm. If the surface roughness of the seed layer is too large, pores may be generated between the seed layer and the wire during the electroplating process, thereby causing a problem that the reliability of the element is lowered.

Therefore, a new integrated circuit process has been developed to reduce the roughness to effectively avoid voids in the electroplating process and improve the reliability of the components, which is an important research focus in the current integrated circuit process technology.

The invention is a master's thesis of Mr. Zhan Zongqi, titled "Study on the Effect of Electromigration Effect on the Roughness of Copper Films", August 28, 1997. According to the second paragraph of Article 22, paragraph 2 of the Patent Law, it has been found in the publication before the application. "But due to research, experimenters, applicants within six months from the date of publication or use, are not subject to the preceding paragraph. The provisions are limited, so the case was filed before the 28th of February, the Republic of China, that is, no loss of novelty.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for reducing the surface roughness of a metal film by reducing the surface roughness of the metal film by applying an electric current to the surface of the metal film. Due to the reduction in the surface roughness of the metal film, the properness of the integrated circuit components is greatly improved.

To achieve the above object, the present invention provides a method for reducing the surface roughness of a metal film, comprising providing a substrate; forming a metal film on the substrate; and passing an electric current on the metal film. The method further includes annealing a temperature after forming a metal film on the substrate and before passing the current to the metal film.

According to an embodiment of the invention, the metal film is made of copper.

According to an embodiment of the invention, the metal film is made of gold.

According to an embodiment of the invention, the material of the metal film is silver.

According to the present invention described in the embodiment, a current density of ¹⁰⁴ to ¹⁰⁷ Amps / dm.

According to an embodiment of the invention, the current passing through is direct current or alternating current.

According to an embodiment of the invention, the thickness of the formed metal film ranges from 3 nm to 50 nm, and more preferably, the thickness of the formed metal film ranges from 3 nm to 10 nm.

According to an embodiment of the invention, the annealing temperature is between 100 ° C and 500 ° C.

According to an embodiment of the invention, the current is applied for a period of from 1 minute to 15 hours.

According to an aspect of the present invention, a process for fabricating a wire structure includes providing a substrate; forming a barrier layer over the substrate, patterning the barrier layer to form a plurality of openings; forming a seed layer on the openings Above; passing an electric current to the seed layer; forming a metal film on the seed layer; and chemically grinding the metal film to the barrier layer. The method further includes annealing at a temperature after forming a seed layer on the barrier layer and the openings and before passing the current through the seed layer.

According to an embodiment of the invention, the material of the seed layer and the metal film is copper.

According to an embodiment of the invention, the material of the seed layer and the metal film is gold.

According to an embodiment of the invention, the material of the seed layer and the metal film is silver.

According to the present invention described in the embodiment, a current density of ¹⁰⁴ to ¹⁰⁷ Amps / dm.

According to an embodiment of the invention, the current passing through is direct current or alternating current.

According to an embodiment of the invention, the formed seed layer has a thickness ranging from 3 nm to 50 nm, and more preferably the seed layer has a thickness ranging from 3 nm to 10 nm.

According to an embodiment of the invention, the annealing temperature is between 100 ° C and 500 ° C.

According to an embodiment of the invention, the current is applied for a period of from 1 minute to 15 hours.

According to another aspect of the present invention, a process for fabricating a wire structure includes providing a substrate, forming a barrier layer over the substrate, patterning the barrier layer to form a plurality of openings, and forming a seed layer on the substrate Above the opening; annealing at a first temperature; passing a first current to the seed layer; forming a metal film on the seed layer; chemically grinding the metal film to the barrier layer; The temperature is annealed; and a second current is passed through the metal film.

According to an embodiment of the invention, the first current and the second current are direct current.

According to an embodiment of the invention, the first current and the second current are alternating current.

According to an embodiment of the invention, the first temperature and the second temperature are between 100 ° C and 500 ° C.

According to an embodiment of the invention, the current is applied for a period of from 1 minute to 15 hours.

The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

The present invention is a method for reducing the surface roughness of a metal film by which the surface roughness of the metal film can be lowered. In the semiconductor process, the reduction in roughness contributes to the subsequent planarization process and allows the stacking of subsequent integrated circuits to be tightly bonded without the occurrence of void defects.

First, the principle of electromigration is introduced. The electromigration effect is the movement of metal ions caused by the temperature and electron wind multiplication effect. Generally, the higher the temperature, the more easily the metal ion electromigration occurs. Phenomenon, according to CY Chang, SM Sze, ULSI Technology, the McGRAW-HILL, P. 663,1996. JR Black, Proceedings of The IEEE, Vol 57, P. 1587, 1969. As shown in Fig. 1a, part of the aluminum ions will transition to the top of the potential well at high temperatures. This activated aluminum ion is basically not limited to the crystal lattice, but it does not leave. Will not fall back into the well, when the external electric E is involved, the activated aluminum ions will withstand two additional forces, 1. Power FE, this part of the force is because the A1 ⁺ ions are subjected to external power Effect; 2. Electron wind force FP, this part of the force is due to the momentum transfer caused by the collision of electrons and aluminum ions at high current density; since FP is in the same direction as the electron flow, FE and electron flow In the opposite direction, and FP>>FE, so aluminum ions will be exposed to electrons Pushed to move along the direction of electron flow, and vacancies V (vacancy) is moved against the direction of electron flow. Therefore, when passing a high-density current, metal ions are moved in the direction of electron flow.

Through intensive efforts in experimentation and research and development, the inventors published their results in the master's thesis "The Study of the Effect of Electromigration Effect on the Roughness of Copper Films" by Mr. Zhan Zongqi, and found that the surface of polycrystalline metal films is reduced after passing high-density currents. Surface roughness, and the flat surface formed is an atomic level plane. In this study, a 50 nm copper metal film was formed on a substrate by electron beam evaporation, under the conditions of a room temperature, an evaporation pressure of 2×10 ^-6 torr, and a coating rate of 0.2 nm/sec. The surface roughness of the copper metal film was measured by a microscope (AFM), and the surface roughness of the formed copper metal film was 0.6 nm (as shown in Fig. 1b). After annealing for an additional minute at 250 ° C, the surface roughness was increased to 7.5 nm (as shown in Figure 1c). As shown in Fig. 1d, after applying a high-density current to the copper metal film for 1 hour, the surface roughness was reduced to 2.3 nm, and the 1f is a surface roughness after applying a high-density current to the copper metal film for 10 hours. Reduced to 1.4 nm. As the passing current time increases, the surface roughness decreases. However, depending on the current density, the time required to reduce the surface roughness is also different. According to the major findings of the above research, it can be applied to semiconductor processes or other related processes, especially in the semiconductor copper metal process of nanometer linewidth.

2a to 2b are cross-sectional views showing the process of an element according to an embodiment of the present invention. Referring to FIG. 2a, a metal film 110 is first formed on the insulating substrate 100, wherein the metal film 110 has a thickness of between 3 nm and 50 nm, and more preferably the metal film 110 has a thickness of 3 nm to 10 nm. between. The material of the metal thin film 110 may be gold, silver, copper or an alloy of the above metals, preferably gold or silver, more preferably copper. The method for forming the metal thin film 110 is not limited, and may be a physical vapor deposition method or a chemical vapor deposition method. Then, the substrate 100 and the metal thin film 110 thereon are annealed at a temperature, thereby reducing stress between the metal thin film 110 and the substrate 100 and eliminating defects in the metal thin film 110, thereby transforming the metal thin film 110 into a plurality of Crystal structure phase. Wherein the annealing temperature is between 100 ° C and 500 ° C. Since the thickness of the metal thin film 110 is extremely thin, when the polycrystalline structure is formed, the metal thin film 110 is made uneven to form the rough surface 111. Next, a current is applied to the metal thin film 110 for a time of 1 minute to 15 hours, and a current density of 10 ⁴ to 10 ⁷ amps/cm 2 . The metal film 110 is flattened by the electromigration effect to form a flat surface 111' due to the passage of a high-density current, and the roughness of the flat surface 111' is reduced to less than 1 nm.

3a to 3e are cross-sectional views showing a metal wire process according to another embodiment of the present invention. Referring to FIG. 3a, the barrier layer 210 is first formed on a substrate 200. The barrier layer 210 may be made of titanium nitride (TiN), tantalum nitride (TaN) or tantalum (Ta). Layer 210 has a thickness of between about 30 nanometers and 50 nanometers. Referring again to FIG. 3b, a patterning process is then performed to pattern the barrier layer 210 and form a plurality of openings 211 having a minimum width of less than 250 nm, wherein the opening 211 can be, for example, a trench or a via (via The patterning process includes a lithography process and an etch process. The seed layer 220 is formed in the plurality of trenches 211, wherein the seed layer 220 has a thickness between about 3 nm and 50 nm, and more preferably the seed layer 220 has a thickness between 3 nm and 10 nm. The material of the seed layer 220 may be gold, silver, copper or an alloy of the above metals, preferably gold or silver, more preferably copper. The method of forming the seed layer 220 is not limited, and sputtering can be generally used. However, since the sputtering method has a problem of insufficient coverage for high aspect ratio holes, it is replaced by chemical vapor deposition (CVD) in this application. Next, annealing is performed at a first temperature to reduce stress between the seed layer 220, the substrate 200, and the barrier layer 210, and to eliminate defects in the seed layer 220, thereby transforming the seed layer 220 into a polycrystalline structure. The first temperature is between about 100 ° C and 500 ° C. Since the thickness of the seed layer 220 is extremely thin, when the polycrystalline structure is formed, the seed layer 220 is made uneven to form the rough surface 221. Next, as shown in FIG. 3c first, by the first current to the plurality of the seed layer 220 an opening 211, through the current time is 1 minute to 15 hours, a current density of ¹⁰⁴ to ¹⁰⁷ Amps / dm. Due to the passage of the high-density current, the seed layer 220 planarizes the rough surface 221 of the seed layer due to the electromigration effect to form the flat surface 221', and the roughness of the flat surface 221' is reduced to less than 1 nm. Continuing to refer to FIG. 3d, a metal layer 230 is formed on the seed layer 220 in the opening 211 and the patterned barrier layer 210 using electroplating, and fills the opening 211. Since the roughness of the flat surface 221' of the seed layer 220 is reduced to less than 1 nm, when the metal layer 230 is formed on the seed layer 220 in the opening 211 by electroplating, the seed layer 220 and the metal layer 230 are They are tightly bound without creating defects or pores. Referring to FIG. 3e, the chemical metal polishing (CMP) is followed to remove the excess metal layer 230 until the patterned barrier layer 210 is exposed, leaving the metal layer 230 in the opening 211. Form a well-formed metal wire.

A cross-sectional view of a metal wire process in accordance with still another embodiment of the present invention is shown. The process as described above is followed by annealing at a second temperature to eliminate defects in the metal layer 230 due to chemical mechanical polishing. Wherein the second temperature is between about 100 ° C and 500 ° C. Then, the second current is passed through the metal layer 230 and the seed layer 220 in the plurality of openings 211 for a period of time of about 1 minute to 15 hours, and the current density is about 10 ⁴ to 10 ⁷ amps/cm 2 . The high-density current is applied to the metal layer 230 and the seed layer 220 to planarize the metal layer 230 and the upper surface 231 of the seed layer 220 due to the electromigration effect, and the roughness of the upper surface 231 is reduced to less than 1 nm. The surface roughness decreases as the time of the current is increased. Finally, a well-formed metal wire is formed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application.

100 200. . . Substrate

110. . . Metal film

111. . . Rough surface

111’. . . Flat surface

210. . . Barrier layer

220. . . Seed layer

211. . . Opening

221. . . Rough surface

221’. . . Flat surface

230. . . Metal layer

231. . . Upper surface

Figure 1a shows the electromigration model.

Figures 1b to 1d show the roughness of the surface of the copper metal film measured by atomic force microscopy (AFM).

2a to 2b are cross-sectional views showing the process of an element according to an embodiment of the present invention.

3a to 3f are cross-sectional views showing the process of another embodiment of the present invention.

210. . . Barrier layer

220. . . Seed layer

211. . . Opening

221. . . Rough surface

221’. . . Flat surface

Claims (31)

A method for reducing surface roughness of a metal film, comprising: providing a substrate; forming a metal film on the substrate; and passing an electric current on the metal film to generate an electromigration effect. The method for reducing the surface roughness of a metal film according to claim 1, further comprising annealing a metal film after the substrate and before the metal film by the current. The method for reducing the surface roughness of a metal film according to claim 1, wherein the metal film is made of copper. The method for reducing the surface roughness of a metal film according to claim 1, wherein the metal film is formed of gold. The method for reducing the surface roughness of a metal film according to claim 1, wherein the metal film is made of silver. The method for reducing the surface roughness of a metal film as described in claim 1, wherein the current has a density of 10 ⁴ to 10 ⁷ amps/cm 2 . The method for reducing the surface roughness of a metal film according to claim 1, wherein the current is a direct current. The method for reducing the surface roughness of a metal film according to claim 1, wherein the current is AC. The method for reducing the surface roughness of a metal film according to claim 1, wherein the metal film is formed to have a thickness ranging from 3 nm to 10 nm. The method for reducing the surface roughness of a metal film according to claim 1, wherein the metal film is formed to have a thickness ranging from 3 nm to 50 nm. The method for reducing the surface roughness of a metal film as described in claim 2, wherein the annealing temperature is between 100 ° C and 500 ° C. The method for reducing the surface roughness of a metal film according to claim 1, wherein the time for passing the current is between about 1 minute and 15 hours. A process for fabricating a wire structure, comprising: providing a substrate; forming a barrier layer over the substrate, patterning the barrier layer to form a plurality of openings; forming a seed layer in the openings; a seed layer; forming a metal film on the seed layer; and grinding the metal film to the barrier layer using chemical mechanical polishing. The process of the wire structure of claim 13, further comprising annealing at a temperature after forming a seed layer in the openings and before passing the current to the seed layer. The process of the wire structure according to claim 13, wherein the seed layer and the metal film are made of copper. The process of the wire structure according to claim 13, wherein the seed layer and the metal film are made of gold. The process of the wire structure according to claim 13, wherein the seed layer and the metal film are made of silver. The process of the wire structure of claim 13, wherein the current has a density of 10 ⁴ to 10 ⁷ amps/cm 2 . The process of the wire structure of claim 13, wherein the current passed is direct current. The process of the wire structure of claim 13, wherein the current passed is alternating current. The process of the wire structure of claim 13, wherein the seed layer thickness is formed between 3 nm and 10 nm. The process of the wire structure of claim 13, wherein the seed layer thickness is between 3 nm and 50 nm. The process of the wire structure of claim 13, wherein the annealing temperature is between 100 ° C and 500 ° C. The process of the wire structure of claim 13, wherein the time for passing the current is between about 1 minute and 15 hours. The process of the wire structure according to claim 13, wherein a metal film is formed on the seed layer by using an electroless plating method. A process for fabricating a wire structure includes: providing a substrate; forming a barrier layer over the substrate, patterning the barrier layer to form a plurality of openings; forming a seed layer in the openings; Annealing at a temperature; passing a first current to the seed layer; forming a metal film on the seed layer; grinding the metal film to the barrier layer using chemical mechanical polishing; annealing at a second temperature; Passing a second current to the metal film. The process of the wire structure of claim 25, wherein the current density is from 10 ⁴ to 10 ⁷ amps/cm 2 . The process of the wire structure of claim 25, wherein the first current and the second current are direct current. The process of the wire structure of claim 25, wherein the first current and the second current are alternating current. The process of the wire structure of claim 25, wherein the first temperature and the second temperature are between 100 ° C and 500 ° C. The method of forming a wire structure according to claim 26, wherein the time of passing the first current and the second current is between about 1 minute and 15 hours, respectively.