TWI467561B - Display and operating method thereof - Google Patents

Description

Display and its operation method

The present invention relates to a display, and more particularly to a display for serially transmitting information by a Timing Controller and a method of operating the same.

A flat display device such as a thin film transistor-liquid crystal display (TFT-LCD) is used in place of a conventional cathode ray tube (CRT) display device. Compared to conventional CRT displays, TFT-LCD devices have many advantages, such as low operating voltage, low power consumption, small size, thin thickness, and light weight.

In general, the display's timing controller and source driver transmit control codes and color data in a side-by-side transmission. Although parallel data transfer can reduce transmission time, the number of pins that output and receive signals increases. According to the above, there are many lines on the printed circuit board (PCB) on which the timing controller and the source driver are arranged, and the circuit on the printed circuit board is complicated. Since the number of pins of the timing controller and the source driver cannot be reduced, the chip area cannot be reduced, and the hardware cost of the timing controller and the source driver cannot be reduced.

The invention provides a display and a method for operating the same, the display has a timing controller and a source driver, and the timing controller and the source driver are synchronized It operates without clock signals and latch signals. Thereby, the hardware cost of the timing controller and the source driver can be reduced.

The invention provides a display comprising a display panel, a timing controller and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to each other. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock the clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and a plurality of control packets to the source drivers according to the lock signal. The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets to the display panel, and the source drivers determine the output timings of the pixel voltages according to the clock of the timing controller and the control packets. The training packets and the color data packets are serially transmitted to the source drivers.

In an embodiment of the invention, each control packet includes two start bits, two end bits, and a control code, wherein the control code is located between the start bits and the end bits.

In an embodiment of the invention, the training packets, the color data packets, and the control packets are transmitted using a differential signal, respectively.

In an embodiment of the invention, each color data packet includes two start bits, two end bits, and a color data code, wherein the color data code is located between the start bits and the end bits.

In an embodiment of the invention, the color data code corresponds to two of the red color data, the green color data, and the blue color data.

In an embodiment of the invention, the color data code corresponds to a red color One of the materials, green color data and blue color data.

In an embodiment of the invention, the start bits respectively correspond to a logic high level, and the end bits respectively correspond to a logic low level.

In an embodiment of the present invention, each training packet includes two start bits, two end bits, a first clock code, and a second clock code, wherein the first clock code is located at the start bits. Between the element and the second clock code, the second clock code is located between the first clock code and the end bits.

In an embodiment of the present invention, the start bit and the plurality of bits of the first clock code respectively correspond to a logic high level, and the end bits and the plurality of bits of the second clock code respectively correspond to A logic low level.

The invention also provides a method for operating a display, the display comprising a display panel, a timing controller and a plurality of source drivers. The method of operation of the display includes the following steps. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock the clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and a plurality of control packets to the source drivers according to the lock signal. The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets according to the latch signal, and the output timings of the pixel voltages are determined according to the clock of the timing controller and the control packets. The training packets and the color data packets are serially transmitted to the source drivers.

In one embodiment of the invention, the source drivers are clocks that sequentially lock the timing controller. When the i-th source driver locks the clock of the timing controller, the clock-lock signal is output to the i+1th source driver to trigger The i+1th source driver locks the clock of the timing controller. When the last source driver locks the clock of the timing controller, the last source driver outputs a lock signal to the timing controller, and the first is triggered by a system voltage to lock the timing controller clock. Here, i is greater than or equal to 1 and less than the number of these source drivers.

In one embodiment of the invention, these source drivers utilize phase comparison to lock the timing of the timing controller.

Based on the above, in the display and the method of operating the same according to the embodiments of the present invention, the timing controller is synchronized with the operation of the source driver through the training packet, and the timing at which the source driver outputs the pixel voltage is set through the control packet. Thereby, the timing controller operates in synchronization with the source driver without passing through the clock signal and the latch signal, and the hardware cost of the timing controller and the source driver can be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a system diagram of a display in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the display 100 includes a timing controller 110 , a plurality of source drivers, and a display panel 130 . In FIG. 1, six source drivers 120_1~120_6 are exemplarily shown. The timing controller 110 is coupled to the source drivers 120_1 120 120_6 to output a plurality of training packets TRP, a plurality of control packets CLP or a plurality of color data packets DAP to the source drivers 120_1 120 120_6. The source drivers 120_1~120_6 are coupled to the display panel 130, to output a plurality of pixel voltages VP to the display panel 130, respectively.

In this embodiment, the training packet TRP, the control packet CLP, and the color data packet DAP are respectively transmitted in series using a differential signal. Based on the circuit design of the timing controller 110 and the source drivers 120_1~120_6, the timing controller 110 can transmit the training packet TRP, the control packet CLP, and the color data packet DAP to a corresponding group through a differential signal line or two sets of differential signal lines. The source driver (such as 120_1~120_6), but the embodiment of the present invention is not limited thereto.

When the source drivers 120_1~120_6 receive the training packet TRP, the source drivers 120_1~120_6 lock the timing of the training packet TRP according to the received training packet TRP, respectively, to lock the clock of the timing controller 110. Here, the source drivers 120_1~120_6 lock the clock of the timing controller 110 through phase comparison. When each of the source drivers 120_1~120_6 locks the clock of the timing controller 110, respectively, a clock lock signal CL is outputted. When the source drivers 120_1~120_6 lock the clock of the timing controller 110, a lock signal LK is output to the timing controller 110.

In the present embodiment, the source drivers 120_1~120_6 sequentially lock the clock of the timing controller 110. In detail, the source driver 120_1 is locked by the system voltage VDD to lock the clock of the timing controller 110. When the source driver 120_1 locks the clock of the timing controller 110, the clock lock signal CL is output to the source driver 120_2. The clock of the timing controller 110 is locked by the trigger source driver 120_2. When the source driver 120_2 locks the clock of the timing controller 110, the clock lock signal CL is output to the source driver 120_3 to trigger the source driver 120_3 to lock the timing control. The clock of the controller 110. The rest are deduced by analogy and will not be repeated here. When the source driver 120_6 locks the clock of the timing controller 110, the source driver 120_6 outputs a clock lock signal CL (ie, the lock signal LK) to the timing controller 110 to inform the timing controller 110 that the source drivers 120_1~120_6 are The clock of the timing controller 110 is locked.

When the timing controller 110 receives the lock signal LK, the timing controller 110 outputs the control packet CLP, the color data packet DAP, and the latch signal TP to the source drivers 120_1 120 120_6 according to the lock signal LK. The source drivers 120_1~120_6 respectively output the pixel voltage VP to the display panel 130 according to the latch signal TP and the received color data packet DAP.

2 is a timing diagram of the display of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, after the source drivers 120_1~120_6 lock the clock of the timing controller 110, the source drivers 120_1~120_6 can correctly receive the data packets transmitted by the timing controller 110 (ie, control packet CLP and color data). Packet DAP). Therefore, when the source drivers 120_1~120_6 do not lock the clock of the timing controller 110 (ie, in the period T1), the timing controller 110 transmits the training packet TRP to the source drivers 120_1~120_6 so that the source driver 120_1 ~120_6 locks the clock of the timing controller 110 according to the training packet TRP.

Also, the period T1 is determined when the source driver 120_6 outputs the lock signal LK. That is, the period T1 is determined by the time required for the source drivers 120_1~120_6 to lock the clock of the timing controller 110. During period T1, the latch signal TP is enabled to trigger the source drivers 120_1~120_6 to reposition their output voltages. The latching signal TP is enabled for a time ta greater than or equal to The time required to transmit 3 training packets to the TRP. The voltages of the source drivers 120_1~120_6 can be relocated by the charge sharing, but the embodiment of the present invention is not limited thereto.

After the source drivers 120_1~120_6 lock the clock of the timing controller 110, the timing controller 110 transmits the first start packet SP1 to the source drivers 120_1~120_6 to inform the source drivers 120_1~120_6 to start transmitting the control packet CLP. After the source drivers 120_1~120_6 receive the control packet CLP, the timing controller 110 transmits the second start packet SP2 to the source drivers 120_1~120_6 to inform the source drivers 120_1~120_6 to start transmitting the color data packet DAP. Then, the timing controller 110 outputs the control packet CLP to the source drivers 120_1~120_6 to set the operation modes of the source drivers 120_1~120_6 or the parameters of the source drivers 120_1~120_6. Alternatively, the source drivers 120_1~120_6 output the color data packet DAP to the source drivers 120_1~120_6, and the source drivers 120_1~120_6 encapsulate the DAP output pixel voltage VP according to the received color data.

After the source drivers 120_1~120_6 receive enough color data packets DAP, the timing controller 110 enables the latch signal TP to control the timing at which the source drivers 120_1~120_6 output the pixel voltage VP. Thereby, the source drivers 120_1~120_6 and the timing controller 110 can operate synchronously without transmitting the clock signal, and can reduce the number of pins of the source drivers 120_1~120_6 and the timing controller 110, and the source drivers 120_1~120_6 The hardware cost with the timing controller 110 can be reduced.

FIG. 3 is a schematic diagram of FIG. 2 of a training packet according to an embodiment of the present invention; FIG. Figure. Referring to FIG. 3, in this embodiment, each training packet TRP includes two start bits, two end bits, a first clock code, and a second clock code, where the bits of the first clock code The number of bits is the same as the number of bits in the first clock code. The first clock code is located between the start bit and the second clock code, and the second clock code is located between the first clock code and the end bit. Wherein, the start bit and the bit of the first clock code respectively correspond to a logic high level H, and the end bits and the bits of the second clock code respectively correspond to a logic low level L, so that the training packet is The TRP is logically equivalent to a pulse of the clock signal.

4 is a schematic diagram of the control packet of FIG. 2 according to an embodiment of the invention. Referring to FIG. 4, in this embodiment, each control packet CLP includes two start bits, two end bits, and a control code. Wherein, the control code is located between the start bit and the end bit. And, the control code is composed of a plurality of control data bits CB. In addition, the start bit corresponds to a logic high level H, and the end bits respectively correspond to a logic low level L.

FIG. 5 is a schematic diagram of a color data packet according to an embodiment of the invention. FIG. Referring to FIG. 5, in this embodiment, each color data packet DAP includes two start bits, two end bits, and a color data code, where the color data code is located in the start bit and the end bit. between. Moreover, the color data code is composed of a plurality of color data bit DBs, the start bits respectively correspond to a logic high level H, and the end bits respectively correspond to a logic low level L.

In this embodiment, the color data code may correspond to two of the red color data, the green color data, and the blue color data. Or, color capital The material code may correspond to one of a red color material, a green color material, and a blue color material, which may be adjusted according to those skilled in the art.

In addition, in this embodiment, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP will be the same (that is, the number of bits is the same). Assuming that the size of each color data is 10 bits, and the color data code corresponds to two of the red color data, the green color data, and the blue color data, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP is Will be 24 bits (ie 2+10+10+2). Assuming that the size of each color data is 10 bits, and the color data code corresponds to one of the red color data, the green color data, and the blue color data, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP is Will be 14 bits (ie 2+10+2).

Assuming that the size of each color data is 8 bits, and the color data code corresponds to two of the red color data, the green color data, and the blue color data, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP is Will be 20 bits (ie 2+8+8+2). Assuming that the size of each color data is 8 bits, and the color data code corresponds to one of the red color data, the green color data, and the blue color data, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP is Will be 12 bits (ie 2+8+2).

Assuming that the size of each color data is 6 bits, and the color data code corresponds to two of the red color data, the green color data, and the blue color data, the training packet TRP, the control packet CLP, and the color data packet are included. The DAP packet size will be 16 bits (ie 2+6+6+2). Assuming that the size of each color data is 6 bits, and the color data code corresponds to one of the red color data, the green color data, and the blue color data, the packet size of the training packet TRP, the control packet CLP, and the color data packet DAP is Will be 10 bits (ie 2+6+2).

6 is a system diagram of a display in accordance with another embodiment of the present invention. Referring to FIG. 1 and FIG. 6, in the present embodiment, the display 200 is substantially the same as the display 100, except that the timing controller 210 outputs two latch signals TP ₁ and TP ₂ . Further, the source driver 120_1 to 120_ controlled by the latch signal TP ₁ outputs the pixel voltage VP, a source driver 120_4 ~ 120_6 controlled by the latch signal TP ₂ outputs the pixel voltage VP, i.e. the source driver 120_1 to 120_6, respectively, by The pixel voltage VP is outputted in response to the latch signals TP ₁ and TP ₂ . By analogy, when the timing controller 210 outputs a plurality of latch signals, the source drivers (eg, 120_1~120_6) are respectively controlled by the corresponding latch signals to output the pixel voltage VP.

7 is a flow chart of a method of operating a display in accordance with an embodiment of the present invention. Referring to FIG. 7, the display of the embodiment includes a timing controller and a plurality of source drivers. First, the timing controller outputs a plurality of training packets to the source drivers (step S710). When the source drivers lock the clock of the timing controller in accordance with the training packets, the lock signal is output to the timing controller (step S720). Then, the timing controller outputs a plurality of control packets, a plurality of color data packets, and at least one latch signal to the source drivers according to the lock signal (step S730), wherein the training packets and the color data packets are serially transmitted to the Source driver. then, The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets in accordance with the latch signal (step S740). The order of the above steps is for illustrative purposes, and the embodiments of the present invention are not limited thereto, and the details of the above steps may be referred to the descriptions of the displays 100 and 200, and details are not described herein again.

FIG. 8 is a schematic diagram of a system of a display according to still another embodiment of the present invention. Referring to FIG. 1 and FIG. 8 , in the embodiment, the display 300 is substantially the same as the display 100 , except that the timing controller 310 and the source drivers 320_1 320 320_6 are different. Similar to the source drivers 120_1~120_6, when the source drivers 320_1~320_6 lock the clock of the timing controller 310 according to the training packet TRP, the source driver 320_6 outputs the clock lock signal CL (ie, the lock signal LK) to the timing controller. 310, to inform the timing controller 310 that the source drivers 320_1~320_6 all lock the clock of the timing controller 310. When the timing controller 310 receives the lock signal LK, the timing controller 110 outputs the control packet CLP, the color data packet DAP to the source drivers 320_1~320_6 according to the lock signal LK.

In this embodiment, the source drivers 320_1~320_6 respectively output the pixel voltage VP to the display panel 130 according to the received color data packet DAP. Moreover, the source drivers 320_1~320_6 set their operation mode or parameters therein according to the received control packet CLP. Therefore, the timing controller 310 can determine the timing of the output of the pixel voltage VP by the source drivers 320_1~320_6 through the control packet CLP. The operation of the source drivers 320_1~320_6 is based on the clock of the timing controller 310, so the source drivers 320_1~320_6 will be based on the received control packets CLP and The timing of the timing controller 310 determines the output timing of the pixel voltage VP.

9 is a flow chart of a method of operating a display in accordance with another embodiment of the present invention. Please refer to FIG. 7 and FIG. 9, which differ in steps S930 and S940. In step S930, the timing controller outputs a plurality of control packets and a plurality of color data packets to the source drivers according to the lock signal, wherein the training packets and the color data packets are serially transmitted to the source drivers. In step S940, the source drivers respectively output a plurality of pixel voltages corresponding to the color data packets, and the output timings of the pixel voltages are determined according to the clock of the timing controller and the control packets. The order of the above steps is for illustrative purposes, and the embodiments of the present invention are not limited thereto, and the details of the above steps may be referred to the descriptions of the displays 100 to 300, and details are not described herein again.

In summary, in the display and the method for operating the same according to the embodiments of the present invention, the timing controller and the source driver are synchronized to operate through the training packet, and the timing of the output voltage of the source driver is set by the control packet. . Thereby, the timing controller operates in synchronization with the source driver without the clock signal and the latch signal, and the hardware cost of the timing controller and the source driver can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300‧‧‧ display

110, 210, 310‧‧‧ timing controller

120_1~120_6, 320_1~320_6‧‧‧ source drive

130‧‧‧ display panel

CB‧‧‧Control data bits

CL‧‧‧clock lock signal

CLP‧‧‧ control package

DAP‧‧‧ color data package

DB‧‧‧ color data bits

H‧‧‧Logical high level

L‧‧‧Logic low level

LK‧‧‧ lock signal

SP1‧‧‧ first start packet

SP2‧‧‧Second start packet

During the period of T1‧‧

ta‧‧‧Time

TP, TP ₁ , TP ₂ ‧‧‧ latch signal

TRP‧‧‧ training package

VDD‧‧‧ system voltage

VP‧‧‧ pixel voltage

S710, S720, S730, S740, S930, S940‧‧ steps

1 is a system diagram of a display in accordance with an embodiment of the present invention.

2 is a timing diagram of the display of FIG. 1 according to an embodiment of the invention.

FIG. 3 is a schematic diagram of FIG. 2 of a training packet according to an embodiment of the invention.

4 is a schematic diagram of the control packet of FIG. 2 according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a color data packet according to an embodiment of the invention. FIG.

6 is a system diagram of a display in accordance with another embodiment of the present invention.

7 is a flow chart of a method of operating a display in accordance with an embodiment of the present invention.

FIG. 8 is a schematic diagram of a system of a display according to still another embodiment of the present invention.

9 is a flow chart of a method of operating a display in accordance with another embodiment of the present invention.

300‧‧‧ display

310‧‧‧Sequence Controller

320_1~320_6‧‧‧Source Drive

130‧‧‧ display panel

CL‧‧‧clock lock signal

CLP‧‧‧ control package

DAP‧‧‧ color data package

LK‧‧‧ lock signal

TRP‧‧‧ training package

VDD‧‧‧ system voltage

VP‧‧‧ pixel voltage

Claims (15)

A display device includes: a display panel; a timing controller; and a plurality of source drivers coupled to the timing controller and the display panel, wherein the source drivers are coupled to each other; wherein the timing controller outputs more a training packet to the source drivers, when the source drivers lock the clock of the timing controller according to the training packets, output a lock signal to the timing controller, and the timing controller is based on the lock signal And outputting a first start packet, a plurality of control packets, a second start packet, and a plurality of color data packets to the source drivers, wherein the source drivers respectively output a plurality of pixel voltages corresponding to the color data packets Up to the display panel, the source drivers determine an output timing of the pixel voltages according to a clock of the timing controller and the control packets, wherein the training packets, the first start packet, the control packets, and the The second start packet and the color data packets are serially transmitted to the source drivers, and the first start packet is used to notify the source drivers Begins transmitting the plurality of control packet, the packet for informing the start of the second plurality of source driver starts transmitting the plurality of color data packet. The display device of claim 1, wherein the source drivers sequentially lock the clock of the timing controller, wherein the i-th source driver locks the clock of the timing controller, and outputs a clock. Locking the signal to the i+1th source driver to trigger the i+1th source driver to lock the clock of the timing controller, and the last source driver locks the timing control When the clock of the controller is output, the lock signal is output to the timing controller, and the first source driver is locked by a system voltage to lock the clock of the timing controller, i is greater than or equal to 1 and smaller than the source driving Quantity. The display device of claim 1, wherein each of the control packets includes two start bits, two end bits, and a control code, wherein the control code is located in the start bits and Some ending bits between. The display device of claim 3, wherein the start bits respectively correspond to a logic high level, and the end bits respectively correspond to a logic low level. The display device of claim 1, wherein the training packets, the color data packets, and the control packets are respectively transmitted by using a differential signal. The display of claim 1, wherein each of the color data packets includes two start bits, two end bits, and a color data code, wherein the color data code is located at the start bits. Between the yuan and the end bits. The display of claim 6, wherein the color data code corresponds to two of a red color data, a green color data, and a blue color data. The display device of claim 6, wherein the color data code corresponds to one of a red color data, a green color data, and a blue color data. The display of claim 6, wherein the display The start bits respectively correspond to a logic high level, and the end bits respectively correspond to a logic low level. The display device of claim 1, wherein each of the training packets includes two start bits, two end bits, a first clock code, and a second clock code, wherein the A clock code is located between the start bit and the second clock code, and the second clock code is located between the first clock code and the end bits. The display device of claim 10, wherein the start bit and the plurality of bits of the first clock code respectively correspond to a logic high level, the end bit and the second clock A plurality of bits of the code respectively correspond to a logic low level. The display of claim 1, wherein the source drivers utilize phase comparison to lock the clock of the timing controller. A method for operating a display, the display includes a timing controller and a plurality of source drivers, the method of operating the display includes: outputting a plurality of training packets to the source drivers through the timing controller; and when the source drivers When the timing of the timing controller is locked according to the training packets, a lock signal is outputted to the timing controller; and the timing controller outputs a first start packet, a plurality of control packets, and a sequence according to the lock signal. The second start packet and the plurality of color data packets are encapsulated to the source drivers, wherein the first start packet is used to notify the source drivers to start transmitting the control packets, and the second start packet is used to notify the source devices The drive begins to transmit the color data packets; And outputting, by the source drivers, a plurality of pixel voltages corresponding to the color data packets, and the output timings of the pixel voltages are determined according to the clock of the timing controller and the control packets; wherein The training packet, the first start packet, the control packet, the second start packet, and the color data packets are serially transmitted to the source drivers. The operating method of the display device of claim 13, wherein the source drivers sequentially lock the clock of the timing controller, and the i-th source driver locks the clock of the timing controller, and outputs a clock lock signal to the i+1th source driver to trigger the i+1th source driver to lock the clock of the timing controller, and output the lock when the last source driver locks the clock of the timing controller The signal is sent to the timing controller, and the first one is triggered by a system voltage to lock the clock of the timing controller, i is greater than or equal to 1 and less than the number of the source drivers. The method of operating a display of claim 14, wherein the source drivers utilize phase comparison to lock a clock of the timing controller.