TWI466521B - Duplex mismatch detection - Google Patents

Description

Duplex mismatch detection method and device

The present invention relates to a material communication. More specifically, the present invention relates to duplex mismatch detection in a data communication channel.

A duplex mismatch occurs when one link partner is in full-duplex mode and another link partner on the link is in half-duplex mode. When transmitting in full-duplex mode, you cannot send any data in half-duplex mode. To make matters worse, the full-duplex link will be sent whenever it wants to send, regardless of whether the half-duplex is currently being sent, resulting in a conflict between the half-duplex frame being sent and the frame receiver error. . Therefore, the signal frame sent by half-duplex is rarely successfully transmitted. The actual data rate on the duplex mismatch link was measured and found to be only 1% of the TCP/IP traffic link's capability rate.

In general, in one aspect, the present invention provides an apparatus comprising: at least one port for transmitting a first data signal frame in a half-duplex mode over a communication channel and receiving a second through the communication channel a data signal frame, wherein the at least one port includes a collision detecting circuit, configured to detect a collision between the first data signal frame and the second data signal frame on the communication channel; and a duplex mismatch circuit Declaring a duplex mismatch when the collision detection circuit detects a predetermined number of late collisions involving the first data signal frame, wherein each of the late collisions occurs in After the first predetermined data volume has been sent in the corresponding first data signal frame; or the conflict detection circuit detects a very late collision involving one of the first data signal frames, wherein the The late conflict occurs after the second predetermined amount of data has been sent in one of the first data signal frames, wherein the second predetermined amount of data is greater than the a first predetermined amount of data; and wherein the duplex mismatch indicates that a full-duplex mode is used for the second data signal frame.

In some embodiments, at least one of the predetermined amounts of data is selected based on a size of a collision domain of the communication channel. In some embodiments, at least one of the predetermined amounts of data is selected based on a multiple of a size of a collision domain of the communication channel. In some embodiments, the duplex mismatch circuit asserts the duplex mismatch by performing at least one or both of the following: setting a flag and transmitting a message in the memory circuit. In some embodiments, the at least one 埠 further comprises: a duplex mode circuit for changing the at least one 埠 from a half duplex mode to a full double when the duplex mismatch circuit declares a duplex mismatch Work mode. Some embodiments include a network device including the apparatus, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE standards 802.3, 802.11, 802.11a, 802.11b, 802.11g, 802.11 n, 802.16, and 802.20. Some embodiments include a network device including the apparatus, wherein the network device includes one of a switch, a router, and a network interface controller.

In general, in one aspect, the present invention provides an apparatus comprising: at least one device for transmitting a first data signal frame in a half duplex mode over a communication channel and receiving a second data signal frame through the communication channel, The at least one device includes collision detection means for detecting a collision between the first data signal frame and the second data signal frame on the communication channel; and a duplex mismatch device for Declaring a duplex mismatch when the conflict detection device detects a predetermined number of late collisions involving the first data signal frame, wherein each of the late conflicts occurs in a corresponding first data signal frame After the first predetermined amount of data has been sent; or the conflict detecting means detects a very late conflict involving one of the first data signal frames, wherein the late collision occurs in the first data signal frame After the second predetermined amount of data has been sent, wherein the second predetermined amount of data is greater than the first predetermined amount of data; Duplex mismatch indication: by using the data signal for the second frame, full-duplex mode.

In some embodiments, at least one of the predetermined amounts of data is selected based on a size of a collision domain of the communication channel. In some embodiments, at least one of the predetermined amounts of data is selected based on a multiple of a size of a collision domain of the communication channel. In some embodiments, the duplex mismatch device asserts the duplex mismatch by performing at least one or both of the following: setting a flag and transmitting a message in a memory circuit. In some embodiments, the at least one 埠 device further comprises: a duplex mode device for changing the at least one 埠 from a half duplex mode to a full when the duplex unmatched device declares a duplex mismatch Duplex mode. Some embodiments include a network device including the apparatus, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE standards 802.3, 802.11, 802.11a, 802.11b, 802.11g, 802.11 n, 802.16, and 802.20. Some embodiments include a network device including the apparatus, wherein the network device includes one of a switch, a router, and a network interface controller.

In general, in one aspect, the present invention provides a method comprising: transmitting a first data signal frame in a half duplex mode through a communication channel and receiving a second data signal frame through the communication channel; detecting the first data signal a collision between the frame and the second data signal frame on the communication channel; and declaring a duplex mismatch when: a predetermined number of late collisions involving the first data signal frame are detected, wherein Each of the late conflicts occurs after the first predetermined data volume has been sent in the corresponding first data signal frame; or a very late conflict involving one of the first data signal frames is detected, wherein the The late conflict occurs after the second predetermined amount of data has been transmitted in one of the first data signal frames, wherein the second predetermined amount of data is greater than the first predetermined amount of data; and wherein the duplex mismatch indication : For the second data signal frame, the full duplex mode is used.

In some embodiments, at least one of the predetermined amounts of data is selected based on a size of a collision domain of the communication channel. In some embodiments, at least one of the predetermined amounts of data is selected based on a multiple of a size of a collision domain of the communication channel. In some embodiments, declaring the duplex mismatch includes performing at least one of: setting a flag and transmitting a message in a memory circuit. Some embodiments include transmitting the first data signal frame in full duplex mode after declaring a duplex mismatch.

Generally, in one aspect, the present invention provides a computer program executable on a processor, comprising: detecting a first data signal frame transmitted in a half duplex mode through a communication channel and receiving through the communication channel An instruction for conflicting between the second data signal frames on the communication channel; and an instruction for declaring a duplex mismatch when: a predetermined number of late stages involving the first data signal frame are detected a conflict, wherein each of the late conflicts occurs after the first predetermined data volume has been sent in the corresponding first data signal frame; or a late conflict involving one of the first data signal frames is detected, wherein The late conflict occurs after a second predetermined amount of data has been transmitted in one of the first data signal frames, wherein the second predetermined amount of data is greater than the first predetermined amount of data; and wherein the duplex Mismatch indication: For the second data signal frame, full duplex mode is used.

In some embodiments, at least one of the predetermined amounts of data is selected based on a size of a collision domain of the communication channel. In some embodiments, at least one of the predetermined amounts of data is selected based on a multiple of a size of a collision domain of the communication channel. In some embodiments, the instructions for declaring the duplex mismatch include instructions for performing at least one of: setting a flag and transmitting a message in a memory circuit.

Generally, in one aspect, the present invention provides an apparatus comprising: at least one port for transmitting a first data signal frame in a full duplex mode through a communication channel and receiving a second data signal frame through the communication channel, wherein The at least one port includes a loop redundancy check (CRC) error detecting circuit for detecting a CRC error in the second data signal frame and a segment for detecting a segment of the second data signal frame One or both of the detection circuits; and a duplex mismatch circuit for declaring a duplex mismatch when one or both of the following conditions occur: the CRC error detection circuit is transmitting at the at least one And detecting, by one of the first data signal frames, a CRC error in one of the second data signal frames, or the segment detecting circuit detects a segment of one of the second data signal frames; The duplex mismatch indication: for the second data signal frame, a half duplex mode is used.

In some embodiments, the duplex mismatch circuit asserts the duplex mismatch by performing at least one or both of the following: setting a flag and transmitting a message in the memory circuit. In some embodiments, the at least one 埠 further comprises: a duplex mode circuit for changing the at least one 埠 from a full duplex mode to a half double when the duplex mismatch circuit declares a duplex mismatch Work mode. In some embodiments, the at least one 埠 further comprises: a collision forcing circuit responsive to the duplex mismatch circuit declaring a duplex mismatch when in the receiving one of the second data signal frames Receiving one of the second data signal frames after the predetermined amount of data, causing the at least one frame to send one of the first data signal frames. Some embodiments include a duplex mode circuit for when the duplex mismatch circuit declares a duplex mismatch after the collision forcing circuit causes the at least one chirp to transmit one of the first data signal frames The at least one 埠 changes from a full duplex mode to a half duplex mode. Some embodiments include a network device including the apparatus, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE standards 802.3, 802.11, 802.11a, 802.11b, 802.11g, 802.11 n, 802.16, and 802.20. Some embodiments include a network device including the apparatus, wherein the network device includes one of a switch, a router, and a network interface controller.

In general, in one aspect, the present invention provides an apparatus comprising: at least one device for transmitting a first data signal frame in a full duplex mode via a communication channel and receiving a second data signal frame through the communication channel, The at least one device includes a loop redundancy check (CRC) error detecting device for detecting a CRC error in the second data signal frame and a segment for detecting the second data signal frame One or both of the segmentation detecting means; and a duplex mismatching means for declaring a duplex mismatch when one or both of the following conditions occur: the CRC error detecting means is transmitting at the at least one device Detecting a CRC error in one of the second data signal frames when one of the first data signal frames is detected, or the segment detecting device detects a segment of one of the second data signal frames; The duplex mismatch indication: for the second data signal frame, a half duplex mode is used.

In some embodiments, the duplex mismatch device asserts the duplex mismatch by performing at least one or both of the following: setting a flag and transmitting a message in a memory circuit. In some embodiments, the at least one 埠 device further comprises: a duplex mode device, configured to change the at least one 埠 from a full duplex mode to a half when the duplex unmatched device declares a duplex mismatch Duplex mode. In some embodiments, the at least one UI device further comprises: a conflict enforcement device for declaring a duplex mismatch in response to the duplex mismatch device, in the receiving one of the second data signal frames Receiving one of the second data signal frames after the predetermined amount of data, causing the at least one device to transmit one of the first data signal frames. Some embodiments include a duplex mode device for when the duplex unmatched device declares a duplex mismatch after the conflict forcing device causes the at least one device to transmit one of the first data signal frames, The at least one helium device is changed from a full duplex mode to a half duplex mode. Some embodiments include a network device including the apparatus, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE standards 802.3, 802.11, 802.11a, 802.11b, 802.11g, 802.11 n, 802.16, and 802.20. Some embodiments include a network device including the apparatus, wherein the network device includes one of a switch, a router, and a network interface controller.

In general, in one aspect, the present invention provides a method comprising: transmitting a first data signal frame in a full duplex mode through a communication channel and receiving a second data signal frame through the communication channel; Declaring a duplex mismatch: detecting a CRC error in one of the second data signal frames when transmitting one of the first data signal frames, or receiving a score of one of the second data signal frames And wherein the duplex mismatch indicates that a half duplex mode is used for the second data signal frame.

In some embodiments, declaring the duplex mismatch includes performing at least one of a plurality of actions including: setting a flag and transmitting a message in a memory circuit. Some embodiments include transmitting the first data signal frame in full duplex mode after declaring a duplex mismatch. Some embodiments include, after declaring a duplex mismatch, transmitting the first data signal frame when receiving one of the second data signal frames after receiving a predetermined amount of data in one of the second data signal frames one. Some embodiments include transmitting the first data signal frame in full duplex mode when a duplex mismatch is declared after transmitting one of the first data signal frames.

In general, in one aspect, the present invention provides a computer program executable on a processor, comprising: instructions for causing a first data signal frame to be transmitted in a full duplex mode over a communication channel, wherein the second data signal a frame received by the communication channel; and an instruction for declaring a duplex mismatch when one or both of the following conditions occur: the second data signal frame is sent when one of the first data signal frames is transmitted A CRC error is detected in one of the segments, or a segment of one of the second data signal frames is received; and wherein the duplex mismatch indicates that a half-duplex mode is used for the second data signal frame.

In some embodiments, the instructions for declaring the duplex mismatch include instructions for performing at least one of a plurality of actions including: setting a flag and transmitting a message in a memory circuit. Some embodiments include instructions for causing the first data signal frame to be transmitted in full duplex mode after declaring a duplex mismatch. Some embodiments include means for causing the first to be received when one of the second data signal frames is received after receiving a predetermined amount of data in one of the second data signal frames after declaring a duplex mismatch The instruction of one of the data signal boxes. Some embodiments include instructions for causing the first data signal frame to be transmitted in full duplex mode in response to declaring a duplex mismatch after transmitting one of the first data signal frames.

The following figures and descriptions give details of one or more implementations. Other features will be apparent from the description and drawings, and claims.

The inventors found that what is known as "duplex mismatch" is far more common than expected. The performance of a link with duplex mismatch can greatly degrade performance in the best case, and in the worst case it can cause port stalling problems.

The IEEE standard that supports Category 3, 5, and 5e (CAT) twisted pair cables is quite prone to duplex mismatches in its development. Initially, the only twisted-pair Ethernet standard was 10BASE-T, which was completely half-duplex using a hub. Network performance may be improved by supporting full-duplex communication, but full-duplex mechanisms are only allowed when both sides of the link indicate that they can support full-duplex mode. This mechanism is called auto-negotiation.

Since, for example, 10BASE-T hubs do not support auto-negotiation, rules have been developed to ensure interoperability with existing devices. One such rule states that if the link partner does not auto-negotiate, the local port must use half-duplex mode. This rule ensures backward compatibility with the original 10BASE-T hub.

With the development of technology, Fast Ethernet (IEEE 100BASE-TX) has become the standard. Similarly, the first batch of Fast Ethernet devices used to interconnect computers are also half-duplex Fast Ethernet hubs. These hubs are less expensive than switches (with full-duplex capability), and Fast Ethernet is standardized so that these hubs do not require auto-negotiation. The mechanism that allows these hubs to be established without auto-negotiation is called "parallel detect." By checking for idle speed patterns that are seen on the link, parallel detection allows the link to be chained at the correct speed (10 or 100 megabits per second), even if the link partner does not auto-negotiate.

Even though auto-negotiation is well defined in the IEEE standard, its complexity is still worrying that not all devices can auto-negotiate correctly. To address these interoperability concerns, the IEEE standard also allows 埠 to be forced into specific speed and duplex modes. This "back door" became quite useful because interoperability issues emerged early in auto-negotiation.

Each of these rules played a role when they were worked out, but when they were put together, it caused a problem of duplex mismatch. For example, some older devices may require forced speed and duplex mode due to auto-negotiating interoperability issues. Many network administrators remember this requirement and force speed and duplex on some newer devices for this reason or to try to get the best performance. In either case, optimal performance is a desirable goal, so when the duplex mode is forced, it is generally forced to full-duplex mode.

When forced to connect to auto-negotiation, the link will be established and the packet will flow, so the link appears to be working properly. However, due to the IEEE standard, auto-negotiation will adopt the half-duplex mode. In fact, the performance of the cockroach is greatly reduced, and the problem is not obvious.

Table 1 shows the six possible combinations of speed and duplex modes on a 10/100 link and the effective bit rate for file downloads using TCP/IP. Most network administrators only consider the first four entries in the table, where no duplex mismatch occurs, so it is good practice to force 埠 to 100 megabit speed and full duplex mode. However, if the coercion of the link partner is also enforced (which is a frequent occurrence), the effective bit rate of the link is actually less than the properly configured 10 megabit half-duplex link.

Table 1

Embodiments of the present invention provide techniques for correcting duplex mismatch at both ends of a link that suffers from duplex mismatch. According to some embodiments, the half-duplex end of the link can detect that the other end of the link is in full-duplex mode by detecting late and/or later collisions, and can correct duplex by changing to full-duplex mode. Mismatch. According to some embodiments, the full duplex end of the link may detect that the other end of the link is in a half-double by one or more techniques including detecting a loop redundancy check (CRC) error and a signal frame segmentation. Work mode, and can correct the duplex mismatch by changing to half-duplex mode. In some embodiments, a device operating in full-duplex mode that detects duplex mismatch can be forced to one or more very late collisions, and a half-duplex link partner can be detected, for example, using the techniques disclosed herein. The chance of duplexing does not match and changes to full-duplex mode, thus solving the duplex mismatch. If the link partner does not change to full-duplex mode, the device changes to half-duplex mode to resolve the duplex mismatch.

1 shows a communication system 100 that includes a network device 102 capable of detecting and correcting a duplex mismatch while in a half-duplex mode, in accordance with a preferred embodiment of the present invention. Network device 102 can be implemented as a switch, router, network interface controller (NIC), and the like. Network device 102 includes at least one port 104 for communicating with another network device 106 over communication channel 108. The network device 102 also includes a duplex mismatch circuit 110 for declaring a duplex mismatch, as described in more detail below. In some embodiments, all or part of the duplex mismatch circuit 110 is implemented in the 埠 104. The UI 104 includes a collision detection circuit 112 for detecting a collision on the communication channel 108, a duplex mode circuit 116 for changing the UI 104 from a half duplex mode to a full duplex mode, and a memory circuit 118.

2 shows a process 200 for the network device 102 of FIG. 1 in accordance with a preferred embodiment of the present invention. If the link between network devices 102 and 106 is established using auto-negotiation (step 202), process 200 is complete (step 204) because there is no duplex mismatch. Otherwise, 埠 104 enters half-duplex mode (step 206) and determines if there is a duplex mismatch, i.e., whether network device 106 is in full duplex mode, as described below. The port 104 of the network device 102 transmits the data signal frame to the network device 106 in the half duplex mode via the communication channel 108 (step 208). Because the 埠 104 is in the half-duplex mode, if the network device 102 and the network device 106 are simultaneously transmitting on the communication channel 108, a collision will occur, and the collision will be detected by the collision detection circuit 112, for example, according to conventional techniques.

When no conflict is detected (step 210), 埠 104 selects another data signal box (step 212) and transmits the signal box via communication channel 108 (continue to step 208). But when the conflict detection circuit 112 detects a collision (step 210), the duplex mismatch circuit 110 determines whether a duplex mismatch has occurred (step 216).

In some embodiments, the duplex mismatch circuit 110 determines that a duplex mismatch has occurred when, for example, a predetermined number of late collisions have occurred within a predetermined time interval. A late collision according to the IEEE 802 standard is a collision that occurs after a threshold amount of data in the signal frame has been transmitted. For example, late conflicts in IEEE 802 have been used to determine when the network's collision domain is too large. According to IEEE Standard 802.3, any collision that occurs after the 64th byte of the signal box is considered a late collision. Therefore, the minimum signal frame size of the Ethernet signal frame is set to 64 bytes. When the collision domain is too large, the network device sending the signal frame may not be able to detect the collision before the signal frame has been sent, so the signal frame may be mistakenly assumed to be successfully sent. Therefore, late conflicts are defined so that oversized collision domains can be detected and corrected. In an excessively large conflict domain, late conflicts typically occur at byte 65 or 66, and the likelihood of its occurrence decreases as the byte count increases. In fact, late conflicts in oversized collision domains are rare because they only occur when two or more stations at or near the end of the collision domain attempt to send a signal frame at the same time.

In these embodiments, the duplex mismatch circuit 110 determines whether a duplex mismatch should be declared by determining if the late collision rate (the number of late collisions during the predetermined time interval) exceeds a predetermined threshold rate (step 216). For example, 1,000 late collisions in a 10 second span may be sufficient to declare a duplex mismatch, especially if the system administrator has previously defined that the network device 102 is not connected to a large collision domain. Of course, other thresholds and time intervals can also be used.

In some embodiments, the duplex mismatch circuit 110 determines that a duplex mismatch has occurred when a "very late" collision occurs. Modern networks generally do not use large collision domains because they are typically built using full-duplex switches instead of half-duplex hubs. Embodiments of the present invention use these late conflicts for different purposes: detecting duplex mismatch. Although the threshold data amount defining the late collision may be set to the size of the collision domain of the communication channel 108, it is preferably set to a certain multiple of the size, for example by defining a very late collision as occurring in the signal frame. The collision after 256 bytes is set to be 4 times the count of late collisions (ie, after 64 bytes). Any such "late" conflict cannot be the result of a slightly oversized conflict domain, so it can only be an indication of a duplex mismatch. Various embodiments employ one or both of these techniques (i.e., use late and/or later conflicts) to determine if a duplex mismatch has occurred.

If duplex mismatch circuit 110 determines that a duplex mismatch has not occurred (step 216), then 104 transmits the data signal block again after a certain time interval (continue to step 208).

However, if the duplex mismatch circuit 110 determines that a duplex mismatch has occurred (step 216), the duplex mismatch circuit 110 asserts a duplex mismatch (step 218). In this case, declaring the duplex mismatch indicates that the network device 106 is in full duplex mode. The duplex mismatch circuit 110 can take one or more actions to declare a duplex mismatch. For example, the duplex mismatch circuit 110 can set an appropriate flag in a Management Information Base (MIB) stored in the memory circuit 118. As another example, duplex mismatch circuit 110 can send a message to a system administrator. In some embodiments, duplex mode circuit 116 changes 埠 104 to full duplex mode after declaring a duplex mismatch (step 220). Process 200 is then complete (step 222).

3 illustrates a communication system 300 that includes a network device 302 capable of detecting and correcting a duplex mismatch while in full duplex mode, in accordance with a preferred embodiment of the present invention. Network device 302 can be implemented as a switch, router, network interface controller (NIC), or the like. Network device 302 includes at least one port 304 for communicating with another network device 306 over communication channel 308. Network device 302 also includes a duplex mismatch circuit 310 for declaring a duplex mismatch, as described in more detail below. The UI 304 includes a CRC error detection circuit 312 for detecting a CRC error in the received signal frame and a segmentation detection circuit 316 for detecting a segment of the signal frame. The 埠 304 includes a duplex mode circuit 318 for changing the 埠 304 from a full duplex mode to a half duplex mode, a memory circuit 320, and a collision forcing circuit 322 for forcing a collision on the communication channel 308.

4 shows a process 400 for the network device 302 of FIG. 3 in accordance with a preferred embodiment of the present invention. If the link between network devices 302 and 306 is established using auto-negotiation (step 402), process 400 is complete (step 404) because there is no possibility of a duplex mismatch. If the link between network devices 302 and 306 is not established using auto-negotiation (step 402), and 埠 304 is not forced into full-duplex mode (step 406), process 400 is complete (step 404). Otherwise, process 400 determines if there is a duplex mismatch, i.e., whether network device 306 is in a half duplex mode.

In order to prevent the network devices 302, 306 from simultaneously attempting to switch to the duplex mode (because they all operate in accordance with embodiments of the present invention), the network device 302 gives the network device 306 a switch pair before changing its own duplex mode. The time of the mode is as follows.

Thus, port 304 of network device 302 receives the data signal frame from network device 306 via communication channel 308 (step 408). The CRC error detection circuit 312 detects any CRC errors in the received signal frame (step 410), such as an error occurring when the 埠 304 begins to transmit a signal frame, which may indicate that a collision on the communication channel 308 is destroying the received signal frame. In some embodiments, when a CRC error is detected, 埠 304 begins transmitting a signal frame preamble before receiving the 64th byte in the next signal box entering 埠304. This results in the reception and detection of the segment at 埠 304, as described below.

Segment detection circuit 314 detects the segmentation of the received signal frame (step 412). Because no segmentation is used in full-duplex mode, the presence of segments on communication channel 308 indicates that network device 306 is operating in a half-duplex mode.

The duplex mismatch circuit 310 determines whether a duplex mismatch should be declared based on one or more conditions detected by the network administrator for the configuration of the feature, the segmentation detection circuit 314, and the CRC error detection circuit 312 (step 414). . In this case, declaring a duplex mismatch indicates that network device 306 is in a half-duplex mode.

If a duplex mismatch should be declared (step 414), the duplex mismatch circuit 110 declares a duplex mismatch (step 416). The duplex mismatch circuit 310 can take one or more actions to declare a duplex mismatch. For example, the duplex mismatch circuit 310 can set an appropriate flag in a Management Information Base (MIB) stored in the memory circuit 320. As another example, duplex mismatch circuit 310 can send a message to a network administrator.

If the duplex mismatch circuit 310 does not assert a duplex mismatch (step 414), then the buffer 304 continues to receive the data signal box (continue to step 408). But if the duplex mismatch circuit 310 declares a duplex mismatch (step 416), in some embodiments, the duplex mode circuit 318 changes the 埠 304 to a half duplex mode (step 418). Process 400 then completes (step 424). However, when network device 306 operates in accordance with FIG. 2, network device 306 may change its duplex mode to full duplex when 埠 304 changes its duplex mode to half duplex, again causing duplex mismatch .

In other embodiments, if the duplex mismatch circuit 310 declares a duplex mismatch (step 416), the conflict enforcement circuit 322, for example, passes the signal frame after receiving a predetermined amount of data in the signal frame being received. Sending a signal frame or at least a preamble portion of the signal frame to force one or more very late collisions on the communication channel 308 (step 420), thereby giving the network device 306 a very late collision and changing the duplex mode, for example, according to the techniques described above. The opportunity for full duplex mode.

The duplex mismatch circuit 310 then monitors the communication channel 308 again to detect if another duplex mismatch has occurred, for example, according to the techniques described above (step 422). If the duplex mismatch circuit 310 does not detect a duplex mismatch (step 422) (as would be the case if the network device 306 has changed the duplex mode to full duplex mode), the process 400 continues with step 408. But if duplex mismatch circuit 310 detects another duplex mismatch (step 422), duplex mode circuit 318 changes 埠 304 to half-duplex mode (step 418). Process 400 then completes (step 424).

Embodiments of the invention may be implemented in digital electronic circuitry, computer hardware, firmware, software, or combinations thereof. The apparatus of the present invention can be implemented in a computer program product tangibly embodied in a machine readable storage device for execution by a programmable processor; the method steps of the present invention can be performed by a programmable processor executing an instruction program for The input data is manipulated and an output is generated to perform the functions of the present invention. The present invention can be advantageously implemented in one or more computer programs executable on a programmable system, the programmable system comprising: at least one programmable processor coupled to receive and transmit Data and instructions to the data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level programming language or object-oriented programming language, or implemented in assembly or machine language as needed; and in any case, the language can be a compiled or interpreted language . Suitable processors include, by way of example, both general and special purpose microprocessors. In general, the processor will receive instructions and data from a read-only memory circuit and/or a random access memory circuit. In general, the computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks, and optical disks. Storage devices suitable for tangibly including computer program instructions and data include all forms of non-volatile memory circuits including, for example, semiconductor memory circuit devices such as EPROM, EEPROM, and flash memory circuit devices; magnetic sheets, such as internal Hard disk and removable disk; magneto-optical disk; and CD-ROM disk. Any of the above devices may be supplemented by an ASIC (Dedicated Integrated Circuit) or incorporated in an ASIC.

Several implementations of the invention have been described above. It should be understood, however, that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are also within the scope of the appended claims.

100. . . Communication Systems

102. . . Network device

104. . . port

106. . . Network device

108. . . Communication channel

110. . . Duplex mismatch circuit

112. . . Conflict detection circuit

116. . . Duplex mode circuit

118. . . Memory circuit

200, 400. . . process

202, 204, 206, 208, 210, 212, 216, 218, 220, 222, 402, 404, 406, 408, 410, 412, 414, 416, 420, 422, 424. . . step

300. . . Communication Systems

302. . . Network device

304. . . port

306. . . Network device

308. . . Communication channel

310. . . Duplex mismatch circuit

312. . . Error detection circuit

314. . . Segmentation detection circuit

316. . . Auto-negotiation detection circuit

318. . . Duplex mode circuit

320. . . Memory circuit

322. . . Conflict enforcement circuit

1 shows a communication system including a network device capable of detecting and correcting a duplex mismatch while in a half-duplex mode, in accordance with a preferred embodiment of the present invention.

2 illustrates a process for the network device of FIG. 1 in accordance with a preferred embodiment of the present invention.

3 illustrates a communication system including a network device capable of detecting and correcting duplex mismatches while in full duplex mode, in accordance with a preferred embodiment of the present invention.

4 illustrates a process for the network device of FIG. 3 in accordance with a preferred embodiment of the present invention.

100. . . Communication Systems

102. . . Network device

104. . . port

106. . . Network device

108. . . Communication channel

110. . . Duplex mismatch circuit

112. . . Conflict detection circuit

116. . . Duplex mode circuit

118. . . Memory circuit

Claims (22)

A duplex mismatch detecting device includes: a first signal frame for transmitting data through a communication channel and a second signal frame for receiving data, wherein the buffer includes: a collision detecting circuit, configured to detect the a collision between the signal frame and the second signal frame on the communication channel; and a duplex mismatch circuit for declaring a duplex mismatch when: the communication channel is established without attempting to automatically Negotiating, the system is in a half-duplex mode, and the conflict detection circuit detects a very late conflict involving one of the first signal frames, wherein the very late collision occurs in the first signal frame After the predetermined amount of data has been sent in one, and wherein the duplex mismatch indication: for the second signal frame, the full duplex mode is used. The duplex mismatch detecting device according to claim 1, wherein the predetermined amount of data is selected according to a size of a collision domain of the communication channel. The duplex mismatch detecting apparatus according to claim 1, wherein the predetermined amount of data is selected according to a multiple of a size of a collision domain of the communication channel. The duplex mismatch detecting device of claim 1, wherein the duplex mismatch circuit declares the duplex mismatch by performing at least one or both of the following actions: in a memory circuit Set the flag and send the message. The duplex mismatch detecting device according to claim 1, wherein the 埠 further includes: a duplex mode circuit, when the duplex mismatch circuit declares that the duplex does not match, The chirp changes from the half duplex mode to the full duplex mode. A network device comprising the duplex mismatch detecting device according to claim 1, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE Standard 802.3, 802.11 , 802.11a, 802.11b, 802.11g, 802.11n, 802.16, and 802.20. A network device comprising the duplex mismatch detection device of claim 1, wherein the network device comprises one of a switch, a router, and a network interface controller. A duplex mismatch detection method includes: a first signal frame for transmitting data through a communication channel of a network device; and a second signal frame for receiving data; detecting the first signal frame and the second signal frame Conflicts between the communication channels; and declaring a duplex mismatch when: the communication channel is established without attempting auto-negotiation, the system is in half-duplex mode, and the involved a very late conflict of one of the first signal frames, wherein the very late conflict occurs after a predetermined amount of data has been transmitted in one of the first signal frames, and wherein the duplex mismatch indication: The second signal box, full duplex mode is used. The duplex mismatch detection method according to claim 8, wherein the predetermined amount of data is selected according to a size of a collision domain of the communication channel. The duplex mismatch detection method of claim 8, wherein the predetermined amount of data is selected according to a multiple of a size of a collision domain of the communication channel. The duplex mismatch detection method of claim 8, wherein the declaring the duplex mismatch includes performing at least one of: setting a flag in a memory circuit; and Send a message. The duplex mismatch detection method of claim 8, wherein the method further comprises: after declaring the duplex mismatch, transmitting the first signal frame in the full duplex mode. A duplex mismatch detecting apparatus includes: at least one port for transmitting a first data signal frame in a full duplex mode through a communication channel and receiving a second data signal frame through the communication channel, wherein the at least one device includes One or both of the following circuits: a loop redundancy check (CRC) error detecting circuit for detecting a CRC error in the second data signal frame; and a segment detecting circuit for detecting the second data Segmentation of a signal frame; a duplex mismatch circuit for declaring a duplex mismatch when one or more of the following conditions occur: the CRC error detection circuit is transmitting the first data signal frame in the at least one And detecting, by one of the second data signal frames, a CRC error, and the segment detecting circuit detects a segment of one of the second data signal frames, wherein the duplex mismatch indication: a half duplex mode is used for the second data signal frame; and a collision forcing circuit for responding to the duplex mismatch circuit to declare a duplex mismatch when the second data is received Receiving one of the second data signal frames after the predetermined amount of data in one of the number boxes, causing the at least one frame to send one of the first data signal frames to give the transmitter of the second data signal frame The opportunity to change the duplex mode to full duplex mode. The duplex mismatch detecting device of claim 13, wherein the duplex mismatch circuit declares the duplex mismatch by performing at least one or both of the following actions: Set flags and send messages in the memory circuit. The duplex mismatch detecting device according to claim 13, wherein the 埠 further includes: a duplex mode circuit, when the duplex mismatch circuit declares the duplex mismatch, The chirp changes from a full duplex mode to a half duplex mode. The duplex mismatch detecting device of claim 13, wherein the at least one 埠 further comprises: a duplex mode circuit, configured to: when the conflict forcing circuit causes the at least one 埠 to send the When the duplex mismatch circuit declares a duplex mismatch after one of the first data signal frames, the at least one chirp is changed from the full duplex mode to the half duplex mode. A network device comprising the duplex mismatch detecting device according to claim 13, wherein the network device follows at least one of a plurality of standards including the following standards: IEEE Standard 802.3, 802.11 , 802.11a, 802.11b, 802.11g, 802.11n, 802.16, and 802.20. A network device comprising the duplex mismatch detection device of claim 13, wherein the network device comprises one of a switch, a router, and a network interface controller. A duplex mismatch detection method includes: transmitting a first data signal frame in a full duplex mode through a communication channel and receiving a second data signal frame through the communication channel; declaring duplex when one or more of the following occurs Matching: detecting a CRC error in one of the second data signal frames when transmitting one of the first data signal frames, and receiving a segment of one of the second data signal frames, wherein the double Work mismatch indication: for the second data signal frame, a half duplex mode is used; and after declaring a duplex mismatch, receiving after receiving a predetermined amount of data in one of the second data signal frames Sending, by one of the second data signal frames, one of the first data signal frames, and giving the second data signal The box's transmitter changes the duplex mode to the full-duplex mode. The duplex mismatch detection method of claim 19, wherein the declaring the duplex mismatch comprises performing at least one of a plurality of actions including: setting a flag in a memory circuit and Send a message. The duplex mismatch detection method of claim 19, further comprising: transmitting the first signal frame in the full duplex mode after declaring the duplex mismatch. The method for detecting a duplex mismatch according to claim 19, further comprising: when the duplex is not matched after transmitting one of the first signal frames, in the full duplex mode Send the first signal frame.