TWI462419B - Neural static switch - Google Patents

Neural static switch Download PDF

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TWI462419B
TWI462419B TW102100690A TW102100690A TWI462419B TW I462419 B TWI462419 B TW I462419B TW 102100690 A TW102100690 A TW 102100690A TW 102100690 A TW102100690 A TW 102100690A TW I462419 B TWI462419 B TW I462419B
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power generation
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TW201429098A (en
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洪穎怡
魏彥泓
蔡宜廷
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中原大學
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Description

類神經式靜態開關Neurostatic static switch

本發明係關於一種類神經式靜態開關,尤指一種結合小波轉換處理以及自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組,以控制開關斷開與連結之靜態開關。The present invention relates to a neurological static switch, and more particularly to a static switch that combines wavelet transform processing and an Adaptive Network-Based Fuzzy Inference System (ANFIS) module to control switch disconnection and connection. .

近年來,大氣中溫室氣體的濃度屢創新高,聯合國世界氣象組織(World Meteorological Organization;WMO)在2011年報告指出,在過去15年中,有13年是史上最溫暖的年份,此種異常的暖化現象除了導致海平面高度上升,造成物種生態失衡更帶來急遽的氣候變遷,面對氣候變遷帶來的嚴峻考驗,全球已開發國家已計畫於2050至2060年間,逐步達成溫室氣體零排放的目標,至於開發中國家,也希望能於2020年達成溫室氣體排放零成長。In recent years, the concentration of greenhouse gases in the atmosphere has reached record highs. The World Meteorological Organization (WMO) reported in 2011 that 13 years have been the warmest year in history in the past 15 years. In addition to causing the sea level to rise, the warming phenomenon causes the ecological imbalance of the species to bring about rapid climate change. In the face of the severe test brought about by climate change, the developed countries in the world have planned to gradually achieve greenhouse gas zero between 2050 and 2060. The target of emissions, as for developing countries, also hopes to achieve zero growth in greenhouse gas emissions by 2020.

其中,隨著氣候的急遽變化,夏季多颱的台灣勢必成為這波氣候暖化下的受害者,台灣除了有氣候上的不利因素外,位處於環太平洋的地震帶,是典型的板塊碰撞下所產生的島嶼,因而成為地震頻繁的國家。以日本311大地震來說,東京電力公司福島核電廠因為地震所引發的海嘯,導致反應爐爆炸,核能外洩的重大意外,事故發生當下造成大規模的停電,截至目前三分之一電力來自核能發電的日本仍在執行節電措施,對民眾及產業造成直接的衝 擊。Among them, with the rapid changes in the climate, Taiwan in the summer is bound to become a victim of this wave of climate warming. In addition to the climatic disadvantages, Taiwan is located in the seismic belt around the Pacific Ocean, which is a typical plate collision. The islands produced have become countries with frequent earthquakes. In the case of Japan's 311 earthquake, the Tokyo Electric Power Company's Fukushima nuclear power plant caused a large-scale power outage due to the tsunami caused by the earthquake, causing a large-scale power outage. As a result, one-third of the power comes from the current power generation. Nuclear power generation in Japan is still implementing power-saving measures, causing direct rush to the people and industry. hit.

台灣跟日本一樣採行集中式發電(Centralized Generation;CG),以火力發電廠、核能發電廠以及水力發電廠居多。倘若遭遇天災、地震或人為操作不當,發生大規模的停電事故,恐對以科技業為重的台灣造成嚴重的損失,進而衝擊台灣的經濟以及競爭力。因此,具有節能環保議題並講求以區域為基礎的微電網便孕育而生。Taiwan, like Japan, adopts Centralized Generation (CG), which is dominated by thermal power plants, nuclear power plants and hydroelectric power plants. In the event of a natural disaster, an earthquake or improper human operation, a large-scale power outage will occur, which will cause serious losses to Taiwan, which is heavily targeted by the technology industry, and thus impact Taiwan’s economy and competitiveness. Therefore, a micro-grid with energy-saving and environmental protection issues and a regional-based approach will emerge.

微電網是由負載、靜態開關、分散式電源、電力設備及自動監控等系統所構成,其中分散式電源以太陽能、風力、燃料電池以及微渦輪發電機系統較為常見。微電網一般都併接在配電系統中,為了避免電力潮流於電力系統中流竄而造成潮流改變,通常不提供電能進入配電網中。而當配電電網或微電網內發生故障,由靜態開關偵測後,使微電網與配電系統切離,並運行於孤島運行模式,可避免受到故障方所造成的擾動,讓系統繼續維持穩定運作。Microgrids are composed of systems such as loads, static switches, decentralized power supplies, power equipment, and automatic monitoring. Dispersed power supplies are more common in solar, wind, fuel cell, and micro-turbine generator systems. Microgrids are generally connected in the distribution system. In order to avoid the power flow change caused by the current flow in the power system, power is usually not supplied into the distribution network. When a fault occurs in the power distribution grid or the microgrid, the static power switch detects the microgrid and the power distribution system, and runs in the island operation mode to avoid the disturbance caused by the faulty party and keep the system stable. .

然而,現有之靜態開關仍是以機械式為主,其在偵測到故障後仍需藉由人力將其切換,此外,機械式的靜態開關佔有相當的空間且其建構成本較大,因此現有之靜態開關仍有待改善。However, the existing static switch is still mainly mechanical, and it needs to be switched by manpower after detecting a fault. In addition, the mechanical static switch occupies a considerable space and its construction is large, so the existing The static switch still needs to be improved.

有鑒於在習知技術中,現有之靜態開關仍為機械式靜態開關,其所佔之空間較大且建構成本較為昂貴,因此現 有之靜態開關仍有待改善。緣此,本發明之主要目的係提供一種類神經式靜態開關,其係藉由小波轉換處理以及自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組的處理,而控制開關斷開與連結,藉以達到開關自動切換之效。In view of the prior art, the existing static switch is still a mechanical static switch, which occupies a large space and is relatively expensive to construct. Some static switches still need to be improved. Accordingly, the main object of the present invention is to provide a neural-like static switch which is controlled by wavelet transform processing and adaptive network-based fuzzy inference system (ANFIS) module. The switch is disconnected and connected to achieve automatic switch switching.

本發明為解決習知技術之問題,所採用之必要技術手段係提供一種類神經式靜態開關,係用以連結於一微電網系統以及一大眾供電系統,微電網系統係包含至少一發電區域系統,大眾供電系統係電性連接於類神經式靜態開關,且發電區域系統係經由一主匯流排而電性連接於類神經式靜態開關,並且包含至少一發電模組,類神經式靜態開關包含一第一小波轉換模組、一第二小波轉換模組、至少一自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組、一處理模組以及一開關。第一小波轉換模組係用以偵測主匯流排之一電壓之狀況,用以依據電壓之狀況進行一小波轉換處理,藉以輸出一第一偵測信號。第二小波轉換模組係用以偵測主匯流排之一電流之狀況,用以依據電流之狀況進行小波轉換處理,藉以輸出一第二偵測信號。The present invention solves the problems of the prior art, and the necessary technical means is to provide a neural-like static switch for connecting to a micro-grid system and a mass power supply system, and the micro-grid system includes at least one power generation area system. The mass power supply system is electrically connected to the neural-like static switch, and the power generation area system is electrically connected to the neuro-static static switch via a main bus bar, and includes at least one power generation module, and the neural-like static switch includes A first wavelet transform module, a second wavelet transform module, at least one Adaptive Network-Based Fuzzy Inference System (ANFIS) module, a processing module and a switch. The first wavelet transform module is configured to detect a voltage of a main bus bar for performing a wavelet transform process according to the voltage condition, thereby outputting a first detection signal. The second wavelet conversion module is configured to detect a current of the main bus, and perform wavelet conversion processing according to the current condition to output a second detection signal.

ANFIS模組係電性連接於第二小波轉換模組,用以接收並處理第二偵測信號,藉以輸出一類神經處理信號。處理模組係電性連接於第一小波轉換模組以及ANFIS模 組,用以接收第一偵測信號以及類神經處理信號,藉以依據第一偵測信號以及類神經處理信號輸出一控制信號。開關係電性連接於處理模組,用以依據控制信號而切換,藉以使微電網系統連結或斷開於大眾供電系統。The ANFIS module is electrically connected to the second wavelet transform module for receiving and processing the second detection signal, thereby outputting a type of neural processing signal. The processing module is electrically connected to the first wavelet transform module and the ANFIS module The group is configured to receive the first detection signal and the neural-like processing signal, thereby outputting a control signal according to the first detection signal and the neural-like processing signal. The open relationship is electrically connected to the processing module for switching according to the control signal, so that the microgrid system is connected or disconnected from the mass supply system.

較佳者,上述之類神經式靜態開關中,ANFIS模組包含至少一指數位址處理器以及至少一查表處理器,用以處理第二偵測信號。另外,第一小波轉換模組以及第二小波轉換模組包含複數個信號處理器,該些信號處理器係為一轉換器、一加法器以及一乘法器;第一小波轉換模組以及第二小波轉換模組包含複數個電性連接於該些信號處理器之低通濾波器以及高通濾波器中之其中一者。此外,包含一信號處理模組,信號處理模組係電性連接於第二小波轉換模組以及ANFIS模組,用以對第二偵測信號進行一巴賽瓦處理。Preferably, in the above-mentioned neural static switch, the ANFIS module includes at least one exponent address processor and at least one look-up table processor for processing the second detection signal. In addition, the first wavelet transform module and the second wavelet transform module comprise a plurality of signal processors, wherein the signal processors are a converter, an adder, and a multiplier; the first wavelet transform module and the second The wavelet transform module includes a plurality of low pass filters electrically connected to the signal processors and a high pass filter. In addition, a signal processing module is included, and the signal processing module is electrically connected to the second wavelet transform module and the ANFIS module for performing a bussew processing on the second detection signal.

較佳者,上述之類神經式靜態開關中,處理模組更包含一或(OR)邏輯電路以及一和(AND)邏輯電路,OR邏輯電路係電性連接於ANFIS模組,而AND邏輯電路電性連接於第一小波轉換模組以及OR邏輯電路,OR邏輯電路係接收第二偵測信號而輸出一邏輯信號至AND邏輯電路,藉以使AND邏輯電路依據第一偵測信號以及邏輯信號而輸出控制信號。另外,發電模組係為一太陽能發電模組、一風力發電模組、一微渦輪機發電模組中之一者。Preferably, in the above-mentioned neurostatic static switch, the processing module further comprises an OR logic circuit and an AND logic circuit, the OR logic circuit is electrically connected to the ANFIS module, and the AND logic circuit is Electrically connected to the first wavelet transform module and the OR logic circuit, the OR logic circuit receives the second detection signal and outputs a logic signal to the AND logic circuit, so that the AND logic circuit is based on the first detection signal and the logic signal. Output control signals. In addition, the power generation module is one of a solar power generation module, a wind power generation module, and a micro turbine power generation module.

相較於習知技術,由於本發明所提供之類神經式靜態開關係經由小波轉換處理以及自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組的處理,進而達到自動控制開關斷開與連結之效果,且上述之處理均係藉由晶片實現,進而將傳統機械式的靜態開關改良為晶片式之靜態開關,因此可進一步降低所佔之空間以及建構成本,且其偵測故障與否而自動關閉之準確度相當高,因此解決了習知技術所具有之問題。Compared with the prior art, the neural static open relationship provided by the present invention is automatically processed through the wavelet transform processing and the adaptive network-based fuzzy inference system (ANFIS) module. Controlling the effect of the switch being disconnected and connected, and the above processing is realized by the wafer, thereby improving the conventional mechanical static switch into a wafer type static switch, thereby further reducing the occupied space and the construction cost, and The accuracy of automatically shutting down when detecting a fault is quite high, thus solving the problems of the prior art.

本發明所採用的具體實施例,將藉由以下之實施例及圖式作進一步之說明。The specific embodiments of the present invention will be further described by the following examples and drawings.

由於本發明所提供之類神經式靜態開關中,其組合實施方式不勝枚舉,故在此不再一一贅述,僅列舉一較佳實施例來加以具體說明。Since the combination of the embodiments of the neural static switch provided by the present invention is numerous, it will not be repeated here, and only a preferred embodiment will be specifically described.

請一併參閱第一圖以及第一A圖,第一圖係顯示本發明較佳實施例之類神經式靜態開關連結於大眾公電系統與微電網系統之第一方塊示意圖,第一A圖係顯示本發明較佳實施例之類神經式靜態開關連結於大眾公電系統與微電網系統之第二方塊示意圖。如圖所示,類神經式靜態開關1係用以連結於一微電網系統2以及一大眾供電系統3,微電網系統2係包含三發電區域系統21、22、23,大眾供電系統3係電性連接於類神經式靜態開關1,且發電區域系統21、22、23係經由一主匯流排4而電性連接於 類神經式靜態開關1,且發電區域系統21、22、23包含至少一發電模組。Please refer to FIG. 1 and FIG. 1A together. The first figure shows a first block diagram of a neural static switch connected to a mass public power system and a micro grid system according to a preferred embodiment of the present invention. A second block diagram showing a neural static switch of the preferred embodiment of the present invention coupled to a mass public electrical system and a microgrid system is shown. As shown, the neuro-static static switch 1 is used to connect to a micro-grid system 2 and a mass supply system 3, the micro-grid system 2 includes three power generation regional systems 21, 22, 23, and the mass-powered system 3 is electrically Connected to the neuro-static static switch 1, and the power generation area systems 21, 22, 23 are electrically connected to each other via a main bus bar 4 The neurostatic static switch 1 and the power generation area system 21, 22, 23 comprise at least one power generation module.

其中,發電模組例如是一太陽能發電模組、一風力發電模組或一微渦輪機發電模組,在其他實施例中,例如可為潮汐發電模組或地熱發電模組等較具環保之發電模組。以本發明較佳實施例而言,發電區域系統21包含一太陽能發電模組211以及一微渦輪機發電模組212;發電區域系統22包含一太陽能發電模組221以及風力發電模組222、223;發電區域系統23包含一太陽能發電模組231以及一微渦輪機發電模組232,當然,在其他實施例中不限於上述配置。另外,大眾供電系統3係為台灣電力公司(台電)所構成之供電系統。The power generation module is, for example, a solar power generation module, a wind power generation module, or a micro turbine power generation module. In other embodiments, for example, a tidal power generation module or a geothermal power generation module can generate environmentally friendly power generation. Module. In a preferred embodiment of the present invention, the power generation area system 21 includes a solar power generation module 211 and a micro-turbine power generation module 212; the power generation area system 22 includes a solar power generation module 221 and wind power generation modules 222, 223; The power generation area system 23 includes a solar power generation module 231 and a micro turbine power generation module 232. Of course, it is not limited to the above configuration in other embodiments. In addition, the Volkswagen Power Supply System 3 is a power supply system consisting of the Taiwan Power Company (Taiwan Power).

具體而言,請進一步參閱第一A圖,其係實務上配電之簡要示意圖,大眾供電系統3係分別經由匯流排5以及匯流排6而電性連接至類神經式靜態開關1,且大眾供電系統3所供應之電壓值例如是69kV,且在經由匯流排5時會經由一變壓器(圖未示)變壓而成為11.4kV,並且再經由匯流排6時,再經由一變壓器(圖未示)的變壓而成為380V,也就是說,匯流排5之電壓係為11.4kV,而匯流排6之電壓係為380V,其中,上述僅為舉例,在其他實施例可為其他值,其係視各國電力標準而定,特此敘明。Specifically, please refer to FIG. 1A, which is a schematic diagram of power distribution in practice. The Volkswagen power supply system 3 is electrically connected to the neuro-static static switch 1 via the bus bar 5 and the bus bar 6, respectively, and the mass supply is The voltage value supplied by the system 3 is, for example, 69 kV, and when it passes through the bus bar 5, it is transformed into a 11.4 kV via a transformer (not shown), and when passing through the bus bar 6, it is further passed through a transformer (not shown). The voltage is 380V, that is, the voltage of the bus bar 5 is 11.4kV, and the voltage of the bus bar 6 is 380V, wherein the above is only an example, and other values may be other embodiments. Depending on the national power standards, it is hereby stated.

而發電區域系統21之太陽能發電模組211以及一微渦輪機發電模組212係經由匯流排7,再經由主匯流排4電性連接至類神經式靜態開關1;發電區域系統22之太陽能 發電模組221與風力發電模組222、223係經由匯流排9,再經由匯流排8與主匯流排4而電性連接至類神經式靜態開關1;發電區域系統23之太陽能發電模組231以及微渦輪機發電模組232係經由匯流排10,再經由匯流排8與主匯流排4而電性連接至類神經式靜態開關1,其中,繼續以上述電壓值為例的話,主匯流排4與匯流排7、8、9、10之電壓值都為380V,當然,此配置乃係視實務上之調整而有變化,不限於上述。The solar power generation module 211 and the micro-turbine power generation module 212 of the power generation area system 21 are electrically connected to the neuro-static static switch 1 via the bus bar 7 and via the main bus bar 4; The power generation module 221 and the wind power generation modules 222 and 223 are electrically connected to the neuro-static static switch 1 via the bus bar 9 and via the bus bar 8 and the main bus bar 4; the solar power generation module 231 of the power generation area system 23 And the micro-turbine power generation module 232 is electrically connected to the neuro-static static switch 1 via the bus bar 10 and then via the bus bar 8 and the main bus bar 4, wherein, if the voltage value is continued, the main bus bar 4 is continued. The voltage values of the bus bars 7, 8, 9, and 10 are both 380 V. Of course, this configuration varies depending on the actual adjustment, and is not limited to the above.

請一併參閱第二圖至第四B圖,第二圖係顯示本發明較佳實施例之類神經式靜態開關之方塊示意圖,第三圖係顯示本發明較佳實施例之第一小波轉換模組之示意圖,第四圖係顯示本發明較佳實施例之ANFIS模組之示意圖,第四A圖係顯示本發明較佳實施例之指數位址處理器之示意圖,第四B圖係顯示本發明較佳實施例之查表處理器之示意圖。Please refer to the second to fourth B drawings. The second figure shows a block diagram of a neural static switch according to a preferred embodiment of the present invention, and the third figure shows the first wavelet transform of the preferred embodiment of the present invention. 4 is a schematic diagram showing an ANFIS module according to a preferred embodiment of the present invention, and FIG. 4A is a schematic diagram showing an exponential address processor according to a preferred embodiment of the present invention, and FIG. 4B is a schematic diagram showing A schematic diagram of a look-up table processor in accordance with a preferred embodiment of the present invention.

如圖所示,類神經式靜態開關1包含一第一小波轉換模組11、一第二小波轉換模組12、一信號處理模組13、四自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組14、14a、14b與14c、處理模組15以及開關16。第一小波轉換模組11係電性連接於主匯流排4,第二小波轉換模組12亦電性連接於主匯流排4,信號處理模組13係電性連接於第二小波轉換模組12。As shown, the neuro-static static switch 1 includes a first wavelet transform module 11, a second wavelet transform module 12, a signal processing module 13, and a four adaptive neuro-fuzzy inference system (Adaptive Network-Based). Fuzzy Inference System; ANFIS) modules 14, 14a, 14b and 14c, processing module 15 and switch 16. The first wavelet transform module 11 is electrically connected to the main bus bar 4, the second wavelet transform module 12 is also electrically connected to the main bus bar 4, and the signal processing module 13 is electrically connected to the second wavelet transform module. 12.

其中,第一小波轉換模組11以及第二小波轉換模組 12之內部電路結構都相同,在此僅以第一小波轉換模組11之內部電路結構為例,請進一步參閱第三圖,第一小波轉換模組11包含複數個信號處理器111以及複數個低通濾波器112。在本發明較佳實施例中,第一小波轉換模組11所包含之信號處理器111有轉換器(上排之Z-1 )、乘法器(中排之a*b)以及加法器(下排之a+b);而低通濾波器112係電性連接於上述之信號處理器111,其用以作為信號處理器111中乘法器之輸入,且乘法器之輸出作為上述信號處理器111之加法器之輸入,其中,上述第一小波轉換模組11之內部電路結構僅為其中之一種實施例而已,其係視實務上之調整,因此不限於上述以及圖中所示。The internal circuit structures of the first wavelet transform module 11 and the second wavelet transform module 12 are the same. Here, only the internal circuit structure of the first wavelet transform module 11 is taken as an example. Please refer to the third figure. A wavelet conversion module 11 includes a plurality of signal processors 111 and a plurality of low pass filters 112. In the preferred embodiment of the present invention, the signal processor 111 included in the first wavelet transform module 11 has a converter (Z -1 in the upper row), a multiplier (a*b in the middle row), and an adder (in the lower row). The low-pass filter 112 is electrically connected to the signal processor 111 described above, and is used as an input of a multiplier in the signal processor 111, and the output of the multiplier is used as the signal processor 111. The input of the adder, wherein the internal circuit structure of the first wavelet transform module 11 is only one of the embodiments, which is based on the actual adjustment, and thus is not limited to the above and shown in the figure.

舉例而言,在其他實施例中,上述之低通濾波器112可因實務上之調整而將其替代為高通濾波器,具體而言,如下表所示,在本發明較佳實施例之濾波器類型可藉由係數的調整手段而達到變換之效,下表順序0至7係分別代表第三圖由左至右之濾波器。For example, in other embodiments, the low pass filter 112 described above may be replaced by a high pass filter due to practical adjustments. Specifically, as shown in the following table, the filter in the preferred embodiment of the present invention The type of the device can be transformed by the adjustment means of the coefficients. The following sequence 0 to 7 represent the left-to-right filter of the third figure.

ANFIS模組14、14a、14b與14c電性連接於信號處理模組13,其中,ANFIS模組14、14a、14b與14c分別係模擬大眾供電系統3(網外)、發電區域系統21、發電區域系統22以及發電區域系統23,且ANFIS模組14、14a、14b與14c內部電路結構均相同,本發明較佳實施例中僅以ANFIS模組14之內部電路結構為例,請進一步參閱第四圖,ANFIS模組14包含三指數位址處理器141(圖中僅標示一個)、三查表處理器142(圖中僅標示一個)、一規則處理模組143、一結論推論處理模組144、以及一輸出處理模組145,而查表處理器142係電性連接於指數位址處理器141,規則處理模組143係電性連接於查表處理器142,結論推論處理模組144係電性連接於規則處理模組143,輸出處理模組145係電性連接於結論推論處理模組144。The ANFIS modules 14, 14a, 14b and 14c are electrically connected to the signal processing module 13, wherein the ANFIS modules 14, 14a, 14b and 14c respectively simulate the mass supply system 3 (outside the network), the power generation area system 21, and the power generation. The regional system 22 and the power generation area system 23, and the internal circuit structures of the ANFIS modules 14, 14a, 14b, and 14c are the same. In the preferred embodiment of the present invention, only the internal circuit structure of the ANFIS module 14 is taken as an example. In the four-figure, the ANFIS module 14 includes a three-index address processor 141 (only one is shown), a three-table processor 142 (only one is shown), a rule processing module 143, and a conclusion inference processing module. 144, and an output processing module 145, the look-up table processor 142 is electrically connected to the exponent address processor 141, the rule processing module 143 is electrically connected to the look-up table processor 142, the conclusion inference processing module 144 The system is electrically connected to the rule processing module 143, and the output processing module 145 is electrically connected to the conclusion inference processing module 144.

其中,ANFIS模組14係應用自適應類神經模糊理論所構成之模組,其主要包含了輸入層、規則層、結論推論層以及輸出層,具體而言,指數位址處理器141以及查表處理器142即為上述之輸入層,規則處理模組143則為規則層,結論推論處理模組144則為結論推論層,輸出處理模組145則為輸出層,且指數位址處理器141、查表處理器142、規則處理模組143、結論推論處理模組144、以及輸出處理模組145都是以邏輯電路來實現。此外,在此值得一提的是,本發明較佳實施例之ANFIS模組14並不包 含傳統自適應類神經模糊理論所包含之正規化層,特此敘明。The ANFIS module 14 is a module composed of an adaptive neuro-fuzzy theory, which mainly includes an input layer, a rule layer, a conclusion inference layer, and an output layer. Specifically, the exponent address processor 141 and the lookup table The processor 142 is the input layer, the rule processing module 143 is a rule layer, the conclusion inference processing module 144 is a conclusion inference layer, the output processing module 145 is an output layer, and the exponent address processor 141, The lookup table processor 142, the rule processing module 143, the conclusion inference processing module 144, and the output processing module 145 are all implemented by logic circuits. In addition, it is worth mentioning that the ANFIS module 14 of the preferred embodiment of the present invention does not include The normalization layer included in the traditional adaptive neuro-fuzzy theory is hereby described.

請再進一步參閱第四A圖,在本發明較佳實施例之指數位址處理器141中,指數位址處理器141包含一減法器14101、一減法器14102、一比較器14103、一比較器14104、一多工器14105、一多工器14106、一除法器14107、一乘法器14108、一轉換器14109、一減法器14110。減法器14101係用以接收一「x_end」以及一「x_start」之輸入;減法器14102係電性連接於多工器14106,比較器14103係電性連接於多工器14105,並且用以接收該「x_end」以及一「x」之輸入;比較器14104係電性連接於多工器14106,並且用以接收該「x_start」以及該「x」之輸入;多工器14106係用以接收該「x_start」、比較器14104以及多工器14105之輸出作為輸入;除法器14107係電性連接於減法器14101、14102而將其輸出作為輸入;乘法器14108係電性連接於除法器14107,並且用以接收其輸出以及一常數「256」作為輸入;轉換器14109係電性連接於乘法器14108而接收其輸出作為輸入,且其輸出係為「index_int」;減法器14110係電性連接於乘法器14108以及轉換器14109,用以接收其輸出作為輸入而輸出「index_dec」,其中,上述之電路結構僅為本發明較佳實施例之結構,在其他實施例可為其他結構,特此敘明。For further reference to FIG. 4A, in the exponent address processor 141 of the preferred embodiment of the present invention, the exponent address processor 141 includes a subtractor 14101, a subtractor 14102, a comparator 14103, and a comparator. 14104, a multiplexer 14105, a multiplexer 14106, a divider 14107, a multiplier 14108, a converter 14109, and a subtractor 14110. The subtracter 14101 is configured to receive an input of "x_end" and an "x_start"; the subtractor 14102 is electrically connected to the multiplexer 14106, and the comparator 14103 is electrically connected to the multiplexer 14105, and is configured to receive the "x_end" and an input of "x"; the comparator 14104 is electrically connected to the multiplexer 14106 and is configured to receive the input of the "x_start" and the "x"; the multiplexer 14106 is configured to receive the "" The output of x_start", comparator 14104, and multiplexer 14105 is input; the divider 14107 is electrically coupled to the subtractors 14101, 14102 and has its output as an input; the multiplier 14108 is electrically coupled to the divider 14107, and The converter 14109 is electrically connected to the multiplier 14108 and receives its output as an input, and its output is "index_int"; the subtractor 14110 is electrically connected to the multiplier. 14108 and a converter 14109 for receiving an output thereof as an input and outputting "index_dec", wherein the above circuit structure is only the structure of the preferred embodiment of the present invention, and other embodiments may be other junctions. This is hereby stated.

請再進一步參閱第四B圖,在本發明較佳實施例之查表處理器142中,查表處理器142包含一儲存器14201、 一比較器14202、一加法器14203、一多工器14204、一儲存器14205、一減法器14206、一加法器14207、一比較器14208、一乘法器14209、一多工器14210。儲存器14201係用以接收上述該「index_int」之輸入,且儲存器14201係儲存有查表對應關係表,且此查表對應關係表包含了輸入資料以及歸屬函數的對應關係,而儲存器14201可為一般具有記憶功能之記憶體;比較器14202係用以接收該「index_int」以及一常數「255」之輸入;加法器14203係用以接收該「index_int」以及一常數「1」之輸入;多工器14204係電性連接於比較器14202以及加法器14203,並且用以接收其輸出以及該常數「255」作為輸入;儲存器14205係電性連接於多工器14204,用以接收其輸出作為輸入,且儲存器14205係儲存有查表對應關係表,且此查表對應關係表包含了輸入資料以及歸屬函數的對應關係,而儲存器14205可為一般具有記憶功能之記憶體;減法器14206係電性連接於儲存器14201以及儲存器14205,用以接收其輸出作為輸入;加法器14207係電性連接於儲存器14201以及乘法器14209,用以接收其輸出作為輸入;比較器14208係電性連接於減法器14206,用以接收其輸出以及一常數「0」作為輸入;乘法器14209係電性連接於減法器14206,用以接收其輸出以及上述該「index_dec」作為輸入;多工器14210係電性連接於儲存器14201、加法器14207以及比較器14208,用以接收其輸出作為輸入,且其輸出係為「MF」,其中,上述之電路結構僅為本發明較佳實施 例之結構,在其他實施例可為其他結構,特此敘明。For further reference to FIG. 4B, in the look-up table processor 142 of the preferred embodiment of the present invention, the look-up table processor 142 includes a memory 14201, A comparator 14202, an adder 14203, a multiplexer 14204, a memory 14205, a subtractor 14206, an adder 14207, a comparator 14208, a multiplier 14209, and a multiplexer 14210. The storage unit 14201 is configured to receive the input of the “index_int”, and the storage unit 14201 stores a lookup table correspondence table, and the lookup table correspondence table includes the correspondence between the input data and the attribution function, and the storage 14201 The comparator 14202 is configured to receive the input of the "index_int" and a constant "255"; the adder 14203 is configured to receive the input of the "index_int" and a constant "1"; The multiplexer 14204 is electrically connected to the comparator 14202 and the adder 14203, and is configured to receive the output and the constant "255" as an input; the storage 14205 is electrically connected to the multiplexer 14204 for receiving the output thereof. As an input, the storage 14205 stores a lookup table correspondence table, and the lookup table correspondence table includes the correspondence between the input data and the attribution function, and the storage 14205 can be a memory having a memory function generally; the subtractor The 14206 is electrically connected to the storage 14201 and the storage 14205 for receiving the output thereof as an input; the adder 14207 is electrically connected to the storage 14201 And a multiplier 14209 for receiving its output as an input; a comparator 14208 is electrically coupled to the subtractor 14206 for receiving its output and a constant "0" as an input; the multiplier 14209 is electrically coupled to the subtractor 14206 The multiplexer 14210 is electrically connected to the memory 14201, the adder 14207, and the comparator 14208 for receiving the output as an input, and the output thereof is "". MF", wherein the above circuit structure is only a preferred embodiment of the present invention The structure of the example can be other structures in other embodiments, and is hereby described.

其中,請繼續一併參閱第二圖至第四B圖,第一小波轉換模組11係用以偵測主匯流排4之一電壓之狀況,藉以依據電壓之狀況進行一小波轉換處理,據以輸出一第一偵測信號S1,且第二小波轉換模組係用以偵測主匯流排4之一電流之狀況,用以依據電流之狀況進行小波轉換處理,藉以輸出一第二偵測信號S2。具體而言,上述之小波轉換處理係經由一離散小波轉換(Discrete Wavelet Transform;DWT)之演算而降低原連續小波轉換(Continuous Wavelet Transform;CWT)演算之複雜度,且本發明較佳實施例之小波轉換處理係經由如第三圖所示之架構,而將上述電壓與電流之資料分解為三層(階)的高頻信號,也就是說第一偵測信號S1以及第二偵測信號S2包含了三層的高頻信號。然而,實務上亦可分解為四層、五層甚至更多,因此不限於上述之三層。此外,上述第一偵測信號S1以及上述第二偵測信號S2係為數位邏輯之信號,其係為「1」或「0」,舉例而言,在本發明較佳實施例中,當偵測到主匯流排4之電壓以及電流為異常時,第一偵測信號S1以及第二偵測信號S2係為「1」,而正常則為「0」。In addition, please continue to refer to the second to fourth B diagrams, the first wavelet conversion module 11 is used to detect the voltage of one of the main bus bars 4, thereby performing a wavelet conversion process according to the voltage condition. The first detection signal S1 is output, and the second wavelet conversion module is configured to detect a current of the main bus 4 for performing wavelet conversion processing according to the current condition, thereby outputting a second detection. Signal S2. Specifically, the wavelet transform processing described above reduces the complexity of the original continuous wavelet transform (CWT) calculus by a discrete wavelet transform (DWT) calculus, and the preferred embodiment of the present invention The wavelet transform processing decomposes the data of the voltage and current into three layers (order) of high frequency signals via the architecture as shown in the third figure, that is, the first detection signal S1 and the second detection signal S2. Contains three layers of high frequency signals. However, the practice can also be decomposed into four layers, five layers or even more, and thus is not limited to the above three layers. In addition, the first detection signal S1 and the second detection signal S2 are digital logic signals, which are “1” or “0”. For example, in the preferred embodiment of the present invention, When the voltage and current of the main bus 4 are abnormal, the first detection signal S1 and the second detection signal S2 are "1", and the normal is "0".

信號處理模組13係用以對第二偵測信號S2進行一巴賽瓦處理,具體而言,上述巴賽瓦處理係依據巴賽瓦能量定理對第二偵測信號S2進行處理,藉以得知第二偵測信號S2中各層小波係數能量的關係,亦即在小波轉換處理之時域以及頻域上可進行信號的能量分割,進而可利用此一小 波一至三階的能量特徵數值作為鑑別正常或者異常之信號的依據。倘使搜集各式正常或異常之一至三階能量特徵數據與這些數據所映射之正常與異常之發生點,便可利用這些數據來逹成ANFIS之訓練學習進而達成一至三階小波能量特徵的模糊歸屬函數之參數。The signal processing module 13 is configured to perform a Baccarat process on the second detection signal S2. Specifically, the Bassava process processes the second detection signal S2 according to the Basseva energy theorem. Knowing the relationship between the energy of the wavelet coefficients of each layer in the second detection signal S2, that is, the energy division of the signal in the time domain and the frequency domain of the wavelet transform processing, and thus utilizing the small The energy characteristic values of the first to third order waves are used as the basis for identifying signals of normal or abnormal. If you collect the normal or abnormal one-to-third-order energy feature data and the normal and abnormal occurrence points mapped by these data, you can use these data to form ANFIS training and learn the fuzzy attribution of the first to third-order wavelet energy features. The parameters of the function.

ANFIS模組14、14a、14b與14c用以接收並處理第二偵測信號S2,藉以輸出一類神經處理信號S3、S3a、S3b與S3c,具體而言,其係先經由指數位址處理器141對第二偵測信號S2所包含之該歸屬函數,利用內插法以及多項是逼近法求出指數位址,且如第四A圖所示,「x」表ANFIS模組14、14a、14b與14c的輸入,「x_end」以及「x_start」分別表示上下限值。在演算的第一步,其係藉由比較器14103以及比較器14104判斷「x」是否超出上下限值,再將減法器14101所運算「x」與「x_start」的差值,除以減法器14102所運算「x_end」以及「x_start」的差值,進而得知此時指數所對應於查表法的位址,且在本發明較佳實施例係將上述之查表法分割為256份,因此需藉由乘法器14108將除法器14107之輸出乘上「256」,最後再經由轉換器14109以及減法器14110將指數位址分割為整數以及小數,即第四A圖之「index_int」為整數,而「index_dec」為小數。The ANFIS modules 14, 14a, 14b and 14c are configured to receive and process the second detection signal S2, thereby outputting a type of neural processing signals S3, S3a, S3b and S3c, in particular, via the exponent address processor 141. For the attribution function included in the second detection signal S2, the exponential address is obtained by interpolation and a plurality of approximation methods, and as shown in FIG. 4A, the "x" table ANFIS modules 14, 14a, 14b With the input of 14c, "x_end" and "x_start" indicate the upper and lower limits, respectively. In the first step of the calculation, the comparator 14103 and the comparator 14104 determine whether the "x" exceeds the upper and lower limits, and divide the difference between the "x" and the "x_start" calculated by the subtractor 14101 by the subtractor. 14102 calculates the difference between "x_end" and "x_start", and further knows that the index corresponds to the address of the look-up table method, and in the preferred embodiment of the present invention, the above-mentioned table look-up method is divided into 256 copies. Therefore, the output of the divider 14107 is multiplied by "256" by the multiplier 14108, and finally the index address is divided into integers and decimals via the converter 14109 and the subtractor 14110, that is, the "index_int" of the fourth A picture is an integer. , and "index_dec" is a decimal.

在產生上述結果後,係輸入至查表處理器142,進一步而言,其係經由儲存器14201所內建之查表對應關係表而實現查表法,進而由對應關係中得出歸屬函數,首先, 其係先藉由比較器14202判斷「index_int」是否為上限值,假若為上限值則直接藉由儲存器14201輸出查表結果;若非上限值的話,藉由加法器14203對「index_int」加上「1」以後,再經由多工器14204輸入至儲存器14205而得到下一筆位址的查表結果,接著再將此結果與儲存器14201之輸出結果,經由減法器14206進行相減而得差值,最後再經由乘法器14209與使差值與「index_dec」相乘,並接著再與儲存器14201之輸出結果相加後而得到歸屬函數「MF」。此外,在此值得一提的是,第四圖中ANFIS模組14內之指數位址處理器141以及查表處理器142各有三個,其主要係經過小波分解後之第二偵測信號有三層高頻信號,此三層高頻信號係分別輸入至三指數位址處理器141,即第一層、第二層以及第三層分別輸入至三個指數位址處理器141。After the above result is generated, it is input to the look-up table processor 142. Further, it is implemented by the look-up table correspondence table built in the memory 14201, and the attribution function is obtained from the corresponding relationship. First of all, It is first determined by the comparator 14202 whether "index_int" is the upper limit value. If it is the upper limit value, the result of the look-up table is directly output by the memory 14201; if it is not the upper limit value, the "index_int" is added by the adder 14203. After adding "1", it is input to the memory 14205 via the multiplexer 14204 to obtain the result of the lookup of the next address, and then the result is compared with the output of the memory 14201 via the subtractor 14206. The difference is obtained, and finally the multiplier 14209 is multiplied by the difference value and "index_dec", and then added to the output of the memory 14201 to obtain the attribution function "MF". In addition, it is worth mentioning that the index address processor 141 and the look-up table processor 142 in the ANFIS module 14 in the fourth figure each have three, which are mainly after the wavelet decomposition, the second detection signal has three The layer high frequency signals are respectively input to the three index address processor 141, that is, the first layer, the second layer, and the third layer are respectively input to the three index address processors 141.

接著,經由上述處理後之信號再經由規則處理模組143、結論推論處理模組144以及輸出處理模組145的處理而輸出類神經處理信號S3、S3a、S3b與S3c至處理模組15。其中,在本發明較佳實施例中,類神經處理信號S3、S3a、S3b與S3c係為「1」或「0」之信號,其在規則處理模組143、結論推論處理模組144以及輸出處理模組145的處理過程中,係藉由實際上的明確計算而產生「1」或「0」之信號,在其他實施例中,可藉由比較之方式產生,例如是大於一預設之閾值則設定輸出為「1」,反之為「0」。Then, the neural processing signals S3, S3a, S3b, and S3c are output to the processing module 15 via the processed signals through the processing of the rule processing module 143, the conclusion inference processing module 144, and the output processing module 145. In the preferred embodiment of the present invention, the neural-like processing signals S3, S3a, S3b, and S3c are signals of "1" or "0", which are in the rule processing module 143, the conclusion inference processing module 144, and the output. During the processing of the processing module 145, the signal of "1" or "0" is generated by the actual explicit calculation. In other embodiments, the signal may be generated by comparison, for example, greater than a preset. The threshold sets the output to "1" and vice versa.

其中,在或邏輯電路151接收上述類神經處理信號 S3、S3a、S3b與S3c後,係立即輸出邏輯信號S4,且此邏輯信號S4亦為「1」或「0」,而和邏輯電路152則依據第一偵測信號S1以及邏輯信號S4輸出控制信號S5,藉以使開關16依據控制信號S5而切換,藉以使微電網系統2連結或斷開於大眾供電系統3。舉例而言,假若主匯流排4之電壓之狀況為故障而異常時,第一偵測信號S1係為1,而此時ANFIS模組14b所模擬之發電區域系統22出現異常,且其於ANFIS模組14、14a與14c為正常時,其或邏輯電路151係輸出「1」之邏輯信號S4,此時,和邏輯電路152即輸出「1」之控制信號S5,進而使開關16得知有異常狀況發生而斷開於大眾供電系統3,進一步來說,更可進一步選擇將發電區域系統22斷開於大眾供電系統3,僅剩發電區域系統21與23連結於大眾供電系統3。Wherein the OR logic circuit 151 receives the above-mentioned neural processing signal After S3, S3a, S3b and S3c, the logic signal S4 is immediately output, and the logic signal S4 is also "1" or "0", and the sum logic circuit 152 is controlled according to the first detection signal S1 and the logic signal S4. The signal S5 is used to switch the switch 16 according to the control signal S5, so that the microgrid system 2 is connected or disconnected to the mass supply system 3. For example, if the voltage of the main bus 4 is abnormal and the fault is abnormal, the first detection signal S1 is 1, and the power generation area system 22 simulated by the ANFIS module 14b is abnormal, and it is in the ANFIS. When the modules 14, 14a and 14c are normal, the logic circuit 151 outputs a logic signal S4 of "1". At this time, the logic circuit 152 outputs a control signal S5 of "1", thereby making the switch 16 known. The abnormal condition occurs and is disconnected from the mass power supply system 3. Further, the power generation area system 22 is further selected to be disconnected from the mass power supply system 3, and only the remaining power generation area systems 21 and 23 are connected to the mass supply system 3.

為了使本發明敘述較為清楚,請一併參閱第一A圖以及第五圖至第五I圖,第五圖至第五I圖係顯示本發明較佳實施例之類神經式靜態開關之模擬結果示意圖。如圖所示,在本發明較佳實施例之模擬狀況中,其係設定風速9m/s(風力發電模組222約為11kW、風力發電模組223約為1.5kW),日照強度為600W/m2 (發電區域系統21之太陽能發電模組211約為17kW,發電區域系統22之太陽能發電模組221約為6kW,發電區域系統23之太陽能發電模組231約為30kW),而發電區域系統21之微渦輪機發電模組212輸出固定功率為37kW,總負載(圖未示)之總負載量為100%(150kW)之情況下, 微電網系統2採主從控制法(習知技術,不再贅述),假設在2秒時於匯流排7發生對稱三相短路故障時,類神經式靜態開關1偵測到故障(其均已於上敘述)後,在1/4週期後將大眾供電系統3斷開,並且將發電區域系統21所電性連接之匯流排7切離斷開,藉以使太陽能發電模組211、微渦輪機發電模組212與負載(圖未示)斷開,進而使微電網系統2由並聯大眾供電系統3模式切換為孤島模式(習知技術,不再贅述),進而以發電區域系統23之微渦輪機發電模組232作為主電源,且其變流器(圖未示)採電壓-頻率之控制,而其餘太陽能發電模組221、風力發電模組222、223以及太陽能發電模組231採P-Q控制(習知技術,不再贅述)。In order to make the description of the present invention clearer, please refer to the first A figure and the fifth figure to the fifth I picture. The fifth figure to the fifth I figure show the simulation of the neural static switch of the preferred embodiment of the present invention. The result is schematic. As shown in the figure, in the simulation situation of the preferred embodiment of the present invention, the wind speed is set to 9 m/s (the wind power generation module 222 is about 11 kW, the wind power generation module 223 is about 1.5 kW), and the sunshine intensity is 600 W/ m 2 (the solar power generation module 211 of the power generation area system 21 is about 17 kW, the solar power generation module 221 of the power generation area system 22 is about 6 kW, and the solar power generation module 231 of the power generation area system 23 is about 30 kW), and the power generation area system The micro-turbine power generation module 212 of 21 outputs a fixed power of 37 kW, and the total load (not shown) is 100% (150 kW). The micro-grid system 2 adopts the master-slave control method (known technology, no As described again, assuming that a symmetrical three-phase short-circuit fault occurs in the busbar 7 at 2 seconds, the neuro-static static switch 1 detects a fault (which is described above), and then powers the Volkswagen after 1/4 cycle. The system 3 is disconnected, and the busbar 7 electrically connected to the power generation area system 21 is disconnected and disconnected, so that the solar power generation module 211 and the micro turbine power generation module 212 are disconnected from the load (not shown), thereby The microgrid system 2 is switched from the parallel mass supply system 3 mode to the island mode ( Known technology, no longer described in detail, and further, the micro-turbine power generation module 232 of the power generation area system 23 is used as the main power source, and the converter (not shown) adopts voltage-frequency control, and the remaining solar power generation modules 221, The wind power generation modules 222 and 223 and the solar power generation module 231 adopt PQ control (known techniques, and will not be described again).

其中,如第五圖至第五B圖所示,其係經小波轉換處理後微電網系統2之主匯流排4電壓之第一層、第二層與第三層之高頻信號,顯然地,可發現第五A圖對於偵測主匯流排4發生對稱三相短路故障最為明顯,在此值得一提的是,在本發明較佳實施例中,上述明顯之對比係以第一層、第二層與第三層之高頻信號波形圖做進一步對比,其可知第二層的振幅是較為小的,因此可知其最為明顯,當然,在其他實施例中,若振幅相較於其餘二圖而較大的話,亦可判斷較為明顯,特此敘明。Wherein, as shown in FIG. 5 to FIG. 5B, the high frequency signals of the first layer, the second layer and the third layer of the main bus bar 4 voltage of the microgrid system 2 after the wavelet conversion process are apparently It can be found that the fifth A picture is most obvious for detecting the symmetrical three-phase short circuit fault of the main bus bar 4. It is worth mentioning that in the preferred embodiment of the present invention, the above obvious contrast is the first layer, The second layer and the third layer are further compared with the high-frequency signal waveform diagram. It can be seen that the amplitude of the second layer is relatively small, so that it is most obvious. Of course, in other embodiments, if the amplitude is compared with the other two If the figure is large, it can be judged more obviously, and it is hereby stated.

進一步來說,第五C圖係表示出發電區域系統23之微渦輪機發電模組232輸出功率;第五D圖係表示發電區域系統21之微渦輪機發電模組212輸出功率;第五E圖 係表示風力發電模組222與223之輸出功率,且曲線100表風力發電模組222之輸出功率,曲線200則為風力發電模組223之輸出功率;第五F圖係表示太陽能發電模組211、221與231之輸出功率,曲線300為發電區域系統23之太陽能發電模組231之輸出功率,曲線400為發電區域系統21之太陽能發電模組211之輸出功率,曲線500為發電區域系統22之太陽能發電模組221之輸出功率;第五G圖係表示主匯流排4之電壓;第五H圖係表示主匯流排4之頻率;第五I圖係表示主匯流排4之電流。Further, the fifth C diagram shows the output power of the microturbine power generation module 232 of the power generation area system 23; the fifth D diagram shows the output power of the micro turbine power generation module 212 of the power generation area system 21; The output power of the wind power generation modules 222 and 223 is represented, and the output power of the wind power generation module 222 is represented by the curve 100, the output power of the wind power generation module 223 is represented by the curve 200, and the solar power generation module 211 is represented by the fifth F diagram. The output power of 221 and 231, the curve 300 is the output power of the solar power generation module 231 of the power generation area system 23, the curve 400 is the output power of the solar power generation module 211 of the power generation area system 21, and the curve 500 is the power generation area system 22 The output power of the solar power generation module 221; the fifth G diagram represents the voltage of the main busbar 4; the fifth H diagram represents the frequency of the main busbar 4; and the fifth diagram I represents the current of the main busbar 4.

其中,發電區域系統23之微渦輪機發電模組232在匯流排7未發生對稱三相短路故障前以P-Q控制輸出功率37kW,當故障發生時則採電壓-頻率控制,而在匯流排7切離後,其他太陽能發電模組221、風力發電模組222、223以及太陽能發電模組231之總發電量約為48.5kW,總負載量為90kW,且為了維持微電網系統2內的供需平衡,發電區域系統23之微渦輪機發電模組232的輸出功率調整至45kW。Wherein, the microturbine power generation module 232 of the power generation area system 23 controls the output power by 37 kW before the symmetrical three-phase short-circuit fault occurs in the bus bar 7, and when the fault occurs, the voltage-frequency control is adopted, and the bus line 7 is cut off. After that, the total power generation of the other solar power generation modules 221, the wind power generation modules 222, 223, and the solar power generation module 231 is about 48.5 kW, the total load is 90 kW, and power generation is maintained in order to maintain the balance between supply and demand in the microgrid system 2. The output power of the microturbine power generation module 232 of the regional system 23 is adjusted to 45 kW.

據此,由上述以及第五圖至第五I圖可知,當微電網系統2由並聯大眾供電系統3切換為孤島運轉模式時,微電網系統2內的發電模組仍可穩定運行而持續給予電力,且當有其他發電模組跳脫後,作為主電源之發電區域系統23可立即調整輸出功率維持平衡。Accordingly, it can be seen from the above and the fifth to fifth figures that when the microgrid system 2 is switched to the island operation mode by the parallel mass supply system 3, the power generation module in the microgrid system 2 can still be stably operated and continuously given. Power, and when other power generation modules are tripped, the power generation area system 23 as the main power source can immediately adjust the output power to maintain balance.

綜合以上所述,結合小波轉換模組以及ANFIS模組之類神經式靜態開關中,其可推論故障之發電區域系 統,且小波能夠提供時間與頻率之關係以及時間與大小之關係,因此能有效反應故障信號。此外,ANFIS模組所應用之自適應類神經模糊理論具有自我學習之能力,並且可立即處理定性的知識與邏輯推論。另外,其是以小波能量特徵作為輸入,經上述模擬後之結果可知其有相當高的準確度,且由模擬結果可知故障發生的1/4週期後,類神經式靜態開關立即斷開,且此時微電網系統2仍維持有穩定的電壓及頻率,提供負載良好的供電品質。In combination with the above, combined with the wavelet static conversion module and the neural static switch such as the ANFIS module, it can infer the faulty power generation area system. The wavelet can provide the relationship between time and frequency and the relationship between time and size, so it can effectively reflect the fault signal. In addition, the adaptive neuro-fuzzy theory applied by the ANFIS module has self-learning ability and can directly process qualitative knowledge and logical inference. In addition, it is based on the wavelet energy characteristic as input, and the result of the above simulation shows that it has a relatively high accuracy, and it is known from the simulation result that after the 1/4 cycle of the fault occurs, the neural-like static switch is immediately disconnected, and At this time, the microgrid system 2 still maintains a stable voltage and frequency, and provides a good load power quality.

因此,藉由本發明所提供之類神經式靜態開關,經由小波轉換處理以及ANFIS模組的處理,進而達到自動控制開關斷開與連結之效果,且上述之處理均係藉由現場可程式邏輯閘陣列(Field Programmable Gate Array;FPGA)晶片實現,進而將傳統機械式的靜態開關改良為晶片式之靜態開關,因此可進一步降低所佔之空間以及建構成本,且在更換為晶片式之類神經式靜態開關後,其偵測故障與否而自動關閉之準確度仍相當高,因此解決了習知技術所具有之問題。Therefore, by the neural static switch provided by the present invention, the effect of automatically controlling the opening and disconnecting of the switch is achieved through the wavelet transform processing and the processing of the ANFIS module, and the above processing is performed by the field programmable logic gate. The implementation of a Field Programmable Gate Array (FPGA) chip, which in turn improves the conventional mechanical static switch into a chip-type static switch, thereby further reducing the occupied space and the construction cost, and replacing it with a neuron type such as a wafer type. After the static switch, the accuracy of detecting the fault or not and automatically closing is still quite high, thus solving the problems of the prior art.

藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

1‧‧‧類神經式靜態開關1‧‧‧-type neural static switch

11‧‧‧第一小波轉換模組11‧‧‧First Wavelet Conversion Module

111‧‧‧信號處理器111‧‧‧Signal Processor

112‧‧‧低通濾波器112‧‧‧Low-pass filter

12‧‧‧第二小波轉換模組12‧‧‧Second wavelet transform module

13‧‧‧信號處理模組13‧‧‧Signal Processing Module

14、14a、14b、14c‧‧‧ANFIS模組14, 14a, 14b, 14c‧‧‧ ANFIS modules

141‧‧‧指數位址處理器141‧‧‧index address processor

14101、14102‧‧‧減法器14101, 14102‧‧‧ subtractor

14103、14104‧‧‧比較器14103, 14104‧‧‧ comparator

14105、14106‧‧‧多工器14105, 14106‧‧‧Multiplexer

14107‧‧‧除法器14107‧‧‧ divider

14108‧‧‧乘法器14108‧‧‧Multiplier

14109‧‧‧轉換器14109‧‧‧ converter

14110‧‧‧減法器14110‧‧‧Subtractor

142‧‧‧查表處理器142‧‧ ‧ lookup processor

14201‧‧‧儲存器14201‧‧‧Storage

14202‧‧‧比較器14202‧‧‧ comparator

14203‧‧‧加法器14203‧‧‧Adder

14204‧‧‧多工器14204‧‧‧Multiplexer

14205‧‧‧儲存器14205‧‧‧Storage

14206‧‧‧減法器14206‧‧‧Subtractor

14207‧‧‧加法器14207‧‧‧Adder

14208‧‧‧比較器14208‧‧‧ comparator

14209‧‧‧乘法器14209‧‧‧Multiplier

14210‧‧‧多工器14210‧‧‧Multiplexer

143‧‧‧規則處理模組143‧‧‧ rule processing module

144‧‧‧結論推論處理模組144‧‧‧Conclusion inference processing module

145‧‧‧輸出處理模組145‧‧‧Output processing module

15‧‧‧處理模組15‧‧‧Processing module

151‧‧‧或邏輯電路151‧‧‧ or logic circuit

152‧‧‧和邏輯電路152‧‧‧ and logic circuits

16‧‧‧開關16‧‧‧ switch

2‧‧‧微電網系統2‧‧‧Microgrid system

21‧‧‧發電區域系統21‧‧‧Power Generation Area System

211‧‧‧太陽能發電模組211‧‧‧Solar power module

212‧‧‧微渦輪機發電模組212‧‧‧Micro Turbine Power Generation Module

22‧‧‧發電區域系統22‧‧‧Power Generation Area System

221‧‧‧太陽能發電模組221‧‧‧Solar power module

222、223‧‧‧風力發電模組222, 223‧‧‧ wind power generation module

23‧‧‧發電區域系統23‧‧‧Power Generation Area System

231‧‧‧太陽能發電模組231‧‧‧Solar power module

232‧‧‧微渦輪機發電模組232‧‧‧Micro Turbine Power Generation Module

3‧‧‧大眾供電系統3‧‧‧VW Power Supply System

4‧‧‧主匯流排4‧‧‧Main bus

5、6、7、8、9、10‧‧‧匯流排5, 6, 7, 8, 9, 10‧‧ ‧ busbars

100、200、300、 400、500‧‧‧ 曲線100, 200, 300, 400, 500‧‧‧ curve

S1‧‧‧第一偵測信號S1‧‧‧ first detection signal

S2‧‧‧第二偵測信號S2‧‧‧ second detection signal

S3、S3a、S3b、S3c‧‧‧類神經處理信號S3, S3a, S3b, S3c‧‧‧ nerve processing signals

S4‧‧‧邏輯信號S4‧‧‧ logic signal

S5‧‧‧控制信號S5‧‧‧ control signal

第一圖係顯示本發明較佳實施例之類神經式靜態開關連結於大眾公電系統與微電網系統之第一方塊示意圖;第一A圖係顯示本發明較佳實施例之類神經式靜態開關連結於大眾公電系統與微電網系統之第二方塊示意圖;第二圖係顯示本發明較佳實施例之類神經式靜態開關之方塊示意圖;第三圖係顯示本發明較佳實施例之第一小波轉換模組之示意圖;第四圖係顯示本發明較佳實施例之ANFIS模組之示意圖;第四A圖係顯示本發明較佳實施例之指數位址處理器之示意圖;第四B圖係顯示本發明較佳實施例之查表處理器之示意圖;以及第五圖至第五I圖係顯示本發明較佳實施例之類神經式靜態開關之模擬結果示意圖。The first figure shows a first block diagram of a neural static switch connected to a mass public power system and a micro grid system according to a preferred embodiment of the present invention; the first A figure shows a neural static switch according to a preferred embodiment of the present invention. A second block diagram of a public electrical system and a microgrid system; a second block diagram showing a neural static switch of a preferred embodiment of the present invention; and a third diagram showing the first embodiment of the preferred embodiment of the present invention. A schematic diagram of a wavelet transform module; a fourth diagram showing a schematic diagram of an ANFIS module in accordance with a preferred embodiment of the present invention; and a fourth diagram showing a schematic diagram of an index address processor in accordance with a preferred embodiment of the present invention; A schematic diagram showing a look-up table processor of a preferred embodiment of the present invention; and fifth through fifth figures are diagrams showing simulation results of a neural static switch according to a preferred embodiment of the present invention.

1‧‧‧類神經式靜態開關1‧‧‧-type neural static switch

11‧‧‧第一小波轉換模組11‧‧‧First Wavelet Conversion Module

12‧‧‧第二小波轉換模組12‧‧‧Second wavelet transform module

13‧‧‧信號處理模組13‧‧‧Signal Processing Module

14、14a、14b、14c‧‧‧ANFIS模組14, 14a, 14b, 14c‧‧‧ ANFIS modules

15‧‧‧處理模組15‧‧‧Processing module

151‧‧‧或邏輯電路151‧‧‧ or logic circuit

152‧‧‧和邏輯電路152‧‧‧ and logic circuits

16‧‧‧開關16‧‧‧ switch

4‧‧‧主匯流排4‧‧‧Main bus

S1‧‧‧第一偵測信號S1‧‧‧ first detection signal

S2‧‧‧第二偵測信號S2‧‧‧ second detection signal

S3、S3a、S3b、S3c‧‧‧類神經處理信號S3, S3a, S3b, S3c‧‧‧ nerve processing signals

S4‧‧‧邏輯信號S4‧‧‧ logic signal

S5‧‧‧控制信號S5‧‧‧ control signal

Claims (7)

一種類神經式靜態開關,係用以連結於一微電網系統以及一大眾供電系統,該微電網系統係包含至少一發電區域系統,該大眾供電系統係電性連接於該類神經式靜態開關,且該發電區域系統係經由一主匯流排而電性連接於該類神經式靜態開關,並且包含至少一發電模組,該類神經式靜態開關包含:一第一小波轉換模組,係用以偵測該主匯流排之一電壓之狀況,用以依據該電壓之狀況進行一小波轉換處理,藉以輸出一第一偵測信號;一第二小波轉換模組,係用以偵測該主匯流排之一電流之狀況,用以依據該電流之狀況進行該小波轉換處理,藉以輸出一第二偵測信號;至少一自適應類神經模糊推論系統(Adaptive Network-Based Fuzzy Inference System;ANFIS)模組,係電性連接於該第二小波轉換模組,用以接收並處理該第二偵測信號,藉以輸出一類神經處理信號;一處理模組,係電性連接於該第一小波轉換模組以及該自適應類神經模糊推論系統模組,用以接收該第一偵測信號以及該類神經處理信號,藉以依據該第一偵測信號以及該類神經處理信號輸出一控制信號;以及一開關,係電性連接於該處理模組,用以依據該控制信號而切換,藉以使該微電網系統連結或斷開於該大眾供電系 統。 A neuro-static static switch is used for connecting to a micro-grid system and a mass supply system, the micro-grid system comprising at least one power generation system electrically connected to the neural static switch. The power generation area system is electrically connected to the neural static switch via a main bus bar, and includes at least one power generation module. The neural static switch includes: a first wavelet conversion module, which is used for Detecting a voltage of the main bus to perform a wavelet conversion process according to the condition of the voltage, thereby outputting a first detection signal; and a second wavelet conversion module for detecting the main convergence The current of the current is arranged to perform the wavelet transform processing according to the current condition, thereby outputting a second detection signal; at least one Adaptive Network-Based Fuzzy Inference System (ANFIS) module The group is electrically connected to the second wavelet transform module for receiving and processing the second detection signal, thereby outputting a type of neural processing signal; The module is electrically connected to the first wavelet transform module and the adaptive neuro-fuzzy inference system module, for receiving the first detection signal and the neural processing signal, according to the first detection The measurement signal and the neural processing signal output a control signal; and a switch electrically connected to the processing module for switching according to the control signal, so that the micro grid system is connected or disconnected from the mass supply system System. 如申請專利範圍第1項所述之類神經式靜態開關,其中,該ANFIS模組包含至少一指數位址處理器以及至少一查表處理器,用以處理該第二偵測信號。 The neural static switch of claim 1, wherein the ANFIS module comprises at least one index address processor and at least one look-up table processor for processing the second detection signal. 如申請專利範圍第1項所述之類神經式靜態開關,其中,該第一小波轉換模組以及該第二小波轉換模組包含複數個信號處理器,並且包含複數個電性連接於該些信號處理器之低通濾波器以及高通濾波器中之其中一者。 The neural static switch of the first aspect of the invention, wherein the first wavelet transform module and the second wavelet transform module comprise a plurality of signal processors, and the plurality of electrical connectors are electrically connected to the plurality of One of a low pass filter of the signal processor and a high pass filter. 如申請專利範圍第3項所述之類神經式靜態開關,其中,該些信號處理器係為一轉換器、一加法器以及一乘法器。 A neural static switch as described in claim 3, wherein the signal processors are a converter, an adder, and a multiplier. 如申請專利範圍第1項所述之類神經式靜態開關,其中,更包含一信號處理模組,該信號處理模組係電性連接於該第二小波轉換模組以及該ANFIS模組,用以對該第二偵測信號進行一巴賽瓦處理。 The neural static switch of claim 1, further comprising a signal processing module electrically connected to the second wavelet transform module and the ANFIS module. Performing a Bacsay process on the second detection signal. 如申請專利範圍第1項所述之類神經式靜態開關,其中,該處理模組更包含一或(OR)邏輯電路以及一和(AND)邏輯電路,該OR邏輯電路係電性連接於該ANFIS模組,而該AND邏輯電路係電性連接於該第一小波轉換模組以及該OR邏輯電路,該OR邏輯電路係接收該第二偵測信號而輸 出一邏輯信號至該AND邏輯電路,藉以使該AND邏輯電路依據該第一偵測信號以及該邏輯信號而輸出該控制信號。 The neural static switch as described in claim 1, wherein the processing module further comprises an OR logic circuit and an AND logic circuit, wherein the OR logic circuit is electrically connected to the An ANFIS module, wherein the AND logic circuit is electrically connected to the first wavelet conversion module and the OR logic circuit, and the OR logic circuit receives the second detection signal and inputs And generating a logic signal to the AND logic circuit, so that the AND logic circuit outputs the control signal according to the first detection signal and the logic signal. 如申請專利範圍第1項所述之類神經式靜態開關,其中,該發電模組係為一太陽能發電模組、一風力發電模組、一微渦輪機發電模組中之一者。The neural static switch as described in claim 1, wherein the power generation module is one of a solar power generation module, a wind power generation module, and a micro turbine power generation module.
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