TWI462249B - A semiconductor device having a pad - Google Patents

Description

Semiconductor device with pad

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a pad.

A semiconductor device (known as a wafer in the industry) is usually fixed on a printed circuit board and electrically connected to the printed circuit board through wire bonding to supply external electric energy to the semiconductor device through the circuit board. Electrical products such as computers, consumer electronics, or communication products.

Referring to FIG. 1, the current semiconductor device includes a substrate unit 11 and a pad unit 12 for externally connecting the bonding wires.

The substrate unit 11 includes at least one semiconductor element 111, which may be selected from a transistor and a diode. The semiconductor component 111 is operable to generate an electrical signal when receiving electrical energy.

The pad unit 12 includes a pad 121, at least one conductive layer 122 formed under the pad 121 and composed of a metal as a main material, a plurality of isolation layers 123, and a protective layer 124.

The pad 121 is made of metal as a main material and has an outer surface for subsequent wire bonding process. The isolation layer 123 is interposed between the conductive layer 122 and the pad 121, and between the conductive layer 122 and the substrate unit 11; the isolation layer 123 between the conductive layer 122 and the pad 121 has a plurality of A via 125 extending from a top surface of the conductive layer 122 to the pad 121, and an insulating material 126 filled between the connecting bodies 125, and located at the conductive layer 122 and the substrate unit The 11 isolation layers 123 also have a plurality of connecting bodies 125 respectively connecting the bottom surface of the conductive layer 122 and the semiconductor element 111 of the substrate unit 11, and the semiconductor element 111 is electrically connected to the pad unit 12.

Referring to FIG. 2, the solder pad 121 of the semiconductor device is electrically connected to a printed circuit board (not shown) by a bonding wire 13 after the bonding process, and the electric energy from the outside passes through the printed circuit board and the bonding pad. The pad 121 of the cell 12, the connector 125, and the conductive layer 122 are transferred to the semiconductor device 111, and the semiconductor device 111 is activated to provide a path for the semiconductor device 111 to transmit an electrical signal.

However, downward mechanical stress must be applied to the surface of the pad 121 during the wire bonding process, and since the conductive layer 122 is a flat layer, mechanical stress is transmitted to the conductive layer 122 by the connector 125. The conductive layer 122 under the solder pad 121 cannot withstand the mechanical stress to cause deformation and depression, and can no longer continue to stably support the solder pad 121 above it, resulting in the solder pad 121 being prone to cracks or even breakage.

Accordingly, it is an object of the present invention to provide a semiconductor device having a solder pad that is less susceptible to breakage.

Accordingly, the semiconductor device with a pad of the present invention comprises a substrate unit and a pad unit.

The substrate unit includes at least one semiconductor component.

The pad unit is electrically connected to the semiconductor component, and includes a pad having an outer surface of the bonding wire, at least one composite layer formed under the pad, and a plurality of isolation layers, wherein the solder is closest to the solder The composite layer of the pad has a stress-resisting region correspondingly below the outer surface and composed of an insulating material, and a conductive region electrically connecting the semiconductor element and the bonding pad, the layers being respectively sandwiched between the pads a composite layer, and between the substrate units.

The invention has the advantages that the stress resistance zone of the composite layer increases the support strength of the pad unit to avoid deformation of the conductive region in the process of the subsequent bonding wire, thereby reducing the probability of cracks in the pad and improving the overall product. Yield.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 3 and FIG. 4, a first preferred embodiment of the semiconductor device having a pad includes a substrate unit 2 and a pad unit 3, and is electrically connected to the outside through the bonding wire 4.

The substrate unit 2 comprises at least one semiconductor component 21. In the first preferred embodiment, the substrate unit 2 is a semiconductor substrate having a plurality of semiconductor elements 21 integrated in the semiconductor substrate, such as a transistor, a diode, a resistor, and an inductor. And become an integrated circuit (IC). Further, when the present invention is applied to the field of optoelectronics, the substrate unit 2 may be a semiconductor substrate having a plurality of photodiodes. It should be noted that the substrate unit 2 may also include only one semiconductor element 21.

The pad unit 3 includes a pad 31, a composite layer 32 formed under the pad 31, two isolation layers 33, and a protective layer 34.

The pad 31 is made of aluminum as a main material and has an outer surface 311 for subsequent wire bonding process. The outer surface 311 may be circular or polygonal as long as the bonding wires 4 (usually gold wires) of a wire bonding device (not shown) are attached.

The composite layer 32 has a stress resisting region 321 formed of an insulating material, and a conductive region 322 composed of a metal as a main material. The stress resisting region 321 is correspondingly located below the bonding pad 31, and correspondingly The center of the pad 31 extends laterally outwardly. The conductive region 322 extends laterally outward from the periphery of the stress resisting region 321 , and the hardness of the stress resisting region 321 is greater than the hardness of the conductive region 322 .

Preferably, the stress-resistant region 321 is mainly composed of an oxide or a nitride, and is selected from, for example, cerium oxide, cerium nitride, and the like, and may be further doped with an element such as phosphorus or arsenic. The conductive region 322 is composed of a metal as a main material, for example, selected from the group consisting of aluminum, copper, and the like.

One of the two isolation layers 33 is interposed between the bonding pad 31 and the composite layer 32, and has a plurality of vias 331 spaced apart from each other, and a gap filled between the connecting bodies 331. An insulating material 332, and each of the connecting bodies 331 extends from the surface of the conductive region 322 of the composite layer 32 to the bonding pad 31 to connect the conductive region 322 and the bonding pad 31; the other of the two isolation layers 33 Sandwiched between the composite layer 32 and the substrate unit 2, and having a plurality of branches spaced apart from each other and extending from the semiconductor element 21 of the substrate unit 2 to the bottom surface of the conductive region 322 to connect the semiconductor device 21 with the The connecting body 331 of the conductive region 322 and an insulating material 332 filled with a gap of the connecting body 331. Therefore, the bonding pad 31 is electrically connected to the semiconductor element 21 through the connecting body 331 and the conductive region 322.

The protective layer 34 is formed on the pad 31 and surrounds the outer surface 311 of the pad 31, and has an opening 341 for the exposed surface 311 to facilitate subsequent soldering process. Since the outer surface 311 is correspondingly located above the stress resistant region 321, the opening 341 is also correspondingly located above the stress resistant region 321 .

Referring to FIG. 4 and FIG. 5, when the semiconductor device performs a subsequent bonding process for the package, the bonding wire 4 is first inserted into the soldering pin 5 of the bonding wire device, and the end of the bonding wire 4 is heated and melted into a circle. Spherical, after controlling the soldering needle 5 to move over the soldering pad 31, the soldering pin 5 is lowered until the bonding wire 4 contacts the outer surface 311 of the bonding pad 31, and then mechanical stress is applied to weld the molten state. The wire 4 is thermocompression bonded to the outer surface 311 of the pad 31 and coupled to the pad 31. Thereafter, the soldering pin 5 is moved up and moved to the surface of the wire 61 of the lead frame 6 to be connected, and the soldering pin 5 is lowered and lowered in accordance with the foregoing steps, and the bonding wire 4 is matched with the downward mechanical stress. The other end is engaged with the wire 61.

The solder pad 31 of the semiconductor device is electrically connected to the wire 61 of the lead frame 6 after the wire bonding process, and the electric energy from the outside passes through the lead frame 6, the pad 31 of the pad unit 3, the connecting body 331, and the conductive region 322. The electric energy is transmitted to the semiconductor element 21, and the semiconductor element 21 is actuated, and the same as the path through which the semiconductor element 21 transmits the electric signal.

The underlying surface 311 of the bonding pad 31 is the filler of the stress-resistant region 321 of the composite layer 32 and the spacers 33, and the hardness of the stress-resisting region 321 is greater than the hardness of the conductive region 322. In the process of the wire process, the stress-resistant region 321 having a large hardness can withstand the mechanical stress from the welding pin 5 without being deformed, so that the pad 31 located above does not be cracked or broken due to deformation of the underlying composite layer 32, and therefore, The yield at the time of packaging of the first preferred embodiment is also increased synchronously.

It should be noted that, in the wire bonding process, the lower needle position of the welding pin 5 is substantially at the center of the outer surface 311, so that the central portion of the outer surface 311 receives mechanical stress from the welding pin 5 that is larger than the outer surface. The surrounding area of 311 is subjected to mechanical stress from the welding pin 5, and the pad can be maintained in order to comply with the lower limit of the total number of the connecting bodies 331 in the IC design layout rule. The area of the outer surface 311, and the diameter of the opening 341 is greater than the diameter of the stress-resisting region 321 , that is, the diameter of the outer surface 311 is larger than the diameter of the stress-resisting region 321 . The partial connection body 331 of the isolation layer 33 between the composite layer 32 and the bonding pad 31 is correspondingly located in the peripheral region of the opening 341, thereby maintaining the total area of the semiconductor device.

Preferably, the diameter of the stress-resisting region 321 is not more than 95% of the diameter of the opening 341 of the protective layer 34, and is not less than the diameter of the bonding wire 4 formed on the outer surface 311, so that the first preferred The stress resistant region 321 of the embodiment has a better bearing force against mechanical stress.

Referring to FIG. 6, a second preferred embodiment of the present invention is similar to the first preferred embodiment, except that the second preferred embodiment further includes a plurality of layer composite layers 32. In the second preferred embodiment, the composite layer 32 and the three-layer isolation layer 33 comprising two laterally extending layers are illustrated.

In the composite layer 32, the composite layer 32 closest to the bonding pad 31 has a stress resisting region 321 which is correspondingly disposed under the outer surface 311 of the bonding pad 31 and is made of an insulating material, and electrically connects the semiconductor component 21 with The conductive region 322 of the pad 31, that is, the composite layer 32 closest to the pad 31 is similar to the composite layer 32 of the first preferred embodiment; and the composite layer 32 adjacent to the pad 31 has a corresponding A conductive region 322 is located below the outer surface 311 of the pad 31.

The isolation layers 33 are respectively sandwiched between the bonding pad 31 and the composite layer 32 closest to the bonding pad 31, between the two composite layers 32, and the composite layer 32 adjacent to the bonding pad 31 (that is, closest to the same). The composite layer 32) of the substrate unit 2 is interposed between the substrate unit 2. The connecting body 331 between the bonding pad 31 and the composite layer 32 closest to the bonding pad 31 is directly connected to the conductive region 322 of the composite layer 32 and the bonding pad 31, and the conductive region 322 and the bonding pad 31 are provided. Electrically connected, the connecting body 331 between the composite layers 32 directly connects the conductive regions 322 of the upper and lower composite layers 32, and the connection between the composite layer 32 adjacent to the bonding pads 31 and the substrate unit 2 The body 331 directly connects the conductive region 322 of the composite layer 32 with the semiconductor element 21 of the substrate unit 2. The connecting body 331 is electrically connected to the conductive region 322 of the composite layer 32 and the pad 31, and the electrical signal generated when the external power and the semiconductor device 21 are activated can pass through the conductive region 322 and the pad 31. Transfer.

Referring to FIG. 5, since the mechanical stress from the welding pin 5 has been subjected to the stress resistance zone 321 of the composite layer 32 closest to the bonding pad 31 and the upper and lower sides connecting the stress resistant zone 321 during the process of the bonding wire process. The surface of the insulating material 332 is received without being continuously transferred to the composite layer 32 adjacent to the bonding pad 31. Therefore, the conductive region 322 of the composite layer 32 adjacent to the bonding pad 31 may be correspondingly located in the stress resistant region 321 . Below, and during the process of the wire bonding process, it is not affected by the mechanical stress, so that the design layout of the conductive region 322 and the connecting body 331 of the semiconductor device can be more flexible.

Referring to FIG. 7 and FIG. 8 , a third preferred embodiment of the present invention is similar to the first preferred embodiment, and the difference lies in the composite layer 32 of the third preferred embodiment. There is also a buffer 323.

The buffer region 323 is correspondingly located at the center of the outer surface 311 and is spaced apart from the conductive region 322 through the stress resisting region 321 , that is, the stress resisting region 321 extends laterally outward from the periphery of the buffer region 323 . The 322 extends laterally outward from the periphery of the stress-resisting zone 321 , and the hardness of the buffer zone 323 is less than the hardness of the stress-resisting zone 321; further, the buffer zone 323 is also transmitted through the insulating material 332 of the upper isolation layer 33 and the lower isolation layer. The insulating material 332 of 33 is spaced apart from the bonding pad 31, the conductive region 322, and the substrate unit 2, respectively.

Referring to FIG. 5, since the composite layer 32 of the third preferred embodiment further has the buffer zone 323, when the third preferred embodiment receives the mechanical stress from the soldering pin during the process of the wire bonding, The buffer zone 323 can also be utilized to absorb the remaining mechanical stresses, and the buffer zone 323 is independent of the conductive region 322 and located on the outer surface 311 of the pad 31. Below, the mechanical stress absorbed by the conductive stress is not transmitted to the conductive region 322, and the conductive region 322 is prevented from being deformed, and the probability of cracking of the soldering pad 31 caused by the deformation of the conductive region 322 is also reduced. Furthermore, the package is further improved. Yield of semiconductor devices.

Preferably, the diameter of the buffer zone 323 is not more than 80% of the width of the wire formed on the outer surface 311, and is not less than 30% of the width of the wire formed on the outer surface 311. The three preferred buffer zones 323 have a better cushioning force for mechanical stress.

Referring to FIG. 9, a fourth preferred embodiment of the present invention is similar to the third preferred embodiment, except that the fourth preferred embodiment further includes a plurality of layer composite layers 32. In the fourth preferred embodiment, the composite layer 32 and the three-layer isolation layer 33 including two layers of laterally extending are illustrated.

In the composite layer 32, the composite layer 32 closest to the bonding pad 31 is similar to the composite layer 32 described in the third preferred embodiment; and the composite layer 32 adjacent to the bonding pad 31 has a correspondingly located A conductive region 322 under the outer surface 311 of the pad 31.

The isolation layers 33 are respectively sandwiched between the bonding pad 31 and the composite layer 32 closest to the bonding pad 31, between the two composite layers 32, and the composite layer 32 adjacent to the bonding pad 31 and the substrate unit 2 between. The connecting body 331 between the bonding pad 31 and the composite layer 32 closest to the bonding pad 31 is directly connected to the conductive region 322 of the composite layer 22 and the bonding pad 31 for electrically connecting the conductive region 322 and the bonding pad 31. The connection body 331 located between the composite layers 32 directly connects the conductive regions 322 of the upper and lower composite layers 32, and the connection between the composite layer 32 adjacent to the bonding pads 31 and the substrate unit 2 The body 331 directly connects the conductive region 322 of the composite layer 32 with the semiconductor element 21 of the substrate unit 2. The connecting body 331 electrically connects the conductive region 322 of the composite layer 32 and the pad 31, and the electrical signal generated when the external power and the semiconductor device 21 are activated can pass through the conductive region 327 and the pad 31. Transfer.

Since the mechanical stress from the welding pin 5 has been subjected to the stress resistance region 321 of the composite layer 32 closest to the bonding pad 31 during the process of the bonding wire, and the insulating material 332 connecting the upper and lower surfaces of the stress resistant region 321 The conductive layer 322 of the composite layer 32 adjacent to the bonding pad 31 can be correspondingly located below the stress resisting region 321 and can be soldered. During the process of the wire process, it is not affected by the mechanical stress, so that the design layout of the conductive region 322 and the connector 331 of the semiconductor device can be more flexible.

In summary, the present invention receives the mechanical stress from the wire bonding process through the stress resistant region 321 of the composite layer 32 closest to the bonding pad 31, and prevents the conductive region 322 of the composite layer 32 from being deformed by excessive mechanical stress. However, the probability of cracking due to the imbalance of the supporting force of the lower conductive region 322 is reduced, and the mechanical stress can be absorbed by the buffer 323, thereby reducing the probability of damage of the bonding pad 31, so that the present invention can be achieved. purpose.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

2. . . Substrate unit

twenty one. . . Semiconductor component

3. . . Pad unit

31. . . Solder pad

311. . . The outer surface

32. . . Composite layer

321. . . Stress resistance zone

322. . . Conductive zone

323. . . Buffer

33. . . Isolation layer

331. . . Connector

332. . . Insulating material

34. . . The protective layer

341. . . Opening

4. . . Welding wire

5. . . Solder pin

6. . . Lead frame

61. . . wire

Figure 1 is a cross-sectional view showing a semiconductor device having a pad;

2 is a cross-sectional view showing that the current semiconductor device can not withstand strong mechanical stress and break in the wire bonding process;

3 is a top plan view showing the positional relationship between the conductive region and the connecting body in a first preferred embodiment of the present invention;

Figure 4 is a cross-sectional view showing the first preferred embodiment;

Figure 5 is a cross-sectional view showing the first preferred embodiment of the wire bonding process;

Figure 6 is a cross-sectional view showing a second preferred embodiment of the present invention;

7 is a top plan view showing the positional relationship between the conductive region and the connecting body according to a third preferred embodiment of the present invention;

Figure 8 is a cross-sectional view showing the third preferred embodiment; and

Figure 9 is a cross-sectional view showing a fourth preferred embodiment of the present invention.

2. . . Substrate unit

twenty one. . . Semiconductor component

3. . . Pad unit

31. . . Solder pad

311. . . The outer surface

32. . . Composite layer

321. . . Stress resistance zone

322. . . Conductive zone

33. . . Isolation layer

331. . . Connector

332. . . Insulating material

34. . . The protective layer

341. . . Opening

4. . . Welding wire

Claims (7)

A semiconductor device having a bonding pad electrically connected to the outside through a bonding wire, comprising: a substrate unit including at least one semiconductor component; and a pad unit electrically connected to the semiconductor component, including a bonding wire a solder pad of the outer surface, at least one composite layer formed under the solder pad, and a plurality of layer isolation layers, wherein the composite layer closest to the pad has a correspondingly located under the outer surface and composed of an insulating material a stress-resistant region, a conductive region electrically connecting the semiconductor element and the bonding pad, and a buffer region formed at a center and passing through the stress-resistant region and spaced apart from the conductive region, and the buffer is less rigid than the stress-resistant region The hardness is such that the isolation layers are respectively sandwiched between the bonding pad, the composite layer, and the substrate unit. The semiconductor device with a pad according to claim 1, wherein the pad unit comprises a plurality of layers, and the composite layer adjacent to the pad has a correspondingly located below the outer surface of the pad. The conductive regions are respectively sandwiched between the bonding pads, the composite layers, and the substrate unit. The semiconductor device with a pad according to claim 2, wherein the isolation layer has a plurality of connectors for electrically connecting the semiconductor device to the pad via the conductive regions of the composite layers, and An insulating material filled between the connectors. The semiconductor device with a pad according to claim 3, wherein the main material of the conductive region of the composite layer is metal, and each The hardness of a conductive region is less than the hardness of the stress resistant region. The semiconductor device with a solder pad according to claim 4, further comprising a protective layer formed on the surface of the bonding pad, and having a correspondingly formed on the stress resistant region of the composite layer for the bonding pad The exposed opening of the outer surface. The semiconductor device with a pad according to claim 5, wherein the protective layer has an opening diameter which is not less than a diameter of the stress resistant region. The semiconductor device with a pad according to claim 6, wherein the stress-resistant region has a diameter smaller than 95% of the opening diameter of the protective layer.