TWI462200B - Semiconductor package structure and method for manufacturing the same - Google Patents

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a stacked semiconductor package structure and a method of fabricating the same.

In today's information society, electronic products are designed to be light, thin, short, and small, so that packaging technologies such as stacked semiconductor component packages that facilitate miniaturization have been developed.

The stacked semiconductor device package utilizes a vertical stack (Z direction) to package a plurality of semiconductor components in the same package structure, thereby increasing the package density and reducing the size of the package in the X/Y direction, and utilizing the stereo stack The method shortens the path length of the signal transmission between the semiconductor components to increase the speed of signal transmission between the semiconductor components, and can combine semiconductor components of different functions in the same package.

A stacked semiconductor device packaging process is known in which a top wafer and a lower wafer are bonded by thermocompression bonding, wherein the lower wafer has conductive vias protruding from the first surface and bumps on the second surface. And solder covering the bumps. In detail, the upper wafer is bonded to the via hole exposed on one end of the underlying wafer, and the thermal head is directly bonded to the solder on the underlying wafer. Since the solder generates a molten state and deformation at a high temperature, the thermal head is contaminated, and the bump and the package substrate on the lower wafer are subsequently bonded to the package substrate by the underlying wafer and the upper wafer thereon. The pads on the top are also not effectively bonded, thereby reducing the process yield and structural reliability of the stacked semiconductor components.

The invention provides a semiconductor package structure with good structural reliability.

The invention also provides a method of fabricating a semiconductor package structure for fabricating the above-described semiconductor package structure.

The present invention provides a method of fabricating a semiconductor package structure that includes the following steps. A package substrate is provided. The package substrate has a bearing surface, a plurality of first pads on the bearing surface, and a plurality of first metal layers covering the first pads. A first wafer is provided. The first wafer has a plurality of via holes therein. The first wafer has a first surface and a second surface opposite to each other, and the via hole protrudes from the first surface. The second surface of the first wafer has a plurality of second pads, a plurality of second bumps on the second pads, and a plurality of second metal layers covering the second bumps. Bonding a second wafer to the via holes of the first wafer and forming a second primer between the second wafer and the first wafer to cover a portion of the via hole protruding from the first surface. The second wafer and the first wafer are bonded to the bearing surface of the package substrate, and a first primer is formed between the first wafer and the package substrate. The first wafer is located between the second wafer and the package substrate, and the first wafer is connected to the first metal layer on the first pad of the package substrate through the second metal layer on the second bump. The first primer covers the first metal layer, the second bump, and the second metal layer.

In an embodiment of the invention, the first primer is pre-formed on the bearing surface of the package substrate before bonding the second wafer and the first wafer to the package substrate.

In an embodiment of the invention, the second primer is pre-formed on the second wafer before bonding the second wafer to the vias of the first wafer.

In an embodiment of the invention, the step of providing the first wafer includes: providing a carrier, an adhesive layer is formed on a surface of the carrier; and configuring a first wafer on the carrier, the first crystal The circle has an upper surface and a plurality of conductive pillars, and the second surface of the first wafer has a second pad, a second bump, and a second metal layer covering the second bump, and the adhesive layer covers the second protrusion And a second metal layer; thinning the upper surface of the first wafer; exposing one end of the conductive pillar to form a via hole, wherein the ends of the via hole protrude from the first surface; separating the first wafer and the adhesive layer, To expose the second bump and the second metal layer; and perform a singulation cutting step to cut the first wafer to form a plurality of first wafers.

In an embodiment of the present invention, before the separating the first wafer and the adhesive layer, forming a protective layer on the first surface, wherein the protective layer does not cover the via hole; and after forming the protective layer, One end of a via hole is surface-finished to form a surface treatment layer covering one end of the via hole.

In an embodiment of the invention, the step of bonding the second wafer to the via of the first wafer includes: providing a second wafer having a plurality of contacts on a surface of the second wafer; a wafer on the second wafer, wherein the contacts are connected to the surface treatment layer on the ends of the via holes; and a singulation cutting step is performed to cut the second wafer to form a plurality of first wafers The second wafer is bonded, wherein each second wafer has a size greater than the size of each of the first wafers.

In an embodiment of the present invention, after bonding the second wafer and the first wafer to the bearing surface of the package substrate, forming an encapsulant on the package substrate, the encapsulant coating the second wafer, first Primer, second primer, and first wafer.

In an embodiment of the invention, the step of bonding the second wafer to the via of the first wafer includes: providing a first wafer, the first wafer including the first wafer; and bonding the second wafer to the first On the wafer, wherein the second wafer has a plurality of contacts, and the contacts are connected to the via holes of the first wafer; after bonding the second wafer to the first wafer, a first encapsulant is formed to cover the second a wafer, a portion of the first wafer, and a second primer; and after forming the first encapsulant, performing a singulation cutting step to cut the first wafer and a portion of the first encapsulant to form a second wafer The bonded first wafer, wherein the size of the second wafer is smaller than the size of the first wafer.

In an embodiment of the invention, after the bonding of the second wafer and the first wafer to the bearing surface of the package substrate, a second encapsulant is formed on the package substrate, and the second encapsulant is coated first. The encapsulant, the first primer, and the first wafer.

In an embodiment of the invention, the second primer is a non-conductive film (NCF).

In an embodiment of the invention, the first metal layer is a tin layer.

In an embodiment of the invention, the second metal layer is formed of a nickel layer and a gold layer.

The present invention also provides a method of fabricating a semiconductor package structure comprising the following steps. A package substrate is provided. The package substrate has a bearing surface, a plurality of first pads on the bearing surface, and a plurality of first metal layers covering the first pads. Bonding a first wafer to the carrying surface of the package substrate and forming a first primer between the package substrate and the first wafer. The first wafer has a plurality of via holes therein. The first wafer has a first surface and a second surface opposite to each other, and the via hole protrudes from the first surface. The second surface of the first wafer has a plurality of second pads, a plurality of second bumps on the second pads, and a plurality of second metal layers covering the second bumps. The first wafer is connected to the first metal layer on the first pad of the package substrate through the second metal layer on the second bump. The first primer covers the first metal layer, the second bump, and the second metal layer. Bonding a second wafer to the via hole of the first wafer bonded to the package substrate, and forming a second primer between the second wafer and the first wafer to cover the via hole to protrude from the first surface part.

In an embodiment of the invention, the first primer is pre-formed on the carrier surface of the package substrate before bonding the first wafer to the package substrate.

In an embodiment of the invention, the second primer is pre-formed on the second wafer before bonding the second wafer to the vias of the first wafer.

In an embodiment of the invention, the step of providing the first wafer includes: providing a carrier, an adhesive layer is formed on a surface of the carrier; and configuring a wafer on the carrier, having the wafer An upper surface and a plurality of conductive pillars, and the second surface of the wafer has a second pad, a second bump, and a second metal layer covering the second bump, and the adhesive layer covers the second bump and the second a metal layer; thinning the upper surface of the first wafer; exposing one end of the conductive pillar to form a via hole, wherein the ends of the via hole protrude from the first surface; separating the wafer and the adhesive layer to expose the second convex a block and a second metal layer; and performing a singulation cutting step to diced the wafer to form a plurality of first wafers.

In an embodiment of the present invention, before the separating the wafer and the adhesive layer, forming a protective layer on the first surface, wherein the protective layer does not cover the via hole; and after forming the protective layer, each of the conductive layers One end of the hole is surface-finished to form a surface treatment layer covering one end of the via hole.

In an embodiment of the present invention, after bonding the second wafer to the via hole of the first wafer, forming an encapsulant on the package substrate, the encapsulant coating the second wafer, the first primer, and the first Two primers and a first wafer.

In an embodiment of the invention, the second primer is a non-conductive film (NCF).

In an embodiment of the invention, the first metal layer is a tin layer.

In an embodiment of the invention, the second metal layer is formed of a nickel layer and a gold layer.

The invention provides a semiconductor package structure comprising a package substrate, a first wafer, a first primer, a second wafer and a second primer. The package substrate has a bearing surface, a plurality of first pads on the bearing surface, and a plurality of first metal layers covering the first pads. The first wafer is bonded to the package substrate. The first wafer has a plurality of via holes therein, and the first wafer has a first surface and a second surface opposite to each other. The via hole protrudes from the first surface, and the second surface of the first wafer has a plurality of second pads, a plurality of second bumps on the second pads, and a plurality of second metal layers covering the second bumps. The first wafer is connected to the first metal layer on the first pad of the package substrate through the second metal layer on the second bump. The first primer is disposed between the first wafer and the package substrate, and covers the first metal layer, the second bump, and the second metal layer. The second wafer is disposed over the first wafer and bonded to the vias of the first wafer. The second primer is disposed between the second wafer and the first wafer, and the portion of the cladding via protruding from the first surface.

In an embodiment of the invention, the size of the second wafer is greater than the size of the first wafer.

In an embodiment of the invention, the semiconductor package structure further includes a surface treatment layer and a protective layer. The surface treatment layer is disposed on one end of each of the via holes protruding from the first surface of the first wafer. The protective layer is disposed on the first surface of the first wafer and does not cover the via holes.

In an embodiment of the invention, the semiconductor package structure further includes a plurality of solder balls disposed on a bottom surface of the package substrate relative to the bearing surface.

In one embodiment of the invention, the semiconductor package structure further includes an encapsulant disposed on the package substrate, and the encapsulant encapsulates the second wafer, the first primer, the second primer, and the first wafer.

In one embodiment of the present invention, the semiconductor package structure further includes a first encapsulant disposed on the first wafer and covering at least a side surface of the second wafer and a portion of the first wafer, wherein a side of the first encapsulant And the sides of the first wafer are substantially flush with each other, and the size of the second wafer is smaller than the size of the first wafer.

In one embodiment of the invention, the semiconductor package structure further includes a second encapsulant disposed on the package substrate, and the second encapsulant encapsulates the first encapsulant, the first primer, and the first wafer.

In an embodiment of the invention, the second primer is a non-conductive film (NCF).

In an embodiment of the invention, the first metal layer is a tin layer.

In an embodiment of the invention, the second metal layer is formed of a nickel layer and a gold layer.

Based on the above, since the first wafer of the present invention has the second metal layer covering the second bumps, when the first wafer and the second wafer are bonded by thermocompression bonding, the thermal head directly contacts the second bump. The second metal layer on the block, and the second metal layer does not melt and deform due to high temperature, so that the problem that the conventional molten solder contaminates the thermal head and the subsequent wafer and package substrate bond yield is not good can be avoided. . That is to say, when the second bump of the first wafer of the present invention is bonded to the first pad of the package substrate, the process yield and structural reliability can be better.

The above described features and advantages of the present invention will be more apparent from the following description.

Embodiments of the present invention disclose a semiconductor package structure and a method of fabricating the same, the first wafer having a second metal layer overlying the second bump. Therefore, when the first wafer and the second wafer are bonded by thermocompression bonding, the thermal head directly contacts the second metal layer on the second bump, and the second metal layer does not melt due to high temperature. The deformation can avoid the problem that the conventional molten solder contaminates the thermal head and the subsequent wafer and the package substrate have poor bonding yield. That is to say, when the second bump of the first wafer of the present invention is bonded to the first pad of the package substrate, the process yield and structural reliability can be better.

It should be noted that in the current conductive via packaging technology for multi-wafer stacking on a substrate, three methods are generally used for packaging: the first method is to temporarily dispose the underlying wafer with via holes. On a carrier, and thinning it to expose the via. Next, the bonding of the upper wafer to the lower wafer is performed without cutting the underlying wafer. Thereafter, the underlying wafer is diced and the stacked wafer structure is bonded to the package substrate. In the second method, the underlying wafer with the buried via and the singulation is flip-chip bonded to the package substrate and protected by dispensing, and the underlying wafer is thinned by the grinding technique, and the via is exposed. After the via holes are surface-treated, the upper wafer is stacked on the lower wafer. In the third way, the process of all the underlying wafers is completed first, and the via holes are exposed and the thickness of the wafer is thinned. Thereafter, the singulated underlying wafer is bonded to the upper wafer in a flip chip manner, and after the dispensing is completed, the flip chip bonding of the stacked wafer and the package substrate is performed. The above-mentioned one of the processes is applicable to the semiconductor package structure proposed by the present invention and a method of fabricating the same.

1A-1N are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention. It should be noted that FIG. 1F is a schematic top view of a first wafer according to an embodiment of the present invention. Referring to FIG. 1A, in a method of fabricating a semiconductor package structure according to the present embodiment, first, a carrier 10 and a first wafer 20 are provided, wherein an adhesive layer 30 is formed on a surface 12 of the carrier 10. The first wafer 20 has a plurality of conductive pillars 22, and a second surface 123 of the first wafer 20 has a plurality of second pads 124 and a plurality of second bumps 126 on the second pads 124. And a plurality of second metal layers 128 covering the second bumps 126. Here, the second metal layer 128 is composed of a nickel layer 128a and a gold layer 128b covering the nickel layer 128a.

Next, referring to FIG. 1B , the first wafer 20 is placed on the carrier 10 , wherein the adhesive layer 30 covers at least the second bumps 126 and the second metal layer 128 of the first wafer 20 on the second surface 123 . Next, the first wafer 20 is thinned by the upper surface 14 of the first wafer 20, and as shown in FIG. 1B, one end 22a of the conductive pillar 22 is exposed by, for example, etching to form a plurality of via holes. 122 , wherein the ends 122 a of the vias 122 protrude from a first surface 121 of the first wafer 20 .

Next, referring to FIG. 1C, a protective layer 165 may be selectively formed on the first surface 121 of the first wafer 20, wherein the protective layer 165 does not cover the via hole 122, wherein the protective layer is, for example, an inorganic material protective layer. For example, an inorganic insulating layer such as cerium oxide (SiO ₂ ) or nitrogen dioxide (SiN _x ); or a protective layer of a polymer material such as polyimide (PI) or benzocyclobutene (BCB) )Wait. Moreover, as shown in FIG. 1D, one end 122a of the first wafer 20 is protruded from each of the via holes 122 to perform a surface finish to form a surface finish layer covering one end 122a of the via hole 122. 160.

Next, referring to FIG. 1E , the first wafer 20 and the adhesive layer 30 are separated to expose the second bumps 126 and the second metal layer 128 on the second surface 123 of the first wafer 20 . Next, as shown in FIG. 1F, a singulation step is performed to cut the first wafer 20 to form a plurality of first wafers 120 (only one first wafer 120 is schematically illustrated in FIG. 1E). So far, the fabrication of the first wafer 120 has been completed.

Next, referring to FIG. 1G, a second wafer 40 is provided, wherein a surface 142 of the second wafer 40 has a plurality of contacts 144 thereon. Moreover, as shown in FIG. 1H, a second primer 150 is formed on the surface 142 of the second wafer 40, wherein the second primer 150 covers a portion of the surface 142 of the second wafer 40 and the contact 144.

Next, please refer to FIG. 1I and FIG. 1J simultaneously to bond the first wafer 120 on the second wafer 40. In the present embodiment, the first wafer 120 has a via hole 122 therein, and the one end 122a of the via hole 122 protruding from the first surface 121 is covered by the surface treatment layer 160, and the second surface 123 of the first wafer 120 has a second surface. The pad 124, the second bump 126 on the second pad 124 and the second metal layer 128 covering the second bump 126. When the first wafer 120 and the second wafer 40 are pre-bonded, the second metal layer 128 of the first wafer 120 is directly pressed through a thermal head 50 by thermal compression, so that the first wafer The surface treatment layer 160 on the ends 122a of the vias 122 of the 120 is connected to the contacts 144 of the second wafer 40, and the second primer 150 simultaneously covers the contacts 144, the protective layer 165 on the first wafer 120. And a surface treatment layer 160 located on the one end 122a of the first surface 121 of the via hole 122.

Since the second metal layer 128 is composed of the nickel layer 128a and the gold layer 128b, when the thermal head 50 directly contacts the second metal layer 128 on the second bump 126, the second metal layer 128 does not become high temperature. Melting and deformation are generated, so that the problem that the conventional molten solder contaminates the thermal head and the subsequent bonding yield of the wafer to the package substrate is not good can be avoided. That is to say, in this embodiment, the second metal layer 128 on the second bump 126 of the first wafer 120 is directly contacted by the thermal head, which can improve the yield and reliability of the subsequent process.

Next, referring to FIG. 1J, a singulation cutting step is performed to cut the second wafer 40 through a cutting tool 60 to form a plurality of second wafers 140 bonded to the first wafer 120 (only in FIG. 1J). A second wafer 140) is schematically illustrated, wherein each second wafer 140 has a size greater than the size of each of the first wafers 120.

1K, a package substrate 110 is provided, wherein the package substrate 110 has a bearing surface 112, a plurality of first pads 114 on the bearing surface 112, and a plurality of covering the first pads 114. A metal layer 116. Here, the first metal layer 116 is, for example, a tin layer.

Finally, as shown in FIG. 1L, the second wafer 140 and the first wafer 120 are bonded to the bearing surface 112 of the package substrate 110, wherein the first primer 130 is located between the first wafer 120 and the package substrate 110. In detail, the first wafer 120 is located between the second wafer 140 and the package substrate 110 , and the first wafer 120 passes through the second metal layer 128 on the second bump 126 and the first pad 114 of the package substrate 110 . The first metal layer 116 is connected, and the first primer 130 covers the first metal layer 116, the second bump 126, the second metal layer 128, and the second surface 123 of the first wafer 120. So far, the fabrication of the semiconductor package structure 100a has been completed.

Structurally, the semiconductor package structure 100a includes a package substrate 110, a first wafer 120, a first primer 130, a second wafer 140, and a second primer 150. The package substrate 110 has a carrier surface 112, a first pad 114 on the carrier surface 112, and a first metal layer 116 covering the first pad 114. The first wafer 120 is bonded to the package substrate 110. The first wafer 120 has a plurality of via holes 122 therein, and the first wafer 120 has a first surface 121 and a second surface 123 opposite to each other. The through hole 122 protrudes from the one end 122a of the first surface 121 to selectively configure the surface treatment layer 160, and the first surface 121 of the first wafer 120 is selectively disposed with the protective layer 165, wherein the protective layer 165 does not cover the via hole 122. The second surface 123 of the first wafer 120 has a plurality of second pads 124, second bumps 126 on the second pads 124, and a second metal layer 128 covering the second bumps 126. The first wafer 120 is connected to the first metal layer 116 on the first pad 114 of the package substrate 110 through the second metal layer 128 on the second bump 126. The first primer 130 is disposed between the first wafer 120 and the package substrate 110 and covers the first metal layer 116 , the second bump 126 , and the second metal layer 128 . The second wafer 140 is disposed above the first wafer 120, and the contacts 144 of the second wafer 140 are bonded to the vias 122 of the first wafer 120, wherein the size of the second wafer 140 is greater than the size of the first wafer 120. The second primer 150 is disposed between the second wafer 140 and the first wafer 120 , and the cladding via 122 protrudes from a portion of the first surface 121 .

Since the first wafer 120 of the embodiment has the second metal layer 128 covering the second bumps 126, the thermal heads are directly contacted when the first wafer 120 and the second wafer 140 are bonded by thermocompression bonding. The second metal layer 128 on the second bump 126 of the first wafer 120, and the second metal layer 128 does not melt and deform due to high temperature, so that the conventional molten solder can be prevented from contaminating the subsequent wafer generated by the thermal head. The problem of poor yield bond with the package substrate. That is, when the second bumps 126 of the subsequent first wafer 120 are bonded to the first pads 114 of the package substrate 110, the process yield and structural reliability may be better.

In addition, as shown in FIG. 1M, the present embodiment can selectively form an encapsulant 182 on the package substrate 110 to form a semiconductor package structure 100a'. The encapsulant 182 covers the second wafer 140, the second primer 150, the first wafer 120, and the first primer 130. In addition, in order to increase the applicability of the semiconductor package structure 100a', please refer to FIG. 1N, or a plurality of solder balls 190 may be selectively formed on a bottom portion 118 of the package substrate 110 to form a semiconductor package structure 100a". The semiconductor package structure 100" can be electrically connected to an external circuit (not shown) through the solder ball 190 to increase its applicability.

It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2A-2D are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 2D, the semiconductor package structure 100b is similar to the semiconductor package structure 100a" of the foregoing embodiment. The main difference is that the second primer 150b of the semiconductor package structure 100b is a non-conductive film (Non-Conductive Film, NCF).

In detail, the semiconductor package structure 100b of the present embodiment can be fabricated in substantially the same manner as the semiconductor package structure 100a" of the foregoing embodiment, and after the step of FIG. 1G, a second primer 150b is formed on the second wafer. The second primer 150 covers the surface 142 of the second wafer 40 and the contact 144. Here, the second primer 150b is a non-conductive film (NCF). Referring to FIG. 2B, the first wafer 120 is bonded to the second wafer 40 by thermal compression bonding. Then, after the steps of FIG. 1J and FIG. 1L are sequentially performed, please refer to FIG. 2C, the second primer 150b. The sides are substantially flush with the sides of the second wafer 140. Thereafter, referring to FIG. 2C, solder balls 190 are formed on the bottom 118 of the package substrate 110, and a package is formed on the package substrate 110 as shown in FIG. 2D. The colloid 182 covers the second wafer 140, the second primer 150b, the first wafer 120, and the first primer 130. Thus, the fabrication of the semiconductor package structure 100b can be substantially completed.

It is to be noted that, from the foregoing FIG. 1M and FIG. 1N, the order of the two steps of forming the solder ball 190 and the encapsulant 180 of FIG. 2C and FIG. 2D of the present embodiment is interchangeable. That is, the present embodiment may choose to form the encapsulant 182 on the package substrate 110 first, and then form the solder balls 190 at the bottom 118 of the package substrate 110. In short, the order of formation of the encapsulant 182 and the solder ball 190 is not limited herein. Those skilled in the art can refer to the description of the foregoing embodiment, and select the foregoing process according to actual needs to achieve the required technology. effect.

3A-3C are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention. Structurally, referring to FIG. 3C, the semiconductor package structure 100c is similar to the semiconductor package structure 100a' of the previous embodiment. The main difference is that the size of the second wafer 140 of the semiconductor package structure 100c is smaller than that of the first wafer 120. size.

In the process, the semiconductor package structure 100c of the present embodiment can be fabricated in substantially the same manner as the semiconductor package structure 100a' of the foregoing embodiment, and after the step of FIG. 1E, the first wafer 20 and the adhesive layer 30 are separated. After exposing the second bumps 126 and the second metal layer 128 on the second surface 123 of the first wafer 20, please refer to FIG. 3A, bonding the second wafer 140 to the first wafer 20, wherein the second The wafer 140 has a contact 144, and the contact 144 is connected to the surface treatment layer 160 of the first wafer 120 through which the via 122 protrudes from one end 122a of the first surface 121. Next, referring to FIG. 3B , a first encapsulant 184 is formed on the first wafer 20 to cover the second wafer 140 , the portion of the first wafer 20 , and the second primer 150 . Thereafter, referring to FIG. 3B and FIG. 3C, a singulation cutting step is performed along the dicing line L to cut the first wafer 20 and a portion of the first encapsulant 184 to form a bonding with the second wafer 140. The first wafer 120, wherein the size of the second wafer 140 is smaller than the size of the first wafer 120. In particular, in the embodiment, the first encapsulant 184 covers at least a side surface of the second wafer 140 and a portion of the first wafer 120, wherein the side surface of the first encapsulant 184 and the side surface of the first wafer 120 are substantially flush with each other. level. Finally, referring to FIG. 3C, after bonding the second wafer 140 and the first wafer 120 to the package substrate 110, a second encapsulant 186 is formed on the package substrate 110, wherein the second encapsulant 186 covers at least the first package. The colloid 184, the first primer 130, and the first wafer 120. Thus far, the fabrication of the semiconductor package structure 100c can be substantially completed.

4A-4K are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention. Structurally, referring to FIG. 4K, the semiconductor package structure 100d of the present embodiment is substantially the same as the semiconductor package structure 100a' except for the manner in which it is fabricated. In detail, the semiconductor package structure 100d of the present embodiment can be fabricated in substantially the same manner as the semiconductor package structure 100a' of the foregoing embodiment, and after the step of FIG. 1F, that is, after the fabrication of the first wafer 120 is completed, please Referring to FIG. 4A, a package substrate 110 is provided, wherein the package substrate 110 has a carrier surface 112, a first pad 114 on the carrier surface 112, and a first metal layer 116 covering the first pad 114, and is packaged. A first primer 130 is formed on the bearing surface 112 of the substrate 110. Here, the first metal layer 116 is, for example, a tin layer.

Next, referring to FIG. 4B, the first wafer 120 is bonded to the carrying surface 112 of the package substrate 110, wherein the first primer 130 is located between the package substrate 110 and the first wafer 120, and the first wafer 120 is transmitted through the second wafer 120. The second metal layer 128 on the bump 126 is connected to the first metal layer 116 on the first pad 114 of the package substrate 110, and the first primer 130 covers the first metal layer 116 and the second bump 126. a second metal layer 128 and a second surface 123 of the first wafer 120. Next, referring to FIG. 4C, a second wafer 140 is provided, wherein the surface 142 of the second wafer 140 has a contact 144 thereon, and as shown in FIG. 4D, a second primer 150b is formed on the surface 142 of the second wafer 140. Wherein the second primer 150b covers the contacts 144. In this embodiment, the second primer 150b is a non-conductive film (NCF). Then, referring to FIG. 4E, the second wafer 140 is bonded to the via hole 122 of the first wafer 120 that has been bonded to the package substrate 110 by thermal compression bonding, so that the second primer 150b covers the via hole. 122 is a surface treatment layer 165 that protrudes from one end 122a of the first surface 122. Thereafter, as shown in FIG. 4F, the encapsulant 182 may be selectively formed on the package substrate 110 to cover the second wafer 140, the second primer 150b, the first wafer 120, and the first primer 130. So far, the fabrication of the semiconductor package structure 100d has been completed.

In summary, the first wafer of the present invention has a second metal layer covering the second bumps. Therefore, when the first wafer and the second wafer are bonded by thermocompression bonding, the thermal head directly contacts the second metal. The second metal layer on the bump, and the second metal layer does not melt and deform due to high temperature, so that the conventional molten solder can be prevented from contaminating the thermal head and the subsequent wafer and package substrate bonding yield is not good. problem. That is to say, when the second bump of the first wafer of the present invention is bonded to the first pad of the package substrate, the process yield and structural reliability can be better.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Carrier

12. . . surface

14. . . Upper surface

20. . . First wafer

twenty two. . . Conductive column

22a. . . One end

30. . . Adhesive layer

40. . . Second wafer

50. . . Hot head

60. . . Cutting tool

100a, 100a', 100a", 100b, 100c, 100d... semiconductor package structure

110. . . Package substrate

112. . . Bearing surface

114. . . First pad

116. . . First metal layer

118. . . bottom

120. . . First wafer

121. . . First surface

122. . . Via

122a. . . One end

123. . . Second surface

124. . . Second pad

126. . . Second bump

128. . . Second metal layer

128a. . . Nickel layer

128b. . . Gold layer

130. . . First primer

140. . . Second chip

142. . . surface

144. . . contact

150, 150b. . . Second primer

160. . . Surface treatment layer

170. . . Solder ball

182. . . Encapsulant

184. . . First encapsulant

186. . . Second encapsulant

190. . . Solder ball

L. . . Cutting line

1A-1N are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention.

2A-2D are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention.

3A-3C are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention.

4A-4F are cross-sectional views showing a part of steps of a method of fabricating a semiconductor package structure according to another embodiment of the present invention.

100a. . . Semiconductor package structure

110. . . Package substrate

112. . . Bearing surface

114. . . First pad

116. . . First metal layer

120. . . First wafer

121. . . First surface

122. . . Via

123. . . Second surface

124. . . Second pad

126. . . Second bump

128. . . Second metal layer

128a. . . Nickel layer

128b. . . Gold layer

130. . . First primer

140. . . Second chip

142. . . surface

144. . . contact

150. . . Second primer

160. . . Surface treatment layer

165. . . The protective layer

Claims (17)

A method for fabricating a semiconductor package structure, comprising: providing a package substrate, the package substrate having a bearing surface, a plurality of first pads on the bearing surface, and a plurality of first pads covering the first pads a metal layer; a first wafer having a plurality of vias therein, the first wafer having a first surface opposite to each other and a second surface, the vias projecting the first surface The second surface of the first wafer has a plurality of second pads, a plurality of second bumps on the second pads, and a plurality of second metal layers covering the second bumps; a second wafer is formed on the via holes of the first wafer, and a second primer is formed between the second wafer and the first wafer to cover portions of the conductive vias protruding from the first surface And bonding the second wafer, the first wafer to the bearing surface of the package substrate, and forming a first primer between the first wafer and the package substrate, wherein the first wafer is located Between the second wafer and the package substrate, and the first wafer is transparent The second metal layers on the second bumps are connected to the first metal layers on the first pads of the package substrate, and the first primer covers the first metal layers The second bumps and the second metal layers. The method for fabricating a semiconductor package structure according to claim 1, wherein the step of providing the first wafer comprises: providing a carrier having an adhesive layer formed on a surface thereof; and configuring a first crystal Rounded on the carrier, the first wafer has an upper surface and a plurality of conductive pillars, and the second surface of the first wafer has the second pads, the second bumps, and the cover The second metal layers of the second bumps, the adhesive layer covers the second bumps and the second metal layers; thin the upper surface of the first wafer; exposing the conductive One end of the pillars to form the via holes, wherein the ends of the via holes protrude from the first surface; separating the first wafer and the adhesive layer to expose the second bumps and the a second metal layer; and performing a singulation cutting step to diced the first wafer to form a plurality of the first wafers. The method of fabricating a semiconductor package structure according to claim 2, wherein the step of bonding the second wafer to the via holes of the first wafer comprises: providing a second wafer, the second wafer a surface having a plurality of contacts; bonding the first wafer to the second wafer, wherein the contacts are connected to the surface treatment layer on the ends of the via holes; and performing a single Forming a cutting step to cut the second wafer to form a plurality of the second wafers bonded to the first wafers, wherein each of the second wafers has a size larger than a size of each of the first wafers. The method of fabricating a semiconductor package structure according to claim 1, wherein the step of bonding the second wafer to the via holes of the first wafer comprises: providing a first wafer, the first wafer Include the first wafer; bonding the second wafer to the first wafer, wherein the second wafer has a plurality of contacts, and the contacts are connected to the via holes of the first wafer; After the second wafer is on the first wafer, a first encapsulant is formed to cover the second wafer, a portion of the first wafer, and the second primer; and after the first encapsulant is formed, a singulation step of cutting the first wafer and a portion of the first encapsulant to form the first wafer bonded to the second wafer, wherein the size of the second wafer is smaller than that of the first wafer size. The method of fabricating a semiconductor package structure according to claim 4, wherein after bonding the second wafer and the first wafer to the carrier surface of the package substrate, forming a second encapsulant in the package On the substrate, the second encapsulant covers the first encapsulant, the first primer, and the first wafer. The method of fabricating a semiconductor package structure according to claim 1, wherein the first metal layer is a tin layer. The method of fabricating a semiconductor package structure according to claim 1, wherein the second metal layer is composed of a nickel layer and a gold layer. A method for fabricating a semiconductor package structure, comprising: providing a package substrate, the package substrate having a bearing surface, a plurality of first pads on the bearing surface, and a plurality of first pads covering the first pads a metal layer; bonding a first wafer to the bearing surface of the package substrate, and forming a first primer between the package substrate and the first wafer, wherein the first wafer has a plurality of conduction a first wafer having a first surface and a second surface opposite to each other, the via holes projecting the first surface, and the second surface of the first wafer has a plurality of second pads a second bump on the second pads and a plurality of second metal layers covering the second bumps, the first wafers passing through the second metal layers on the second bumps The first metal layers on the first pads of the package substrate are connected, and the first primer covers the first metal layers, the second bumps, and the second metal layers; Bonding a second wafer to the first wafer that has been bonded to the package substrate The via hole, and forming a second adhesive to the second substrate between the first wafer and the wafer, encapsulating the via hole to the projecting portion of the first surface. The method of fabricating a semiconductor package structure according to claim 8 , wherein the second primer is a non-conductive film (NCF). The method of fabricating a semiconductor package structure according to claim 8, wherein the first metal layer is a tin layer. The method of fabricating a semiconductor package structure according to claim 8, wherein the second metal layer is composed of a nickel layer and a gold layer. A semiconductor package structure comprising: a package substrate having a carrier surface, a plurality of first pads on the carrier surface, and a plurality of first metal layers covering the first pads; a first wafer Bonding to the package substrate, the first wafer has a plurality of vias therein, and the first wafer has a first surface and a second surface opposite to each other, the via holes projecting the first surface, and the conductive vias protrude from the first surface The second surface of the first wafer has a plurality of second pads, a plurality of second bumps on the second pads, and a plurality of second metal layers covering the second bumps, the first The first metal layer on the second pads of the package substrate is connected to the first metal layers on the first pads of the package substrate; a first primer is disposed on the first chip Between the package substrate and the first metal layer, the second bumps and the second metal layers; a second wafer disposed above the first wafer and bonded to the first The via holes of a wafer; and a second primer disposed on the second wafer and the Between a wafer, and covering the plurality of vias on the first surface of the projecting portion. The semiconductor package structure of claim 12, wherein the size of the second wafer is larger than the size of the first wafer. The semiconductor package structure of claim 12, further comprising: a surface treatment layer disposed on one end of each of the via holes protruding from the first surface of the first wafer; and a protective layer disposed thereon The first surface of the first wafer does not cover the via holes. The semiconductor package structure of claim 12, wherein the second primer is a Non-Conductive Film (NCF). The semiconductor package structure of claim 12, wherein the first metal layer is a tin layer. The semiconductor package structure of claim 12, wherein the second metal layer is composed of a nickel layer and a gold layer.