TWI461910B - Memories and methods for performing atomic memory operations in accordance with configuration information - Google Patents

Description

Memory and method for performing atomic memory operations in accordance with configuration information

Embodiments of the present invention are generally related to memory, and in one or more of the illustrated embodiments, more specifically to logic having operations operable to provide atomic memory under mask control. And a memory with a variable operand size.

The memory is used in electronic systems and circuits to store data that can be retrieved for processing by, for example, a processor. The data can be written to the memory and later read from the memory. In more advanced memory, basic operations can be performed by logic in the memory itself to free a processor from issuing multiple memory commands to the memory and managing the operation. For example, a processor can issue a single "read-modify-write" command to a memory, and the memory manages to retrieve data from the memory, perform operations on the data, and write the resultant data back. The steps to the memory. Thus, while a memory command is issued to the memory, the memory itself manages and executes a plurality of operations involving accessing data stored in a memory and performing operations on the data. These commands can be referred to as "atomic memory operations." Such operations are referred to as "atomic" because they are performed indivisibly: if one order cannot be interrupted or subdivided. If a processor is required to update a shared memory item, additional operations must be performed to prevent the shared processor from accessing and/or modifying the data item while the first processor is executing the update before returning the updated data to the memory. . By placing the update operation more directly in the memory, the shared project can be updated more quickly without the extra burden of coherence and with reduced energy expenditure.

The memory and control logic that performs atomic memory operations may not have the flexibility to accommodate manipulation of data of different sizes. That is, the memory can be designed to perform operations on data having a certain length and data units of a certain size. Performing operations on smaller data units (e.g., performing an operation on a tuple of data, although extracting 4 bytes of data) will consume an entire operational cycle, although only the results of the smaller data units are expected. Discard the results of operations performed on other data units. Since the desired data may need to be retrieved in one of a plurality of different data blocks and cannot be performed in a single simple order or efficiently, the operation of using data from different blocks may require more operations on specific data. Operations.

Therefore, it is desirable to have a memory capable of performing an atomic memory operation that also provides flexibility in terms of operands and data size independently of the manner in which a particular memory operation is performed.

Embodiments of the present invention can provide capabilities so that multiple atomic operations can be performed simultaneously with a single command. Certain details are set forth below to provide a thorough understanding of one embodiment of the invention. It will be apparent to those skilled in the art, however, that the embodiments of the invention may be practiced without the specific details. In addition, the specific embodiments of the invention set forth herein are provided by way of example only and are not intended to limit the scope of the invention. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the present invention.

Figure 1 illustrates a portion of a memory 100 in accordance with one embodiment of the present invention. The memory 100 includes an IO interface 110 that receives memory commands and other information (such as configuration information related to data associated with memory commands) to request execution of memory commands. Memory commands and configuration information can be provided to the IO interface 110 in a packetized format. That is, a command packet can include fields in which a combination of binary digits (bits) in the fields represents information that can be decoded by a command decoder (such as a packet decoder 120) to determine which command to execute. And in some embodiments, configuration information related to the data associated with the command packet is represented. Examples of command packets containing configuration information related to the data are explained in more detail below.

Packet decoder 120 receives the packet from IO interface 110 and decodes the packet to generate internal control and timing signals to implement the requested memory command. For example, in the embodiment of FIG. 1, packet decoder 120 decodes a packet to generate an internal signal representative of command, address, operational metadata, mask information, length information, and data unit size information. The address information is provided to a memory store 130 configured to store data to identify memory locations that are accessible during execution of the command. It can be implemented using a variety of different technologies, such as memory cell technology (such as dynamic random access memory cells, static random access memory cells, and non-volatile memory cells) and disk technology (such as disk drive media). Memory storage 130.

Memory 100 further includes operational logic 140 that performs memory operations, such as read and write operations, and other operations that can be part of an atomic memory operation. The operational logic 140 is controlled by the internal control and timing signals (eg, commands, addresses, operational metadata and masks, data lengths, and data unit size information) provided by the packet decoder 120. As will be explained in more detail below, the control of operational logic 140 is based, at least in part, on information received in a memory packet. In some embodiments, operational logic 140 performs various operations on the operational metadata, such as logical operations, arithmetic operations, comparison operations. The operational metadata may be data associated with the control, function, and provided to the memory 100 and in a separate signal or having a command packet; the memory stored in the memory may be retrieved in response to a command in the command packet Memory data in the device 130; or a combination thereof. In response to a command packet to return data, a packet combiner 150 in memory 100 receives the data from operational logic 140 and prepares the data to be provided through IO interface 110, for example, in the form of a return data packet. In some embodiments, the data can be returned directly. The data may be the result of operations performed by operational logic 140, data retrieved from memory storage 130, or some other material.

In some embodiments of the invention, the blocks illustrated in Figure 1 represent memory storage interface circuits coupled to communicate with one of a plurality of memory memories that are operable independently of one another. For example, the memory bank can be implemented in one embodiment by stacking a plurality of memory devices all communicating with blocks 110, 120, 130, 140, and 150.

The memory 100 can perform a conventional memory operation, for example, reading data from a location in the memory bank 130 identified by a memory address and writing the data to the location. Memory 100 is further operable to perform atomic memory operations. As previously discussed, the atomic memory operation is presented as a memory operation that is not separable by the entity that issued the memory command, but includes several internal memory operations, for example, multiple memory storage access operations. Although an atomic memory command is issued to the memory, the memory internally performs a number of internal memory operations to complete the requested memory operation. For example, IO interface 110 receives the command packet and packet decoder 120 decodes a memory command for an atomic memory operation. In response, the packet decoder 120 generates internal control and timing signals for managing the operation of the plurality of internal memories (eg, signals representing commands, addresses, operational metadata and masks, data lengths, and data unit size information). ).

An example of an atomic memory operation includes reading data from a memory location, performing an arithmetic operation by providing an operation element to the memory and the read data, and writing the result back to initially reading the data. A memory operation of the memory location. In some embodiments of the invention, the atomic memory operation has two operational versions: one version performs the requested memory operation and writes the result back to the original memory location; and the other version is the execution The requested memory operates and provides the result as output from one of the memories in addition to rewriting the result to the original memory location. Other examples of atomic memory operations are set forth below.

2 illustrates various portions of a command packet 200 in accordance with an embodiment of the present invention. One of the command portions of the packet 200 can include a command field 210, and one of the configuration portions of the packet 200 can include, for example, a data length field 220, a data unit size field 230, and/or a mask field 240. . The command packet 200 can be provided to a memory (e.g., memory 100 of FIG. 1) to request execution of a memory command, as previously discussed. Command packet 200 may include other portions that are well known or later developed, in addition to those portions of the particular display shown in FIG. However, the specifically identified fields in Figure 2 will be explained in detail herein. It will be appreciated that, although specific examples of the field and the size of the field are set forth below, the invention is not limited thereto, and for example, the field size may be variable without departing from the scope of the invention. Can be bigger or smaller. Command packet 200 includes a command field (CMD) 210. The CMD field 210 is used to provide a command decoded by the command decoder to perform an operation. In the embodiment illustrated in Figure 2, the CMD field 210 is [(N-M) + 1] bits in length. In some embodiments, the CMD field 210 is 6 bits long. The command packet 200 further includes a data length field (LNG) 220 for specifying one of the total lengths of data (not shown) associated with the command packet. In the particular embodiment illustrated in Figure 2, the LNG field 210 is [(P-O) + 1] bits in length. In some embodiments, the LNG field is 5 bits long. The value defined by the LNG field 210 may correspond to a code representing the total length of the data. For example, the following definitions can be used in one embodiment of the invention:

Therefore, a value of 1 in the LNG field 220 defines the total data length of the packet as 8 bytes long. In the event that one of the memory commands defined by CMD field 210 does not require data, a value of 0 may be provided in LNG field 220 to indicate that no data is associated with the packet.

The command packet 200 further includes a data unit size field (SIZ) 230. In the embodiment illustrated in Figure 2, the SIZ field 230 is [(R-Q) + 1] bits in length. In one embodiment of the invention, the SIZ field 230 is 3 bits long. The value contained in SIZ field 230 is defined by the number of bytes, for example, the size of each data unit. For example, the following definitions can be used in one embodiment of the invention:

Therefore, a value of 3 in the SIZ field 230 defines the data unit size as 4 bytes long. That is, each data unit contained in the packet is 4 bytes in length.

The command packet 200 further includes a mask field (MSK) 240. In the embodiment illustrated in Figure 2, the MSK field 240 is [(T+S) + 1] bits in length. In one embodiment of the invention, the MSK field 240 is 16 bits long. The combination of bits in the MSK field 240 is used to define which of the data elements in the packet are masked. In some embodiments, one of the bit positions of the MSK field 240 "1" indicates that the corresponding data unit should be masked and one of the bit positions of the MSK field 240 "0" indicates the corresponding data unit. Should not be masked. A value of "1" in the mask field prevents the operation defined in the command field from occurring on a separate data unit. A value of "0" allows the operation to occur on the respective data unit.

The LNG, SIZ, and MSK fields 220, 230, 240 individually and together provide configuration information relating to the data that is manipulated by the memory commands provided in the CMD field 210. The following non-limiting examples will be used to illustrate the interaction of the definitions of the fields 220, 230, 240.

Assuming an example command packet, the value in the LNG field 220 is 2 to define a total data length of one of the 16 bytes, and the value in the SIZ field 230 is 1 to define the size of the data unit as 1 Bytes. Thus, there is a total data length of one of 16 bytes and a data unit size of one of the bytes, and the example packet contains 16 data units. Assuming one of the MSK field 240 bit combinations: (MSB) 1010 1010 1010 1010 (LSB), the 16 data elements provided as data are masked such that the first data unit is not masked (first cover) The mask bit is a "0" and the second data unit is masked (the second mask bit is a "1"). Every other data unit (ie, byte groups 4, 6, 8, 10, 12, 14, and 16) of the remaining data units (ie, byte 3 to byte 16) is masked, and The remaining data units (ie, bytes 3, 5, 7, 9, 11, 13, and 15) are not masked. If the command indicated is added, each unmasked data byte adds a corresponding data item to the memory data bit before rewriting the unmasked data bytes back to the memory. group. The masked memory data byte has not been modified.

In another embodiment, the bit of the MASK field 240 starting with the LSB corresponds to a respective data unit as defined by the SIZ field 230. For example, assume that an example command packet has a value of 2 for the LNG field 220 to define a total data length of one of the 16 bytes, and a value of 2 in the SIZ field 230 to define the data unit size as 2 One byte. Therefore, in the case of having a total data length of one of 16 bytes and a data unit size of one of the two bytes, the example packet contains data of eight data units. Assume that one of the MSK field 240 bits is: (MSB) 1111 1111 0110 0110 (LSB), and the eight data units provided for the data are masked to make the first, fourth, fifth and eighth data The unit is not masked and the second, third, sixth and seventh data units are masked. The most significant 8 bits of the MSK value are "1", but since the number of data units of the example packet is 8, only the least significant 8 bits of the MSK value are used for the masking operation. Although specific examples have been set forth, other configurations relating to configuration information for the data may be used without departing from the invention.

FIG. 3 illustrates a packet decoder 300 in accordance with an embodiment of the present invention. The packet decoder 300 can be used as the packet decoder 120 of the memory 100 of FIG. The packet decoder 300 receives a command packet from an IO interface (eg, the IO interface 110). The command packet includes, among other things, a memory command and configuration information (eg, related to the total data length, data unit size, and masking). Cover information information). In some embodiments, packet decoder 300 receives command packet 200 of FIG.

The packet decoder 300 receives information relating to the data associated with the command packet, for example, information provided by the LNG, SIZ, and MSK fields of the command packet 200. The packet decoder 300 decodes the values in the various fields and generates an internal signal representing the command, address, operand data and data length, data unit size, and mask information from the packet. As will be explained in more detail below, the decoded information can be used to perform operations on the data associated with the command packet.

Figure 4 illustrates one of the operational logics 400 in accordance with one embodiment of the present invention. Operational logic 400 can be used for operational logic 140 of memory 100 of FIG. The operational logic 400 includes a first selector 410 configured to receive the read data from the memory store and further receive one of an address, a data length, and a data unit size information associated with a command packet. The first selector 410 provides the read data to an operating unit 420 and a second selector 430. The operating unit 420 configures the data according to the address, data length, and data unit size information to be provided to the operating unit 420. For example, a selected portion of the information identified by the information is provided to the operation unit 420. The same configured data is also provided to a second selector 430. The operation unit 420 further receives the operation metadata and the command associated with the command packet and performs various operations on the read data and/or the operation metadata in accordance with the command. Example operations are set forth in greater detail below.

The resulting data from the operating unit 420 is provided to the second selector 430. The second selector uses the mask, data length, and data unit size information associated with the command packet to provide information for returning to the requesting device and/or for storage in the memory storage device (wherein the data can be A combination or part of any of the information read, the data obtained, or the above information). The data can be provided to the memory storage and/or prepared to be returned through an IO interface (eg, IO interface 110, Figure 1). In some embodiments, which information is provided by the second selector 430 is based, at least in part, on information from the command packet. For example, if a mask bit is "0", the second selector 430 provides a corresponding portion of the obtained data, whereas for a "1", a corresponding portion of the read data is provided. In some embodiments, data different from the material stored in the memory store is returned to a request processor based at least in part on how the atomic operation is defined.

In the embodiment shown in FIG. 4, operating unit 420 is operative to perform arithmetic operations. For example, in one embodiment of the invention, operating unit 420 is operable to perform arithmetic operations on two 32-bit values. The operating unit 420 is operable to perform a logical operation on the material. For example, in one embodiment of the invention, operating unit 420 is operative to perform logical operations on a 64-bit value.

In an embodiment of the invention, the operating unit 420 is operative to perform the following arithmetic operations.

In an embodiment of the invention, operating unit 420 is operative to perform the following logical operations.

The operating unit can also perform other logical operations. For example, comparison logic operations (such as swap and store operations) and other operations can be performed. The comparison logic operation compares the two values and makes a determination as to which of the two values is larger or smaller (or, in some embodiments, whether the two values are equal). By comparing and exchanging logic operations, it can be selected to store the larger or smaller value.

As previously explained, in operation, the first selector 410 uses the address, LNG, and SIZ values to configure the read data for operation by the operating unit 420. For example, assuming that the operation unit 420 can perform operations of up to two 32-bit data items, the operation unit 420 can be used to perform, for example, 4×1 bytes, 2×2 bytes, or 1×4 bytes. The operation of the operational logic. That is, in the case where the data unit size is 1 byte, the operation unit 420 can operate on two sets of 4×1 byte operands. In another example, in the case where the data unit size is 4 bytes, the operating unit 420 can operate on two sets of 1×4 byte data operands.

As explained further above, the MSK value can be used to mask or not mask the data elements of the data associated with a package, which are defined by SIZ values. In operation, the MSK and SIZ values can be used to select a particular data unit of data to be provided by the second selector 430. For example, when an MSK value is applied, the data unit of the material can be selectively provided by the second selector 430. This operation can be illustrated by considering an example as previously explained. In a previously illustrated example, it is assumed that the total data length is 16 bytes and the size of the data unit is 1 byte, resulting in an exemplary packet of associated data having data containing 16 data units. . The instance MSK value does not mask the data unit of the first and every other byte length, but masks the data unit of the second and every other byte length. The first, third, fifth, seventh, ninth, eleventh, thirteenth and fifteenth data units when used in the selection of specific data units (16-bit long units) That is, it is possible that 8 of the data units of the 16-bit group length are provided by the second selector 430.

It will be apparent that the particular embodiments of the invention have been described herein by way of illustration, Accordingly, the invention is not limited except in the scope of the accompanying claims.

100. . . Memory

110. . . IO interface

120. . . Packet decoder

130. . . Memory storage

140. . . Operational logic

150. . . Packet combiner

200. . . Command packet

210 (CMD). . . Command field

220 (LNG). . . Data length field

230 (SIZ). . . Data unit size field

240 (MSK). . . Mask field

300. . . Packet decoder

410. . . First selector

420. . . Operating unit

430. . . Second selector

1 is a block diagram of a memory in accordance with an embodiment of the present invention.

2 is a diagrammatic representation of one of the portions of a command packet in accordance with an embodiment of the present invention.

3 is a block diagram of a packet decoder in accordance with an embodiment of the present invention.

4 is a block diagram of one of the operational logics in accordance with an embodiment of the present invention.

100. . . Memory

110. . . IO interface

120. . . Packet decoder

130. . . Memory storage

140. . . Operational logic

150. . . Packet combiner

Claims (27)

A memory comprising: a command decoder configured to receive a command packet, each of the command packets having at least one memory command portion in which a memory command is provided and providing a correlation therein And a configuration portion of the configuration information of the data associated with a command packet, the command decoder being further configured to generate the command control signal based at least in part on the memory command and further configured to at least partially Generating a configuration control signal based on the configuration information; and operating logic configured to receive the data associated with the command packet from a memory storage, and control signals and the configuration control signal in accordance with the command Performing an atomic operation on the data, the operational logic comprising: a first selector configured to configure the data in accordance with the configuration control signal; an operating unit configured to control the signal pair in accordance with the command The configured data performs the atomic operation to generate a resultant; and a second selector for receiving the configured from the first selector And receiving the result from the operating unit, and configured to pass the resulting portion that is not masked by the configuration information to a packet combiner for delivery to one of the components external to the memory, and the group Transmitting the resulting portion of the configuration information mask to the memory storage, wherein the component is sent to the external portion of the memory The portion of the resulting portion is different from the portion of the resulting portion stored in the memory reservoir. The memory of claim 1, wherein the command decoder comprises: a packet decoder configured to receive a command packet including at least mask control information as the configuration information, wherein the second selector is based on the mask The cover control information determines which portions of the result are unmasked. The memory of claim 2, wherein the packet decoder is configured to receive mask control information of 16 bits. The memory of claim 2, wherein the mask control information selectively enables a mask for each data unit from the data obtained from the atomic operation and wherein the operational logic is configured to select information based on the mask control information Information element of one of the obtained materials is provided sexually. The memory of claim 1, wherein the command decoder comprises: a packet decoder configured to receive data length information including at least partially defining a length of the data associated with a respective command packet The command packet. The memory of claim 5, wherein the command decoder is configured to receive data length information defining the length of the data as one of 0 bytes, 8 bytes, or 16 bytes. The memory of claim 1, wherein the command decoder comprises: a packet decoder configured to receive a size of at least one of the data units at least partially defining the data associated with a respective command packet The command packet of the data unit size information. The memory of claim 7, wherein the command decoder is configured to receive The data unit size is defined as a unit size information in units of bytes. The memory of claim 8, wherein the command decoder is configured to receive the data unit size as 0 bytes, 1 byte, 2 bytes, 4 bytes, Data unit size information for 8 or 16 bytes. The memory of claim 1, wherein the command decoder is further configured to receive and decode the atomic memory command and configured to manage a plurality of internal operations to execute the atomic memory command. The memory of claim 1, wherein the operational logic is further configured to perform an operation on the received data under mask control based at least in part on the configuration control signal provided by the command decoder. The memory of claim 11, wherein the configuration control signal comprises a plurality of configuration control signals and wherein the command decoder is configured to generate the groups based at least in part on data length, data unit size, and data mask information State control signal. A memory comprising: operation logic configured to perform an atomic operation on a command and an operation metadata to provide the obtained data, wherein the atomic operation is in accordance with at least a data size and a mask configuration. Executing a configuration instruction, the operation logic includes: a data configuration unit for receiving the data and the configuration instruction, and configured to configure the data according to the configuration instruction; an operation unit, It is used to receive the group from the data configuration unit State data and receiving the command and the metadata, and configured to perform the atomic operation on the configured data and the operational metadata in accordance with the command to generate a result; and a data selector Reconfiguring to receive the configuration command and the resulting, and further configured to select a data unit from the resulting mask based on the mask configuration, wherein the mask configuration determines which of the obtained data units are to be Memory storage, and the data selector is further configured to determine which of the obtained data units are to be returned to a request processor; a command decoder coupled to the operational logic and configured to receive the command and Further configured to receive configuration information relating to the operational metadata and/or the resulting data, the command decoder configured to generate internal control and timing signals for performing the atomic memory operation; and a packet a combiner configured to receive from the operational logic the derived data units to be returned to the requesting processor, and further configured to be returned from the request This is obtained from the combination of such data units to send a data packet to the requesting processor, wherein the combined data packet is different from the data obtained from those of the storage unit of the memory. The memory of claim 13, wherein the command and configuration information is provided to the command decoder in a packetized format. As in the memory of claim 13, wherein the operational logic is further configured to perform an arithmetic operation. The memory of claim 15, wherein the operational logic is configured to execute At least one of the following arithmetic operations: adding 1 to the data read from a memory storage; subtracting 1 from the data read from the memory storage; adding the operational metadata to the The data read by the memory storage; and subtracting the operational metadata from the data read from the memory storage. As in the memory of claim 13, wherein the operational logic is further configured to perform a logical operation. The memory of claim 17, wherein the operational logic is configured to perform at least one of: clearing a bit; setting a bit; and switching the bit. The memory of claim 13, wherein the operational logic is further configured to perform an arithmetic operation on up to two 16-bit data values. The memory of claim 13, wherein the operational logic is further configured to perform an operation on the data based at least in part on a data unit size parameter. A method of performing an atomic memory operation, comprising: receiving a command packet for an atomic memory operation, wherein the command packet includes at least one command operation, a memory storage address, and a configuration portion; receiving and The atomic memory operation is associated with the mask control information, wherein the mask control information is also included in the command packet; Configuring, according to the configuration part, the data associated with the memory storage address according to the configuration part of the command packet; performing the atomic memory operation on the configured data according to the command operation to generate a result; controlling based on the mask The information is stored in the memory storage address; and a data packet is prepared from the result for providing to a request processor, wherein the data packet is different from being stored in the memory storage address Different parts of the income. The method of claim 21, further comprising configuring the operational metadata to perform the atomic memory on the operational metadata based at least in part on a length of the operational metadata and a size of one of the operational metadata operating. The method of claim 22, further comprising receiving information relating to the size of the data unit associated with the command. The method of claim 21, further comprising providing the length of the operational metadata and the size of the data unit for the command for the atomic memory operation. The method of claim 21, wherein the performing the operation comprises performing an arithmetic operation on the operational metadata and the data retrieved from the memory. The method of claim 21, wherein performing the operation comprises performing a logical operation on the operational metadata. The method of claim 21, wherein the performing the operation comprises performing at least one of the logical operations of comparing, exchanging, storing, or a combination thereof with the operational metadata.