TWI459696B - Power factor correction boost converter and frequency switching modulation method thereof - Google Patents

Description

Power factor correction boost converter and switching frequency modulation method thereof

The present invention relates to a power factor corrector, and more particularly to a power factor modified boost converter (PFC Boost converter) for use in a high efficiency switched power supply.

In recent years, the promotion of environmental awareness and global warming have forced energy conservation to become one of the important policies of all countries in the world. The US Environmental Protection Agency (EPA) has relatively high efficiency specifications for various information electronic devices to achieve energy-saving goals, such as 80+ basic requirements on PC power supplies (80%, 80%). , 80%), Bronze (82%, 85%, 82%), Silver (85%, 88%, 85%), Gold (87%, 90%, 87%) certification, so improving the efficiency of the power converter is The problem we must overcome now.

In power electronics applications, AC to DC converters are widely used. For example, home appliances and computers need to use AC to DC converters to convert AC power to DC power. The power supply industry based on existing computers has been moving toward a trend of high efficiency and high power. Therefore, in the design of power circuits, there is a fairly stringent requirement for the power factor of electronic devices. Since there are many nonlinear components in the AC-to-DC converter, such as bridge rectifier filters, it is necessary to use a power factor corrector to adjust the phase of the output voltage and the output current to improve the power factor. Among them, the power factor correction boost converter is one of the most common architectures.

The general converter adopts CCM average current mode fixed frequency control, so that the switching frequency of the power supply is constant regardless of the output voltage under any load. For light and medium loads of switched power supplies, higher switching frequencies are not a good operation because they increase the switching loss, driver loss and magnetic properties of the power transistors. The core loss of the component affects the conversion efficiency of the overall power supply. Therefore, how to reduce the power consumption of the switching power supply during switching has become an important research direction of power electronics.

The invention provides a power factor correction boost converter, which is suitable for using a power factor correction power converter of a boost converter, which is controlled by a control unit, so that the switching frequency of the converter is adjustable, and can be adjusted according to the output load. The switching frequency is used to reduce the switching loss of the power switch and the fixed loss of the magnetic component, thereby improving the conversion efficiency of the power converter.

The present invention provides a power factor correction boost converter for generating power to a voltage converter. The power factor correction boost converter includes a power factor correction conversion unit and a control unit. The power factor correction conversion unit adjusts the power output to the voltage converter according to a pulse width modulation signal. The control unit is coupled to the power factor correction conversion unit, and adjusts the frequency of the pulse width modulation signal according to an output load of the power factor correction conversion unit. Wherein, when the output load of the power factor correction conversion unit is increased, the control unit increases the frequency of the pulse width modulation signal; when the output load of the power factor correction conversion unit decreases, the control unit decreases the frequency of the pulse width modulation signal .

In an embodiment of the invention, the control unit includes a current detecting circuit, a voltage detecting circuit, and a control circuit. The current detecting circuit is configured to generate a first detection signal corresponding to an output load current of the power factor correction conversion unit. The voltage detecting circuit is configured to generate a second detection signal corresponding to an output load voltage of the power factor correction conversion unit. The control circuit is coupled to the current detection circuit and the voltage detection circuit, and adjusts the frequency of the pulse modulation signal according to the first detection signal/second detection signal. Wherein, when the load current of the power factor correction conversion unit is less than a first preset value or the output load voltage of the power factor correction conversion unit is less than a second preset value, the control circuit reduces the frequency of the pulse width modulation signal to Reduce the switching loss of the power factor correction converter. On the contrary, when the output load current of the power factor correction conversion unit is greater than a first preset value or the output load voltage of the power factor correction conversion unit is greater than a second preset value, the control circuit increases the frequency of the pulse width modulation signal. .

From another point of view, the present invention further provides a switching frequency modulation method for a power factor correction boost converter, wherein the power factor correction boost converter adjusts the output to a voltage converter according to a pulse width modulation signal. The power frequency modulation method includes the following steps: detecting an output load of the power factor correction boost converter; detecting a change of the output load, and increasing the pulse width when the output load of the power factor correction boost converter is increased. The frequency of the modulated signal; when the output load of the power factor correction conversion unit decreases, the frequency of the pulse width modulation signal is reduced.

In summary, the power factor correction boost converter proposed by the present invention can adjust the switching frequency according to the output load. When the load is low, the controller actively reduces the switching frequency to reduce the switching loss of the power factor correction boost converter. Especially at medium and light loads, the present invention automatically operates at lower switching frequencies to reduce power loss.

The above described features and advantages of the present invention will be more apparent from the following description.

In the following, the invention will be described in detail by the embodiments of the invention, and the same reference numerals are used in the drawings.

(First Embodiment)

Please refer to FIG. 1A. FIG. 1A is a functional block diagram of a power factor correction boost converter according to a first embodiment of the present invention. The power factor modified boost converter 100 can generate power to the back end voltage converter 150 and then convert it to a DC voltage via the voltage converter 150 for use by the system or electronic device. The power factor correction boost converter 100 includes a control unit 101 and a power factor correction conversion unit 140, wherein the power factor correction conversion unit 140 may be, for example, a CCM power factor correction converter. The control unit 101 further includes a control circuit 110, a current detecting circuit 120, and a voltage detecting circuit 130. The current detecting circuit 120 is configured to generate a first detection signal DS1 corresponding to the output load current of the power factor correction conversion unit 140, and the voltage detecting circuit 130 is configured to generate an output load corresponding to the power factor correction conversion unit 140. The second detection signal DS2 of the voltage.

The control circuit 110 adjusts the frequency of the pulse width modulation signal PWM according to at least one of the first detection signal DS1 and the second detection signal DS2. That is, the control circuit 110 can adjust the frequency of the pulse width modulation signal PWM according to the first detection signal DS1 or the second detection signal DS2. When the output load of the power factor correction conversion unit 140 is increased, the control unit 101 increases the frequency of the pulse width modulation signal PWM; when the output load of the power factor correction conversion unit 140 decreases, the control unit 101 decreases the pulse width modulation. The frequency of the signal PWM is varied to reduce the switching loss of the power factor correction conversion unit 140.

The load variation of the power factor correction conversion unit 140 can be determined via an output load voltage or an output load current, wherein the output load of the power factor correction conversion unit 140 can be expressed as a product of the output load voltage and the output load current, that is, the output power. In this embodiment, when the output load current of the power factor correction conversion unit 140 is less than a first preset value or the output load voltage of the power factor correction conversion unit 140 is less than a second preset value, the control circuit 110 lowers the pulse. The wave width modulates the frequency of the signal to reduce the switching loss of the power factor converter. On the contrary, when the output load current of the power factor correction conversion unit 140 is greater than a first preset value or the output load voltage of the power factor correction conversion unit 140 is greater than a second preset value, the control circuit 110 increases the pulse width modulation. The frequency of the signal. In addition, the control circuit 110 may also adjust the switching frequency of the power factor correction conversion unit 140 in a progressive manner such that the frequency of the pulse width modulation signal PWM changes with the load of the power factor correction conversion unit 140. When the load increases, the frequency of the pulse width modulation signal PWM is increased, and when the load is decreased, the frequency of the pulse width modulation signal PWM is decreased. The manner in which the control circuit 110 adjusts the pulse width modulation signal PWM may vary according to design requirements and circuit architecture. This embodiment is not limited to the above description.

The current detecting circuit 120 can detect the output load current of the power factor correction conversion unit 140 (indicated by a solid line) or directly detect the output current of the power factor correction conversion unit 140 via the current of the voltage converter 150 at the rear end ( The dotted line indicates) to generate the first detection signal DS1. Similarly, the voltage detecting circuit 130 can generate the second detecting signal DS2 or directly detect the power via the VEAO (shown by the solid line) signal corresponding to the output voltage of the power factor correction converting unit 140 generated by the control circuit 110. The output voltage of the factor correction conversion unit 140 (indicated by a broken line) is used to generate the second detection signal DS2. Since the circuit and the method of the voltage detection and the current detection have various implementation manners, the embodiment does not limit the circuit architecture and the coupling manner of the current detection circuit 120 and the voltage detection circuit 130, as long as the power factor can be detected. The output load voltage/output load current of the conversion unit 140 may be corrected. In a typical PWM controller, such as Champion's CM6802, the VEAO signal is the output voltage of the error amplifier, which is related to the output voltage of the power factor correction conversion unit 140. In the specification of CM6802, VEAO is output by Pin 16, which represents (PFC transconductance voltage amplifier output).

The power factor correction conversion unit 140 controls the switching of the power switch (not shown) according to the pulse width modulation signal generated by the control circuit 110 to adjust the power output to the voltage converter. In the present embodiment, the power factor correction conversion unit 140 is, for example, a boost type power factor correction converter, which is mainly composed of a bridge rectifier and a booster circuit. Referring to FIG. 1B, a circuit diagram of a boost type power factor correction converter according to a first embodiment of the present invention is shown. The power factor correction conversion unit 140 is mainly composed of a bridge rectifier 142, an inductor L1, a transistor Q1, a diode D1, and an output capacitor C1. The bridge rectifier 142 rectifies the received alternating current VAC. The inductor L1, the transistor Q1, the diode D1, and the output capacitor C1 constitute a booster circuit, and generate different output voltages OUT according to the duty cycle of the pulse width modulation signal PWM. After the description of the above embodiments, those skilled in the art should be able to infer the implementation of the power factor correction conversion unit 140, and no further details are provided herein. The voltage conversion unit 150 is a DC/DC converter, such as a PWM converter or a resonant converter.

Next, a circuit diagram of the current detecting circuit 120 and the voltage detecting circuit 130 will be described. Please refer to FIG. 2. FIG. 2 is a schematic circuit diagram of the current detecting circuit 120 according to the first embodiment of the present invention. The current detecting circuit 120 includes resistors R21 to R28, comparators COM21 to COM22, capacitors C21 to C23, and a programmable shunt regulator 211. Resistor R21 is used to sense the primary side current of the transformer in voltage converter 150. In terms of circuit structure, the resistor R21 is coupled to the voltage converter 150, for example, between a switch (not shown) connected to the primary side of the transformer and the ground GND. In general, the voltage converter 150 has a transformer and a power transistor (switch). The resistor R21 can be coupled to one end of the power transistor to extract the current IS (IS) of the transformer on the primary side of the transformer. The current flows through the resistor R21 to be amplified to a desired signal) which is related to the output load current of the power factor correction conversion unit 140. The resistor R21 is mainly used to sense the output load current of the power factor correction conversion unit 140. In different circuit architectures, the resistor R21 can be coupled to different terminals to draw the current of the load according to design requirements. This embodiment does not Limited to Figure 2.

The positive input terminal of the comparator COM21 is coupled to the contact of the resistor R21 and the switch via a resistor R22, and the negative input terminal thereof is coupled to the ground GND via a resistor R23. The resistor R24 is coupled between the output of the comparator COM21 and the negative input of the comparator COM21. One end of the resistor R25 is coupled to the output end of the comparator COM21, and the other end of the resistor R25 is coupled to the positive input terminal of the comparator COM22. The output of the comparator COM22 is used to output the first detection signal DS1. The resistor R26 is coupled between the negative input terminal of the comparator COM22 and the capacitor C21. The other end of the capacitor C21 is coupled to the ground GND. The resistor R27 is coupled between the output of the comparator COM22 and the positive input of the comparator COM22. The resistor R28 is coupled between an operating voltage VCC and a cathode of the programmable shunt regulator 211. The anode of the programmable shunt regulator 211 is coupled to the ground GND, and the reference end of the programmable shunt regulator 211 is coupled to the cathode of the programmable shunt regulator. The junction of the resistor R26 and the capacitor C21 is coupled to the cathode of the programmable shunt regulator 211. The capacitor C22 is coupled between the positive input terminal of the comparator COM21 and the ground GND. The capacitor C23 is coupled between the positive input terminal and the negative input terminal of the comparator COM21. The programmable shunt regulator 211 is, for example, a TL431 voltage regulator manufactured by Texas Instruments (TI). For the component description, please refer to the data sheet, and no further description is provided here.

Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of the voltage detecting circuit 130 according to the first embodiment of the present invention. The voltage detecting circuit 130 includes resistors R31 to R35, capacitors C31 to C33, comparators COM31 to COM32, and a programmable shunt regulator 311. One end of the resistor R31 is coupled to a VEAO (voltage error amplifier output voltage, VEAO is proportional to the output load) corresponding to the output voltage of the power factor correction conversion unit 140. Some controllers (refer to Figure 4) use the output voltage of the power factor correction converter as a feedback voltage and generate VEAO based on the feedback voltage. The voltage detecting circuit 130 can use the VEAO to detect the output load voltage of the power factor correction conversion unit 140. It should be noted that the voltage detecting circuit 130 can also obtain the VEAO corresponding to the output load voltage of the power factor correction converting unit 140 via other endpoints according to the circuit architecture. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

The positive input terminal of the comparator COM31 is coupled to the other end of the resistor R31, and the negative input terminal thereof is coupled to the output terminal of the comparator COM31. One end of the resistor R32 is coupled to the output end of the comparator COM31, and the other end is coupled to the positive input terminal of the comparator COM32. The positive input terminal of the comparator COM32 is coupled to the output of the comparator COM32 via a resistor R33. The resistor R34 is coupled between the negative input terminal of the comparator COM32 and the capacitor C31. The other end of the capacitor C31 is coupled to the ground GND. The resistor R35 is coupled between an operating voltage VCC and a cathode of the programmable shunt regulator 311. The anode of the programmable shunt regulator 311 is coupled to the ground GND. The reference end of the programmable shunt regulator 311 is coupled to the cathode of the programmable shunt regulator 311, wherein the junction of the resistor R34 and the capacitor C31 is coupled to the cathode of the programmable shunt regulator 311. The capacitor C32 is coupled between the positive input terminal and the negative input terminal of the comparator COM31. The capacitor C33 is coupled between the positive input terminal of the comparator COM32 and the ground GND.

In addition, the internal structure of the control circuit 110 may have different circuit architectures depending on the control IC used. The control IC is, for example, a high voltage resonant control chip of STMicroelectronics (ST) (for example, model L6599) or Campion. The implementation of the control IC such as CM6802 or CM6502 does not limit the type of control IC used in this embodiment. Those skilled in the art should be able to infer from the above description that a suitable control IC and its peripheral circuits are not described herein. The control IC in this embodiment is exemplified by CM6802 or CM6502. Please refer to FIG. 4. FIG. 4 is a schematic diagram showing the main internal circuit of the control circuit 110 according to the first embodiment of the present invention. The control circuit 110 mainly includes a first frequency control circuit 410, a second frequency control circuit 420, and a controller 430. The peripheral circuit of the controller 430 can refer to the data sheet of the IC, which is not shown in FIG. 4 . The controller 430 has pins P1 P P3, wherein the pin P1 outputs a VEAO (voltage error amplifier output voltage) corresponding to the output load voltage of the power factor correction conversion unit 140; the pin P2 can output a fixed reference voltage VREF; P3 is the frequency setting pin. The controller 430 adjusts the frequency of the pulse width modulation signal PWM according to the impedance value coupled to the frequency setting pin P3. The pin P1 is, for example, a pin 16 in Champion's CM6802 controller. The pin P2 is, for example, a pin 14 in the CM6802 controller, and the pin P3 is, for example, a pin 7 or 8 in the CM6802 controller.

The resistor RT is coupled between the pin P2 of the controller 430 and the pin P3, and the capacitor CT is coupled between the pin P3 of the controller 430 and the ground GND. The frequency of the pulse width modulation signal PWM output by the controller 430 changes with the resistance RT and the capacitance CT. The first frequency control circuit 410 is coupled to both ends of the resistor RT (the first terminal T1 of the resistor RT and the second terminal T2 of the resistor RT), that is, the pins P2 and P3 of the controller 430. The second frequency control circuit 420 is also coupled to both ends T1 and T2 of the resistor RT. The first frequency control circuit 410 adjusts the equivalent resistance across the resistor RT according to the first detection signal DS1 (representing the output load current of the power factor correction conversion unit 140). In this embodiment, the first frequency control circuit 410 selectively parallels another resistor to both ends of the resistor RT to change the impedance value received by the pin P3, thereby adjusting the frequency of the pulse width modulation signal PWM. Similarly, the second frequency control circuit 420 selectively parallels another resistor to both ends of the resistor RT according to the second detection signal DS2 (representing the output load voltage of the power factor correction conversion unit 140) to adjust the pulse width modulation. The frequency of the signal PWM.

Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a first frequency control circuit 410 according to the first embodiment of the present invention. The first frequency control circuit 410 includes NMOS transistors Q51, Q55, PNP transistor Q52, NPN transistors Q53 to Q54, resistors R51 to R59, and a capacitor C51. The gate of the NMOS transistor Q51 is coupled to the first detection signal DS1, and the source thereof is coupled to the ground GND. The resistor R51 is coupled between the gate of the NMOS transistor Q51 and the ground GND. The capacitor C51 is coupled between the gate of the NMOS transistor Q51 and the ground GND. The emitter of the PNP transistor Q52 is coupled to an operating voltage VCC. The resistor R52 is coupled between the emitter of the PNP transistor Q52 and the base of the PNP transistor Q52. The resistor R53 is coupled between the base of the PNP transistor Q52 and the drain of the NMOS transistor Q51. One end of the resistor R54 is coupled to the collector of the PNP transistor Q52. The resistor R55 is coupled between the other end of the resistor R54 and the ground GND.

Furthermore, one end of the resistor R56 is coupled to the emitter of the PNP transistor Q52, and the other end is coupled to the collector of the NPN transistor Q53. The base of the NPN transistor Q53 is coupled to the junction of the resistor R54 and the resistor R55, and the emitter is coupled to the ground GND. The resistor R57 is coupled between the collector of the NPN transistor Q53 and the ground GND. The base of the NPN transistor Q54 is coupled to the collector of the NPN transistor Q53, and the emitter is coupled to the ground GND. The resistor R58 is coupled between the collector of the PNP transistor Q52 and the collector of the NPN transistor Q54. The gate of the NMOS transistor Q55 is coupled to the collector of the PNP transistor Q52, and the source thereof is coupled to the frequency setting pin of the controller 430 (ie, P3). The resistor R59 is coupled between the pin P2 of the controller 430 and the drain of the NMOS transistor Q55.

The resistor R59 and the NMOS transistor Q55 are coupled to the two ends T1 and T2 of the resistor RT. When the first detection signal DS1 indicates that the output load current is greater than the first preset value, the NMOS transistor Q55 is turned on, and the parallel connection of the resistor R59 and the resistor RT reduces the equivalent impedance of the two ends T1 and T2. The controller 430 will change the switching frequency set point accordingly to increase the frequency of the PWM of the pulse width modulation signal. On the contrary, when the first detection signal DS1 indicates that the output load current is less than the first preset value, the NMOS transistor Q55 is turned off to increase the equivalent resistance value across the resistor RT. The controller 430 will thereby reduce the frequency of the PWM of the pulse width modulation signal.

Please refer to FIG. 6. FIG. 6 is a schematic circuit diagram of a second frequency control circuit 420 according to the first embodiment of the present invention. The second frequency control circuit 420 includes an input resistor R60, NMOS transistors Q61, Q65, PNP transistor Q62, NPN transistors Q63-Q64, resistors R61-R69, and capacitor C61. The main difference between the second frequency control circuit 420 and the first frequency control circuit 410 is the input resistance R60, and the remaining circuit architectures are similar, and are not described herein. The input resistor R60 is coupled between the second detection signal DS2 and the gate of the NMOS transistor Q61 for transmitting the second detection signal DS2. The resistor R69 and the NMOS transistor Q65 are coupled to the two ends T1 and T2 of the resistor RT. When the second detection signal DS2 indicates that the output load voltage is greater than the second predetermined value, the NMOS transistor Q65 is turned on, and the parallel connection of the resistor R69 and the resistor RT reduces the equivalent impedance of the two ends T1 and T2. The controller 430 will change the switching frequency set point accordingly to increase the frequency of the PWM of the pulse width modulation signal. On the contrary, when the second detection signal DS2 indicates that the output load voltage is less than the second preset value, the NMOS transistor Q65 is turned off to increase the equivalent resistance value across the resistor RT. The controller 430 will thereby reduce the frequency of the PWM of the pulse width modulation signal.

The main function of the first frequency control circuit 410 and the second frequency control circuit 420 is to adjust the impedance value connected to the frequency setting pin P3 of the output load voltage adjustment controller 430 according to the output load current. The implementation of the two circuits is not limited to FIG. 5 and FIG. 6. Those skilled in the art should be able to infer other embodiments from the description of the first embodiment, and no further details are provided herein.

Please refer to FIG. 7. FIG. 7 is a schematic overall circuit diagram of the power factor correction boost converter 100 according to the first embodiment of the present invention. The power factor correction boost converter 100 includes a current detecting circuit 120, a voltage detecting circuit 130, a power factor correction converting unit 140, a voltage converter 150, a controller 430, a first frequency setting circuit 410, and a second frequency setting circuit 420. The circuit implementation details and its connection relationship. The details of the individual circuits can be inferred from the above description of FIGS. 1 to 6 and will not be described herein. In FIG. 7, the power factor correction boost converter 100 can generate a two-stage switching frequency adjustment based on the output load voltage/output load current. When the output load is below a predetermined value, a fixed switching frequency is maintained; when the output load exceeds a predetermined value, the switching frequency is increased to another frequency point. At lower loads, the overall loss is reduced due to the lower switching frequency to increase efficiency. Thereby, the power loss of the power factor correction boost converter 100 at medium and light loads is improved.

In addition, the first frequency control circuit 410 and the second frequency control circuit 420 can adjust the impedance value connected to the frequency setting pin P3 of the controller 430 by another manner. For example, the resistor RT can be implemented by using a variable resistor, and the first frequency control circuit 410 and the second frequency control circuit 420 can adjust the resistance RT according to the output load current and the output load voltage of the power factor correction conversion unit 140, respectively. The resistance value. Such a circuit architecture allows the pulse width modulated signal PWM to have a multi-segment (linear) frequency variation to meet the needs of different output loads. Similarly, the resistors R59 and R69 can also be implemented by using a variable resistor, and the first frequency control circuit 410 and the second frequency control circuit 420 are not only used to control whether the resistors R59 and R69 are connected in parallel to the resistor RT, and the resistor R59 can be controlled. The resistance value of R69. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

(Second embodiment)

There are many types of controllers that generate the pulse width modulation signal PWM. Different types of controllers may have different frequency modulation modes. FIG. 8 is a schematic diagram showing the main internal circuit of the control circuit 110 according to the second embodiment of the present invention. In FIG. 8, the pin P3 of the controller 830 is a frequency setting pin, and the pin P1 thereof can output a VEAO corresponding to the output load voltage of the power factor correction conversion unit 140. The resistor RT is coupled between the pin P3 of the controller 830 and the ground GND. Both ends of the resistor RT are represented by T1 and T2. The controller 830 adjusts the frequency of the pulse width modulation signal PWM according to the impedance value coupled to the pin P3. It should be noted that the present invention does not limit the type of controller, and its peripheral circuits can be set according to design requirements and IC specifications.

The first frequency control circuit 810 and the second frequency control circuit 820 are respectively coupled to the two ends of the resistor RT, and adjust the equivalent impedance across the resistor RT according to the first detection signal DS1 and the second detection signal DS2, respectively. In this embodiment, the first frequency control circuit 810 and the second frequency control circuit 820 adjust the equivalent impedance across the resistor RT by using a parallel connection of resistors. When the output load current of the power factor correction conversion unit 140 exceeds the first preset value, the first frequency control circuit 810 parallels a resistor to both ends T1 and T2 of the resistor RT to reduce the equivalent impedance, and the controller 830 accordingly The switching frequency set point is changed to increase the frequency of the pulse width modulation signal PWM. When the output load voltage of the power factor correction conversion unit 140 exceeds the second preset value, the second frequency control circuit 820 parallels a resistor to both ends T1 and T2 of the resistor RT to reduce the equivalent impedance, and the controller 830 accordingly The switching frequency set point is changed to increase the frequency of the pulse width modulation signal PWM.

Please refer to FIG. 9. FIG. 9 is a schematic circuit diagram of a first frequency control circuit 810 in a second embodiment of the present invention. The first frequency control circuit 810 includes NMOS transistors Q91, Q93, PNP transistor Q92, resistors R91-R95, and capacitors C91-C92. The gate of the NMOS transistor Q91 is coupled to the first detection signal DS1, and the source thereof is coupled to the ground GND. The resistor R91 is coupled between the gate of the NMOS transistor Q91 and the ground GND. The capacitor C91 is coupled between the gate of the NMOS transistor Q91 and the ground GND. The emitter of the PNP transistor Q92 is coupled to the operating voltage VCC. The resistor R92 is coupled between the emitter of the PNP transistor Q92 and the base of the PNP transistor Q92. The resistor R93 is coupled between the base of the PNP transistor Q92 and the drain of the NMOS transistor Q91. The capacitor C92 is coupled between the collector of the PNP transistor Q92 and the ground GND. The resistor R94 is coupled between the collector of the PNP transistor Q92 and the ground GND. The gate of the NMOS transistor Q93 is coupled to the collector of the PNP transistor Q92, and the source thereof is coupled to the T2 terminal of the resistor RT (refer to FIG. 8, the T2 terminal of the resistor RT is also coupled to the ground GND). The resistor R95 is coupled between the drain of the NMOS transistor Q93 and the frequency setting pin (pin P3) of the controller 830.

When the first detection signal DS1 indicates that the output load current is greater than the first preset value, the first frequency control circuit 810 turns on the NMOS transistor Q93, and the resistor R95 is connected in parallel to the two ends T1 and T2 of the resistor RT to reduce the equivalent impedance. The controller 830 changes the switching frequency set point accordingly to increase the frequency of the output pulse width modulation signal PWM.

Please refer to Figure 10. FIG. 10 is a circuit diagram of a second frequency control circuit 820 according to a second embodiment of the present invention. The second frequency control circuit 820 includes an input resistor R00, an NMOS transistor Q01, a Q03, a PNP transistor Q02, resistors R01 to R05, and capacitors C01 to C02. The main difference between the second frequency control circuit 820 and the first frequency control circuit 810 is the input resistance R00, and the remaining circuit architectures are similar, and are not described herein. The input resistor R00 is coupled between the gate of the NMOS transistor Q01 and the second detection signal DS2 for transmitting the second detection signal DS2. Similarly, when the second detection signal DS2 indicates that the output load voltage is greater than the second preset value, the second frequency control circuit 820 turns on the NMOS transistor Q03, and the resistor R05 is connected in parallel to the two ends T1 and T2 of the resistor RT to be lowered. The equivalent impedance, the controller 830 will change the switching frequency set point accordingly to increase the frequency of the output pulse width modulation signal PWM.

Please refer to FIG. 11. FIG. 11 is a schematic overall circuit diagram of a power factor correction boost converter 100 according to a second embodiment of the present invention. The power factor correction boost converter 100 includes a current detecting circuit 120, a voltage detecting circuit 130, a power factor correction converting unit 140, a voltage converter 150, a controller 830, a first frequency setting circuit 810, and a second frequency setting circuit 820. The circuit implementation details and its connection relationship. The details of the individual circuits can be inferred from the descriptions of FIGS. 1 to 3 and FIGS. 8 to 10 described above, and are not described herein.

According to the first embodiment and the second embodiment, the present invention can be summarized as a switching frequency modulation method of a power factor correction boost converter. Referring to FIG. 12, a power factor correction boost according to an embodiment of the present invention is illustrated. Flowchart of a switching frequency modulation method of a voltage converter. The power factor correction boost converter adjusts the power output to the voltage converter based on the pulse width modulation signal. At the same time, the power factor correction boost converter detects the output load of the power factor correction boost converter (step S110), and adjusts the frequency of the pulse width modulation signal according to the change of the output load. When detecting that the output load of the power factor correction boost converter is increased, increasing the frequency of the pulse width modulation signal (steps S120, S140); when detecting that the output load of the power factor correction boost converter is decreased, The frequency of the pulse width modulation signal is lowered (steps S120, S130). The determination of the output load can be determined by the output load current of the power factor correction boost converter and the output load voltage. Therefore, the frequency of the pulse width modulation signal is adjusted according to the power factor correction output load current of the boost converter and the output load voltage. For the remaining implementation details of the switching frequency modulation method, reference may be made to the descriptions of the first embodiment and the second embodiment, and no further details are provided herein.

Next, please refer to FIG. 13, which illustrates a comparison of efficiency data of a power factor correction boost converter and a conventional power factor correction boost converter using an embodiment of the present invention. The AC input power of the test conditions is 100V and the frequency is 60HZ. In the case where the switching frequency modulation technique of the present invention is not used, the switching frequency (Fs) of the conventional power factor correction boost converter is 66 kHz, and at 20% load (light load), the input power (Pin) is 72.05W (watt); at 50% load (middle load), the input power is 176.7W. After switching frequency adjustment using the technique of the present invention, the input power is 71.15 W at 20% load, and the improved switching loss of the present invention is 0.9 W, and the improved conversion efficiency is 1.1%. At 50% load, the input power is 175.8W, the improved switching loss of the present invention is 0.9W, and the improved conversion efficiency is 0.45%. As can be seen from Fig. 13, the power factor correction boost converter of the present invention actually has an effect of improving input power.

The NMOS transistor represents a N channel metal-oxide-semiconductor field-effect transistor; the NPN transistor represents an NPN bipolar junction transistor; and the PNP transistor represents a PNP PNP bipolar junction transistor. The control circuit 110 can be implemented using different controllers (control wafers) whose peripheral circuits are differently designed according to different controllers and are not limited to the above embodiments. Those skilled in the art should be able to know different peripheral circuit architectures through component specifications, and no further details are provided herein.

In addition, it is to be noted that the coupling relationship between the above elements includes a direct or indirect electrical connection as long as the desired electrical signal transfer function can be achieved, and the invention is not limited. The technical means in the above embodiments may be combined or used alone, and the components may be added, removed, adjusted or replaced according to their functions and design requirements, and the invention is not limited. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

In summary, the power factor correction boost converter of the present invention passes through a control unit, so that the switching frequency of the converter is adjustable, and the switching frequency can be adjusted according to the size of the load, thereby reducing the lightness and the medium. Switching losses when carrying (eg 20% load or 50% load). Taking a 320 W power supply as an example, the present invention can reduce the switching loss by about 0.9 W, which is helpful for improving the overall efficiency.

Although the preferred embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and any one of ordinary skill in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention should be determined by the scope of the appended claims.

100. . . Power factor correction boost converter

101. . . control unit

110. . . Control circuit

120. . . Current detection circuit

130. . . Voltage detection circuit

140. . . Power factor correction conversion unit

142. . . Bridge rectifier

150. . . Voltage converter

211, 311. . . Programmable shunt regulator

410, 810. . . First frequency control circuit

420, 820. . . Second frequency control circuit

430, 830. . . Controller

R01~R05, R21~R28. . . resistance

R31~R35, R51~R59. . . resistance

R61~R69, R91~R95, RT. . . resistance

R60, R00. . . Input resistance

COM21~COM22, COM31~COM32. . . Comparators

CO1~C02, C21~C23, C31~C33. . . capacitance

C1, C51, C61, C91~C92. . . capacitance

VEAO. . . Voltage error amplifier output voltage

DS1. . . First detection signal

DS2. . . Second detection signal

D1. . . Dipole

L1. . . inductance

GND. . . Ground terminal

P1~P3. . . Pin

VREF. . . Reference voltage

T1, T2. . . Both ends of the resistor RT

VCC. . . Operating Voltage

Q1, Q01, Q03, Q51, Q55, Q65, Q61. . . NMOS transistor

Q02, Q52, Q62, Q92. . . PNP transistor

Q53~Q54‧‧‧NPN transistor

Q63~Q64‧‧‧NPN transistor

Q91, Q93‧‧‧ NMOS transistor

S110~S140‧‧‧ Flowchart steps

1A is a functional block diagram of a power factor correction boost converter of a first embodiment of the present invention.

FIG. 1B is a circuit diagram of a boost type power factor correction converter according to a first embodiment of the present invention.

2 is a circuit diagram of the current detecting circuit 120 of the first embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a voltage detecting circuit 130 according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram showing the main internal circuit of the control circuit 110 of the first embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a first frequency control circuit 410 according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram of a second frequency control circuit 420 according to the first embodiment of the present invention.

7 is a schematic overall circuit diagram of a power factor correction boost converter 100 according to a first embodiment of the present invention.

FIG. 8 is a schematic diagram showing the main internal circuit of the control circuit 110 according to the second embodiment of the present invention.

FIG. 9 is a circuit diagram of a first frequency control circuit 810 in a second embodiment of the present invention.

FIG. 10 is a circuit diagram of a second frequency control circuit 820 according to a second embodiment of the present invention.

FIG. 11 is a schematic overall circuit diagram of a power factor correction boost converter 100 according to a second embodiment of the present invention.

FIG. 12 is a flow chart showing a method for switching frequency modulation of a power factor correction boost converter according to an embodiment of the invention.

13 is a graph comparing efficiency data of a power factor modified boost converter and a conventional power factor modified boost converter using an embodiment of the present invention.

100. . . Power factor correction boost converter

101. . . control unit

110. . . Control circuit

120. . . Current detection circuit

130. . . Voltage detection circuit

140. . . Power factor correction conversion unit

150. . . Voltage converter

VEAO. . . Voltage error amplifier output voltage

DS1. . . First detection signal

DS2. . . Second detection signal

Claims (15)

A power factor correction boost converter for generating power to a voltage converter, the power factor correction boost converter comprising: a power factor correction conversion unit that adjusts an output to the voltage conversion according to a pulse width modulation signal And a control unit coupled to the power factor correction conversion unit, and adjusting the frequency of the pulse width modulation signal according to the power factor correction conversion unit at least one output load current and/or an output load voltage, And the control unit includes: a current detecting circuit for generating a first detecting signal corresponding to the output load current of the power factor correction converting unit; and a voltage detecting circuit for generating the power factor corresponding to the power factor Correcting a second detection signal of the output load voltage of the conversion unit; and a control circuit coupled to the current detection circuit and the voltage detection circuit, according to the first detection signal and the second detection signal At least one of the frequencies of the pulse modulation signal is adjusted; wherein at least one of the output loads of the power factor correction conversion unit When the current and/or the output load voltage is increased, the control unit increases the frequency of the pulse width modulation signal; when at least one of the output load current of the power factor correction conversion unit and/or the output load voltage decreases, The control unit reduces the frequency of the pulse width modulation signal. The power factor correction boost converter of claim 1, wherein the output load current of the power factor correction conversion unit is less than a first preset value or the output load voltage of the power factor correction conversion unit When less than a second predetermined value, the control circuit reduces the frequency of the pulse width modulation signal. The power factor correction boost converter according to claim 1, wherein the output load current of the power factor correction conversion unit is greater than a first preset value or the output load voltage of the power factor correction conversion unit When it is greater than a second preset value, the control circuit increases the frequency of the pulse width modulation signal. The power factor correction boost converter of claim 1, wherein the current detecting circuit comprises: a first resistor coupled to the voltage converter for sensing a transformer in the voltage converter a primary current, a positive input coupled to the junction of the first resistor and the voltage converter via a second resistor, the negative input coupled to the ground via a third resistor a fourth resistor coupled between the output of the first comparator and the negative input of the first comparator; a fifth resistor having one end coupled to the output of the first comparator; a second comparator having a positive input coupled to the other end of the fifth resistor, an output terminal for outputting the first detection signal, and a sixth resistor coupled to the negative input of the second comparator Between the terminal and the first capacitor, the other end of the first capacitor is coupled to the ground; a seventh resistor is coupled to the output of the second comparator and the positive input of the second comparator An eighth resistor coupled to an operating voltage and a programmable shunt regulator Between the cathodes of the device, the anode of the programmable shunt regulator is coupled to the ground, and the reference end of the programmable shunt regulator is coupled to the cathode of the programmable shunt regulator, wherein the sixth resistor is The contact of the first capacitor is coupled to the programmable parallel regulator a second capacitor coupled between the positive input terminal of the first comparator and the ground terminal; and a third capacitor coupled to the positive input terminal and the negative input terminal of the first comparator between. The power factor correction boost converter according to claim 1, wherein the voltage detecting circuit comprises: a first resistor, one end of which is coupled to the control circuit; and a first comparator whose positive input terminal The other end of the first resistor is coupled to the output of the first comparator; a second resistor coupled to the output of the first comparator; a second comparator The positive input end is coupled to the other end of the second resistor, the positive input end is coupled to the output end of the second comparator via a third resistor, and the output end is configured to output the second detection signal; The fourth resistor is coupled between the negative input terminal of the second comparator and a first capacitor, and the other end of the first capacitor is coupled to the ground terminal; a fifth resistor coupled to an operating voltage and a Between the cathodes of the programmable shunt regulator, the anode of the programmable shunt regulator is coupled to the ground, and the reference end of the programmable shunt regulator is coupled to the cathode of the programmable shunt regulator, wherein The fourth resistor is coupled to the first capacitor and coupled to the programmable parallel a cathode of the voltage regulator; a second capacitor coupled between the positive input terminal of the first comparator and the negative input terminal of the first comparator; and a third capacitor coupled to the first comparator Between the positive input terminal and the ground terminal. The power factor correction boost converter according to claim 1, wherein the control circuit comprises: a controller having a frequency setting pin for adjusting a frequency of the pulse width modulation signal; The first end is coupled to a reference voltage, and the second end is coupled to the frequency setting pin; a capacitor is coupled between the frequency setting pin and a ground; a first frequency control circuit, The current detecting circuit is coupled to the two ends of the resistor and the current detecting circuit, and the impedance value received by the frequency setting pin is adjusted according to the first detecting signal; and a second frequency control circuit coupled to the two resistors And the voltage detecting circuit adjusts the impedance value received by the frequency setting pin according to the second detecting signal; wherein the controller adjusts the pulse width according to the impedance value received by the frequency setting pin The frequency of the modulated signal. The power factor correction boost converter of claim 6, wherein the first frequency control circuit comprises: a first NMOS transistor, the gate of which is coupled to the first detection signal, and a source thereof The first resistor is coupled between the gate of the first NMOS transistor and the ground; a first capacitor coupled to the gate of the first NMOS transistor and the gate Between the grounding ends; a PNP transistor having an emitter coupled to an operating voltage; a second resistor coupled to the emitter of the PNP transistor and the PNP transistor Between the bases of the body; a third resistor coupled between the base of the PNP transistor and the drain of the first NMOS transistor; a fourth resistor coupled to the PNP transistor at one end a fifth resistor coupled between the other end of the fourth resistor and the ground; a sixth resistor having one end coupled to the emitter of the PNP transistor; a first NPN transistor, The collector is coupled to the other end of the sixth resistor, the base is coupled to the junction of the fourth resistor and the fifth resistor, and the emitter is coupled to the ground; a seventh resistor is coupled Between the collector of the first NPN transistor and the ground; a second NPN transistor having a base coupled to the collector of the first NPN transistor, the emitter of which is coupled to the ground; An eighth resistor coupled between the collector of the PNP transistor and the collector of the second NPN transistor; a second NMOS transistor having a gate coupled to the collector of the PNP transistor, The source is coupled to the second end of the resistor; and a ninth resistor coupled between the first end of the resistor and the drain of the second NMOS transistor. The power factor correction boost converter of claim 6, wherein the second frequency control circuit comprises: an input resistor, one end of which is coupled to the second detection signal; a first NMOS transistor, The gate is coupled to the other end of the input resistor, and the source thereof is coupled to a ground end; a first resistor coupled between the gate of the first NMOS transistor and the ground; a first capacitor coupled between the gate of the first NMOS transistor and the ground; a transistor, the emitter of which is coupled to the operating voltage; a second resistor coupled between the emitter of the PNP transistor and the base of the PNP transistor; and a third resistor coupled to the PNP Between the base of the crystal and the drain of the first NMOS transistor; a fourth resistor having one end coupled to the collector of the PNP transistor; and a fifth resistor coupled to the other end of the fourth resistor a sixth resistor, one end of which is coupled to the emitter of the PNP transistor; a first NPN transistor whose collector is coupled to the other end of the sixth resistor, the base coupling Connected to the junction of the fourth resistor and the fifth resistor, the emitter is coupled to the ground; a seventh resistor is coupled between the collector of the first NPN transistor and the ground; a second NPN transistor having a base coupled to the collector of the first NPN transistor and an emitter coupled to the ground; an eighth resistor coupled to the PNP transistor Between the collector and the collector of the second NPN transistor; a second NMOS transistor having a gate coupled to the collector of the PNP transistor, the source of which is coupled to the second end of the resistor; And a ninth resistor coupled to the first end of the resistor and the second NMOS transistor Between the bungee of the body. The power factor correction boost converter according to claim 1, wherein the control circuit comprises: a controller having a frequency setting pin for adjusting a frequency of the pulse width modulation signal; The first end is coupled to the frequency setting pin, the second end is coupled to a ground end, and a first frequency control circuit is coupled to the two ends of the resistor and the current detecting circuit, according to the The first detection signal adjusts the impedance value received by the frequency setting pin; and a second frequency control circuit is coupled to both ends of the resistor and the voltage detecting circuit, and the second detecting signal is adjusted according to the second detecting signal The frequency setting pin receives the impedance value; wherein the controller adjusts the frequency of the pulse width modulation signal according to the impedance value received by the frequency setting pin. The power factor correction boost converter of claim 9, wherein the first frequency control circuit comprises: a first NMOS transistor, the gate is coupled to the first detection signal, and the source is coupled Connected to a ground terminal; a first resistor coupled between the gate of the first NMOS transistor and the ground; a first capacitor coupled to the gate of the first NMOS transistor and the ground Between the terminals; a PNP transistor having an emitter coupled to an operating voltage; a second resistor coupled to the emitter of the PNP transistor and the PNP transistor Between the bases of the body; a third resistor coupled between the base of the PNP transistor and the drain of the first NMOS transistor; and a second capacitor coupled to the collector of the PNP transistor And a fourth resistor coupled between the collector of the PNP transistor and the ground; a second NMOS transistor having a gate coupled to the collector of the PNP transistor, The source is coupled to the second end of the resistor; and a fifth resistor coupled between the drain of the second NMOS transistor and the first end of the resistor. The power factor correction boost converter of claim 9, wherein the second frequency control circuit comprises: an input resistor, one end of which is coupled to the second detection signal; a first NMOS transistor, The gate is coupled to the other end of the input resistor, the source of which is coupled to a ground; a first resistor coupled between the gate of the first NMOS transistor and the ground; a first capacitor Between the gate of the first NMOS transistor and the ground; a PNP transistor having an emitter coupled to an operating voltage; and a second resistor coupled to the emitter of the PNP transistor Between the base of the PNP transistor and a base of the PNP transistor; and a third resistor coupled between the base of the PNP transistor and the drain of the first NMOS transistor; a second capacitor coupled between the collector of the PNP transistor and the ground; a fourth resistor coupled between the collector of the PNP transistor and the ground; a second NMOS transistor The gate is coupled to the collector of the PNP transistor, the source is coupled to the second end of the resistor, and the fifth resistor is coupled to the drain of the second NMOS transistor and the resistor Between one end. The power factor correction boost converter of claim 1, wherein the power factor correction conversion unit is a boost type power factor correction converter. A switching frequency modulation method for a power factor correction boost converter, wherein the power factor correction boost converter adjusts power output to a voltage converter according to a pulse width modulation signal, the switching frequency modulation method comprising: Detecting an output load of the power factor correction boost converter; and detecting a change in the output load; wherein, when the output load of the power factor correction boost converter is increased, increasing the pulse width modulation signal The frequency of the pulse width modulation signal is reduced when the output load of the power factor correction conversion unit of the power factor correction boost converter is decreased; wherein the step of detecting the output load further comprises detecting At least one output load current and/or an output load voltage; wherein the output load of the power factor correction boost converter corresponds to the output load voltage of the power factor correction boost converter and the output load current, the pulse The frequency of the wave width modulation signal is based on the output load voltage and the input At least one of the load currents is adjusted. The switching frequency modulation method of the power factor correction boost converter according to claim 13, wherein when the output load current of the power factor correction conversion unit is less than a first preset value or the power factor correction conversion When the output load voltage of the unit is less than a second preset value, the frequency of the pulse width modulation signal is decreased. The switching frequency modulation method of the power factor correction boost converter according to claim 13 , wherein the output load current of the power factor correction conversion unit is greater than a first preset value or the power factor correction conversion When the output load voltage of the unit is greater than a second preset value, the frequency of the pulse width modulation signal is increased.