TWI459203B - Data storage device and control method for non-volatile memory - Google Patents

Description

Data storage device and non-volatile memory control method

The present invention relates to a data storage device and a non-volatile memory control method, and more particularly to a restart technique for erasing an interrupt on a non-volatile memory.

Non-volatile memory is commonly used to implement a data storage device. Non-volatile memory includes: read-only memory, flash memory, electronic erasable rewritable read-only memory, embedded flash memory, magnetic memory, phase change memory, resistive memory, and Tantalum nitride memory...etc. Non-volatile memory usually requires the release of space for data storage. However, if an unexpected interruption (for example, a power outage) occurs during the erasing process, the state of the memory cell being erased cannot be grasped, and an error occurs.

The invention discloses a data storage device and a non-volatile memory control method.

A data storage device implemented in accordance with an embodiment of the present invention has a non-volatile memory and a controller. The non-volatile memory provides a plurality of blocks for data storage, and each block is divided into a plurality of segments. The controller sets the erase flag bit in each segment to record the progress of the erase operation performed on the non-volatile memory to restart the erase operation when needed.

Another embodiment discloses a non-volatile memory controller law. A non-volatile memory system provides a plurality of blocks to store data, and each block is divided into a plurality of sectors. The control method includes the steps of: setting an erase mark bit in each segment; and recording, by the erase mark bit, a progress of an erase operation performed on the non-volatile memory, to restart the device when needed Describe the erase operation.

The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

1 is a block diagram illustrating a data storage device 102 implemented in accordance with an embodiment of the present invention. The data storage device 102 can be coupled to a host 104 for backup storage or for long-term persistent data storage. The user can control the data storage device 102 through an interface between the host 104 and the data storage device 102. In other embodiments, the data storage device 102 can be used to implement a portable electronic device, such as an MP3 or a smart phone, etc. At this time, the host 104 can be designed as a microcontroller in the portable electronic device.

The data storage device 102 includes a non-volatile memory 106 and a controller 108. The controller 108 can further include a read-only memory storage firmware code. The controller 108 can execute the firmware code to control the non-volatile memory 106 according to instructions issued by the host 104.

As shown, the non-volatile memory 106 can include a plurality of blocks. BLK1, BLK2, etc., for data storage. Each block is divided into multiple segments (the segment is a spatial unit, ie, sector). For example, block BLK1 includes a plurality of segments SEC1, SEC2 to SECN. Under the control of the controller 108, each segment is configured with erasing marker bits (as shown, the last digit of the segment SEC1 is used as the erasing flag bit of the segment SEC1, labeled as Marker_Bits). Each segment provides itself with a space as an erase mark bit. Note that the erased mark bit disclosed does not limit the last digits of each segment. For example, in other embodiments, an initial digit of a segment can be configured to erase the flag bit. The controller 108 can record an erasing operation (which can be a "segment" erase operation or a "block" erase operation) in the erased segment or the erased mark bit in the erased block. schedule. Based on the erase flag bit, the controller 108 can restart the erase operation from an unexpected break point of the erase operation.

Regarding the non-volatile memory 106, the erase operation performed thereon may be a segment erase operation or a block erase operation. The so-called segment erase operation erases only a single segment of space. The so-called block erase operation is to erase the space of an entire block. In order to distinguish the erased form (for segment erase or block erase), the controller 108 has a corresponding special design. When an erase operation is performed on a space of a segment, the controller 108 changes the erase mark bit of the single segment. When an erase operation is performed on the space of a block, the controller 108 is a erase mark bit that changes the space of at least two of the blocks. For example, if a segment/block erase operation is unexpectedly interrupted (eg, powered down), controller 108 may resume the erase erase operation based on the previously changed erase flag bit. During a erase operation restart process, if more than one segment of the verified block has a changed erase flag bit, the controller 108 may restart a block for the verified block. Erase operation. If the verified block has only a single segment of space with a changed erase flag bit, the controller 108 may restart an erase operation on the single segment of the verified block. During the erase operation restart, the controller 108 verifies the blocks in the non-volatile memory 106 one by one until the changed erase mark bit is detected, or until the non-volatile memory 106 is detected. All blocks have been verified.

2A and 2B are flowcharts illustrating how the controller 108 performs the segment/block erase operation. The segment/block erase operation can be implemented by a pre-program, an erase program, a post-program, and a refresh program. The controller 108 can set the erase flag bits with different values to indicate different programs. In an embodiment, the erasing flag of each segment may have 8 bits and may be set to the following 5 different values: a first value (eg, 8'h00) indicates the pre-stylized state; a second A value (such as 8'hFF) indicates the erased state; a third value (such as 8'hFC) indicates the post-stylized state; a fourth value (such as 8'hF0) indicates the updated state; and, a fifth The value (such as 8'hC0) is used as a default value, indicating a erase completion status.

According to the flowcharts shown in Figs. 2A and 2B, the pattern of the erase operation (segment or block erase) is identified in step S202.

If step S202 recognizes that an erase operation is performed on a particular segment, the disclosed process proceeds to steps S204 through S218. Step S204 sets the erase flag bit of the specific segment to the first value (e.g., 8'h00), and step S206 stylizes the specific segment. Step S208 performs an erase program of the segment erase operation for the specific segment, and sets the erase flag bit of the specific segment to the second value (e.g., 8'hFF). Step S210 wipes the specific segment The flag is set to a third value (e.g., 8'hFC), and step S212 is post-programmed. Step S214 sets the erase flag bit of the specific segment to the fourth value (e.g., 8'hF0), and step S216 updates the specific segment. Step S218 sets the erase flag bit of the specific segment to a fifth value (e.g., 8'hC0), the value being a standing value indicating that the segment erase operation is completed.

If the step S202 recognizes that a block erasing operation is performed on a specific block, the disclosed process proceeds to steps S220 to S234. Step S220 sets the start segment of the specific block and the erase flag of the final segment to the first value (e.g., 8'h00). Step S222 pre-programs the entire block of the specific block. Step S224 performs an erase program of the block erase operation on the specific block, and the erase flag bits of all the segments in the specific block are set to the second value (such as 8'hFF). Step S226 sets the erase flag bit of all segments of the specific block to the third value (e.g., 8'hFC), and step S228 post-programs the specific block. Step S230 sets the erase flag bits of all the segments of the block to the fourth value (e.g., 8'hF0), and step S232 updates the specific block. Step S234 sets the erase flag bits of all the segments of the specific block to the fifth value (such as 8'hC0), which is a permanent value, indicating that the block erasing operation has been completed.

Figure 3 is a flow chart illustrating an erase operation restart procedure performed by the controller 108 during power up. After the fuse read step of step S302, the controller 108 scans a start block (address 0). In step S304, the controller 108 reads out the erase flag bits of the plurality of segments of the start block. If it is determined that more than one segment of the erase flag bit corresponding to the start block has deviated from the standing value (condition S306 is established), the flow advances to step S308. Step S308, restarting a block erasing operation, and the block erasing operation The interrupt program restarted by the erase flag bit whose value has changed. After the block erase operation of the restart is completed, the non-volatile memory 106 can be operated by other control programs.

If it is determined that only one segment of the space in the initial block has an erase flag bit deviating from the standing value (condition S310 is established), the flow advances to step S312. Step S312 restarts an erase program, and the erase program is restarted from the interrupt program indicated by the erase flag bit whose value is changed. The erasing operation to be restarted is completed, and the non-volatile memory 106 can be operated by other control programs.

If it is determined that the erase flag bits of all the segments of the initial block are maintained at the permanent value (condition S314 is established), the flow advances to step S316. Step S316 determines whether all the blocks of the non-volatile memory 106 have been verified. Step S318 is designed to re-instruct the address of the address to direct the controller 108 to read the next block, to perform step S304 again to read the erase flag bit of the plurality of segments in the next block. Similarly, according to the conditions S306, S310, and S314, the steps S308, S312, and S316 are alternatively performed. Once it is determined in step S316 that all of the non-volatile memory 106 has been verified, the controller 108 determines that the non-volatile memory 106 can be operated by other control programs.

Another embodiment discloses a non-volatile memory control method. A non-volatile memory system stores data in a plurality of blocks, and each block is divided into a plurality of blocks. The control method includes the steps of: configuring an erase mark bit in a space of each segment; and using the erase mark bit to record an erase operation on the non-volatile memory, to restart the wipe when needed In addition to the operation.

In some embodiments, the disclosed control method can be erased in one segment An erase mark bit that changes the space of the segment when the operation is performed in a space. Alternatively, the disclosed control method may change the erase flag bits of the space of at least two of the blocks when a block erase operation is performed on a block. During an erase operation restart process, if it is detected that there is more than one erased mark bit in the verified block, the disclosed control method may restart a block erase operation on the verified block. . If it is determined that the erased mark bit of the block in the verification has only one space, the disclosed control method performs a segment erase operation on the space of the segment in the verified block. During the restart of the erase operation, a plurality of blocks in the non-volatile memory may be verified one by one until a changed erase mark bit is detected or until all areas of the non-volatile memory are detected. The blocks are verified. In some embodiments, the erase flag bits are set with a number of values (such as the five values described above) to show the progress of an erase operation (segment or block erase).

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102‧‧‧ data storage device

104‧‧‧Host

106‧‧‧Non-volatile memory

108‧‧‧ Controller

BLK1, BLK2‧‧‧ blocks

Marker_Bits‧‧‧Erase Marker Bits

S202...S234‧‧‧Steps

S302...S318‧‧‧Steps

SEC1, SEC2...SECN‧‧‧

1 is a block diagram illustrating a data storage device implemented in accordance with an embodiment of the present invention; FIGS. 2A and 2B are a flow chart illustrating how the controller 108 performs a segment/block erase operation; FIG. 3 is a flowchart The erase controller restarts the program as illustrated by the controller 108 during power-up.

102‧‧‧ data storage device

104‧‧‧Host

106‧‧‧Non-volatile memory

108‧‧‧ Controller

BLK1, BLK2‧‧‧ blocks

Marker_Bits‧‧‧Erase Marker Bits

SEC1, SEC2...SECN‧‧‧

Claims (14)

A data storage device comprising: a non-volatile memory having a plurality of blocks for storing data, wherein each of the blocks is further divided into a plurality of segments; and a controller configured to respectively erase the flag bits in the segments And recording the progress of an erasing operation performed on the non-volatile memory for restarting the erasing operation; wherein the erasing operation comprises pre-programming the erasing flag bit with different numerical values Program, a wiper program, a post-programming program, and an update program. The data storage device of claim 1, wherein the controller changes the erasing operation when performing the erasing operation on a target erasing segment. The target erases the above erased flag bit of the segment. The data storage device of claim 1, wherein the controller performs the erasing operation on a target erasing block in a state in which the erasing operation is a block erasing operation. And changing the above-mentioned erasing flag bit corresponding to at least two segments in the target erasing block. The data storage device of claim 3, wherein: the controller verifies the blocks during an erase operation restart process, and detects the number of blocks in the blocks. When more than one segment of the corresponding erase flag bit is changed, the block erase operation is restarted for the one of the blocks. The data storage device of claim 2, wherein the controller performs the inspection of the blocks during an erase operation restart process. And verifying that the segment erase operation is restarted for the single segment when it is detected that only one of the erase flag bits corresponding to a single segment in one of the blocks is changed. The data storage device of claim 4, wherein the controller verifies the blocks of the non-volatile memory one by one during the restarting of the erasing operation until a change is detected. The erased mark bit is pasted, or until all blocks of the non-volatile memory have been verified. The data storage device of claim 1, wherein the controller sets the erasing marker bit by a plurality of values, wherein the plurality of values are: a first value indicating a pre-stylized state; and a second value Marking a erased state; a third value indicating a post-stylized state; a fourth value indicating an updated state; and a fifth value indicating a standing value of the erased mark bit, indicating a erase completion state . A non-volatile memory control method, wherein the controlled non-volatile memory has a plurality of blocks for data storage, and each of the blocks is further divided into a plurality of segments, and the non-volatile memory control method includes: Segments are respectively configured to erase the mark bit; and the erase mark bit records the progress of an erase operation performed on the non-volatile memory for restarting the erase operation, wherein the erase operation includes The above-mentioned erased mark bit is a pre-programming program, a eraser program, and a post-programming program indicated by different numerical values. And an update program. The non-volatile memory control method of claim 8, further comprising: when the erasing operation is a segment erasing operation, when the erasing operation is performed on a target erasing segment The above erase flag bit of the target erase segment is changed. The non-volatile memory control method of claim 8, further comprising: performing the erasing operation on a target erasing block in the case that the erasing operation is a block erasing operation; The above erased flag bit of at least two segments in the target erase block is changed. The non-volatile memory control method according to claim 10, further comprising: in the process of restarting the erasing operation, if it is perceived that one of the blocks in the verified block has more than one segment If the above erased flag bit changes, the block erase operation is restarted for the one of the blocks. The non-volatile memory control method according to claim 9, wherein: during the erasing operation restarting, verifying the blocks, if it is perceived that there is a block in the blocks verified When there is only a single segment of the above erased flag bit, the segment erase operation is restarted for the single segment. The non-volatile memory control method according to claim 11 or 12, wherein the blocks of the non-volatile memory are verified one by one during the restarting of the erasing operation until the detection Varying the above erased mark bit, or up to the area of the non-volatile memory The blocks have been verified. The non-volatile memory control method of claim 8, further comprising: providing a plurality of values for setting the erasing marker bit, wherein the plurality of values includes: a first value indicating a pre-stylization State; a second value indicating an erase state; a third value indicating a post-stylization state; a fourth value indicating an update state; and a fifth value being a standing value indicating a wipe completion state.