TWI458261B - Digital controller with level conversion function and its level conversion circuit - Google Patents

Description

Digital controller with level conversion function and its level conversion circuit

The present invention is a digital controller, and more particularly a digital controller having a level conversion function and a level conversion circuit that can be integrated into the digital controller in a semiconductor process.

An existing power supply system is shown in FIG. 5, which includes a DC-to-DC conversion unit 21 and a digital controller 22; wherein the DC-to-DC conversion unit 21 has a power input terminal and a power output terminal. The power output terminal is connected to the input end of the digital controller 22 through a quasi-conversion circuit 23; the digital controller 22 includes an analog-to-digital converter 221, a digital compensator 222 and a digital pulse width modulator 223; The input end of the analog-to-digital converter 221 is connected to the output end of the level conversion circuit 23, and the output end of the digital pulse width modulator 223 is used to control the on/off of each power transistor in the DC-to-DC conversion unit 21. On cycle.

The above-mentioned power supply has a relatively common output voltage of 12V or 5V, and the digital controller 22 that controls the output voltage adopts digital control. After sensing the output voltage (V _out ) of the DC-to-DC conversion unit 21, it must pass analogical digits. The converter 221 is converted to a digital form and then subjected to compensation control, and the highest voltage allowed by the analog-to-digital converter 221 is 3.3V, so the output voltage of the DC-to-DC conversion unit 21 must be transmitted through the level conversion circuit 23. _The buck can be used to make the analog-to-digital converter 221 operate in the normal range.

The level conversion circuit 23 includes a differential amplifier 231 having a positive phase input terminal, an inverting input terminal, and an output terminal. The positive phase input terminal is connected to the power supply of the DC to DC conversion unit 70. The output terminal 232 is mainly composed of a voltage dividing resistor and a quenching diode to provide a reference voltage to the inverting input terminal of the differential amplifier 231; a protection circuit 233 is provided The output of the differential amplifier 231 is mainly composed of a diode 234 and a capacitor 235. The node of the diode 234 and the capacitor 235 is connected to the output of the differential amplifier 231, and the diode 234 is connected. The other end is connected to the DC power supply (3.3 V), and the other end of the capacitor 235 is connected to the ground; the diode 234 and the capacitor 235 prevent the output voltage of the differential amplifier 231 from being overloaded and distorted.

It can be seen from the above structure that the existing level conversion circuit 23 generates a level voltage by the reference voltage generating unit 232 as the differential amplifier 231 reduces the signal level of the power supply output voltage; wherein the digital controller is not allowed to be used. 22, because the input signal is too large, resulting in overload damage, so the output of the differential amplifier 231 is connected to a protection circuit 233, which provides overload protection by the diode 234; in addition, in order to enable the input signal of the digital controller 22 More complete, the capacitor 235 is utilized to prevent the output signal of the differential amplifier 231 from being distorted.

It can be seen from the above description that although the level conversion circuit can supply the output voltage of the power supply to a digital controller to perform voltage regulation, the level conversion circuit is installed on the circuit board by a plurality of components. The circuit is composed of a large volume, which causes the power density of the power supply to be further improved. Moreover, each component constituting the level conversion circuit has a certain tolerance range, so it is necessary to frequently fine-tune after the composition, so that the existing The level shifting circuit works normally, which is another significant inconvenience.

In view of the above-mentioned existing level conversion circuit, since most components are mounted on a predetermined line on the circuit board and occupy a large volume, the power density cannot be improved and each component has a certain tolerance range, so it is necessary to frequently fine-tune after the composition. The main object of the present invention is to provide a level conversion circuit of a digital controller for reducing the area of the level conversion circuit itself.

The main technical means used to achieve the above purpose is that the level conversion circuit includes: a constant current level loop, which is mainly composed of a level resistor connected in series with a first transistor, the first transistor having a a control terminal for controlling the magnitude of the loop current; the DC loop controller has an input end and an output end, the output end of which is connected to the control end of the first transistor, and the input end is coupled to the first transistor and a series connection between the level resistors, thereby forming a feedback to cause the DC loop controller to generate a voltage corresponding to a current flowing through the first transistor; an AC/DC separation loop, mainly by a cross The DC input resistor is connected in series with a third transistor, the third transistor has a control end for controlling the magnitude of the current flowing through the loop; an AC loop controller has an input end and an output end, and the output end is connected At the control end of the third transistor, the input terminal is connected to the serial connection node between the third transistor and the AC/DC input resistor; and the circuit is fed back by the circuit to make the AC circuit The device generates a voltage corresponding to a current flowing through the third transistor; the DC-current shunt circuit includes a second transistor, and the second transistor is connected in parallel with the third transistor of the AC-DC separation circuit. And the control end of the second transistor is also connected to the output end of the DC link controller, and is simultaneously connected to the control end of the first transistor; wherein the first and second transistors have the same specification characteristics; and an AC check The circuit is mainly composed of a fourth transistor, a current mirror circuit and an AC output resistor. The current mirror circuit has an input end and an output end, and the input end is connected in series with the fourth transistor, and the output thereof is The terminal is connected in series with the AC output resistor; wherein the fourth transistor and the control terminal of the third transistor are simultaneously connected to the output end of the AC circuit controller, and the fourth transistor has the same specification characteristics as the third transistor .

It can be seen from the above structure that the level conversion circuit of the present invention generates a fixed direct current by using the direct current level loop, and generates a direct current bias corresponding to the direct current by the feedback structure of the direct current loop controller, so that the The DC shunt circuit generates a DC shunt current with a DC current; and the DC shunt circuit is connected in parallel with the AC/DC separation circuit; and further, the DC component of the AC/DC current signal input to the AC/DC separation circuit flows into the DC shunt In the loop; further, since the feedback structure of the AC loop controller generates an AC bias corresponding to the AC current and is connected to the AC detection circuit, the AC detection circuit can obtain the AC/DC current signal Its communication component.

Furthermore, as can be seen from the above description, the level conversion circuit of the present invention is mainly composed of a transistor or a loop controller composed of a transistor, and thus is relatively easy to be completed in a semiconductor process, and can be further integrated into a digital controller. in.

In addition, another object of the present invention is to provide a digital controller having a level conversion function, and the main technical means used for the above purpose is to enable the digital controller to include: a predetermined level conversion circuit; The digital converter includes an input end and an output end; the input end is connected to the output end of the level conversion circuit; the digital pulse width modulator comprises an input end and an output end; A digital compensator is coupled to the output of the analog to digital converter.

As can be seen from the structure, and since the digital controller of the present invention integrates the level conversion circuit, most components are not required to be mounted on the circuit board, and the occupied volume can be greatly reduced, thereby improving the power density of the power supply. .

According to the above description, since the digital controller with the level conversion function and the level conversion circuit thereof are all completed in the semiconductor process, all the materials and specifications can be uniformly designed, thereby avoiding the generation of the tolerance range. There is no need to fine tune frequently.

The present invention provides a digital controller, and more particularly to a digital controller having a level conversion function and a level conversion circuit that can be integrated into the digital controller in a semiconductor process. Referring to FIG. 1 , the level conversion circuit of the present invention comprises a DC level circuit 11 , a DC circuit controller 12 , an AC/DC separation circuit 13 , an AC circuit controller 14 , and a DC current circuit 15 . An AC detection circuit 16; wherein: the DC level circuit 11 includes: a level resistor (R_DC), one end of which is connected to a fixed voltage source terminal (V _DD ); and a first transistor (M1) ) is connected in series to the other end of the level resistor (R_DC) and the common ground (GND), and includes a control terminal (gate) for controlling the direct current flowing between the two ends (I _DC ).

In the present embodiment, the DC link controller 12 is formed by a first operational amplifier (OPA1), and its non-inverting input terminal is connected to one end of the level resistor (R_DC) in series with the first transistor (M1). Forming a negative feedback, the inverting input is connected to a fixed voltage source (BVR), and the output is connected to the control end of the first transistor (M1); the first operational amplifier (OPA1) is By forming a negative feedback with the above components, a DC bias corresponding to a direct current (I _DC ) flowing across the first transistor (M1) is generated at the output terminal.

The AC/DC separation circuit 13 includes an AC/DC input resistor (R_ACDC), one end of which is connected to the output end of the power supply to receive the output voltage (V _out ) of the power supply; and a third transistor (M3) ) is connected in series to the other end of the AC/DC input resistor (R_ACDC) and the common ground (GND), and includes a control terminal (gate) for controlling the alternating current (i _ac ) flowing through the two ends.

In the embodiment, the AC circuit controller 14 is composed of a second operational amplifier (OPA2), and its non-inverting input terminal is connected to one end of the AC/DC input resistor (R_ACDC) and the third transistor (M3). To form a negative feedback, and the inverting input is connected to a fixed voltage source (BVR), and the output is connected to the control end of the third transistor (M3); the second operational amplifier (OPA2) borrows A negative feedback is formed by the above-mentioned components, and an AC bias corresponding to the alternating current (i _ac ) flowing through the third transistor (M3) is generated at the output end.

The DC shunt circuit 15 includes a second transistor (M2) connected in parallel with a third transistor (M3) of the AC/DC separation circuit 13, and the second transistor (M2) has a control terminal (gate). The control terminal is connected to the output end of the first operational amplifier (OPA1) with the control terminal of the first transistor (M1), and the first transistor (M1) due to the manufacturing parameters of the second transistor (M2) The same, so when the DC bias on the output of the first operational amplifier (OPA1) is simultaneously input to the control terminal between the two, the DC image current flowing through the second transistor (M2) (I _DC ' And the direct current (I _DC ) flowing between the two ends of the first transistor (M1) must be the same; in addition, since the second transistor (M2) is connected in parallel with the third transistor (M3), The AC and DC current (i _AC+DC ) originally flowing through the third transistor (M3) is divided into a part of current to the second transistor (M2), and the current is the DC image current (I _DC) '), then flows through the third transistor (M3) then the current leaving only the alternating current (I _AC); the AC line detection circuit 16 includes a fourth transistor (M4), an electrical A mirror circuit 160 and the AC output resistor (R_AC).

The fourth transistor (M4) has a control terminal (gate), and its control terminal is connected to the output end of the third transistor (M3) connected to the output terminal of the second operational amplifier (OPA2). And because the manufacturing parameters between the two are the same, when the AC bias at the output of the second operational amplifier (OPA2) is simultaneously sent to the control terminals of the third and fourth transistors (M3, M4), a fourth transistor (M4) of the alternating current image (i _ac ') flowing through the third transistor (M3) of the alternating current (i _ac) certainly be the same; the current mirror circuit having an input line 160 and An output terminal is connected to the fourth transistor (M4); in the embodiment, the current mirror circuit 160 is a stacked configuration; wherein the stacked configuration current mirror circuit 160 includes There is: a fifth transistor (M5) whose source is connected to a fixed voltage source terminal (V _DD ), the gate thereof serves as a control terminal, and a sixth transistor (M6) whose source string is Connected to the drain of the fifth transistor (M5), and the drain of the fifth transistor (M4) is connected in series with the drain of the fourth transistor (M4), and the gate is connected as a modified control terminal. a positive voltage (V _b ); a seventh transistor (M7) whose source is connected to a fixed voltage source terminal (V _DD ), the gate of which is a control terminal, and the control terminal is connected to the sixth The drain of the fourth transistor (M6, M4) is connected to the gate of the fifth transistor (M5) to form a substantially stacked current mirror structure; and an eighth transistor (M8) whose source string is Connected to the drain of the seventh transistor (M7); the gate is used as a control terminal, and the control terminal is coupled with a correction voltage (V _b ) of the correction control terminal of the sixth transistor (M6); The output resistance (R_AC) is serially connected to the output end of the current mirror circuit 160 and the common ground (GND); for converting the AC image current (i _AC ') into an AC voltage signal (v _lc ) for the power supply The digital controller of the supplier is used.

It can be seen from the above structure that the present invention utilizes the DC level loop 11 to generate a fixed DC current (I _DC ), wherein the DC current (I _DC ) can be adjusted by a level resistance (R_DC); and because of the DC level The first transistor (M1) in the loop and the first operational amplifier (OPA1) of the DC link controller 12 form a negative feedback structure, so the first operational amplifier (OPA1) generates a DC The current (I _DC ) corresponds to a DC bias that causes the DC shunt circuit 15 to generate a DC shunt current that is the same as the DC current.

Moreover, the input end of the AC/DC separation circuit 13 of the present invention receives the output voltage (V _out ) of the power supply, and thereby generates an AC and DC current (i _AC+DC ) corresponding thereto, wherein the AC and DC current The size of (i _AC+DC ) can be adjusted by the AC/DC input resistance (R_ACDC); and the DC shunt circuit system 15 is connected in parallel with the AC/DC separation circuit 13, so that the DC current of the AC/DC current (i _AC+DC ) signal is further The component (I _DC ') flows into the DC shunt circuit 15 such that the AC/DC separation circuit 13 obtains a pulsating AC portion (i _ac ) in the _AC -DC current (i _AC+DC ).

Furthermore, the AC/DC separation circuit 13 uses a structure in which the third transistor (M3) and the AC circuit controller 14 form a negative feedback, so that the AC circuit controller 14 thus generates an AC current (i _ac ). Corresponding AC bias voltage is sent to the AC detection circuit 16 and converted by the AC detection circuit 16 into an AC voltage (v _lc ) for use by the digital controller.

In addition, the above-mentioned level resistance (R_DC), AC/DC input resistance (R_ACDC), and AC output output resistance (R_AC) can be utilized in the semiconductor process in addition to the independent components. The structure of the transistor is realized, and the above-mentioned resistors can be integrated into one wafer.

Please refer to FIG. 2 and FIG. 3 together for the output voltage signal (V _out ) of the power supply and the AC voltage (V _lc ) detected by the AC output resistance (R_AC) on the level conversion circuit of the present invention. ) is a graph of the waveform of FIG.; in the present embodiment, the output voltage signal (V _out) of the DC component is 12.2 volts and an AC component system is maintained between 10.7 - 13.7 volts, so that this embodiment of the present invention will The original power supply output voltage signal (V _out ) with a DC level of 12.2 volts is reduced to 1.5 volts, and output to the AC detection resistor (R_AC) to maintain the AC voltage between 0.75 and 2.25 volts. Avoid exceeding the rated 3.3 volts.

Please refer to FIG. 4 , which is another preferred embodiment of the present invention. The basic architecture is substantially the same as that of the previous embodiment, and the present invention further includes a first switch circuit 17 and a second switch circuit 18. The first switch circuit 17 is respectively connected to the AC/DC separation circuit 13, the DC level circuit 11, the DC shunt circuit 15 and the AC detection circuit 16, and controls the circuit to be turned on and off; the first switch circuit 17 includes There are four transistor switches (M11, M12, M13, M14), wherein three transistor switches (M11, M12, M13) are respectively connected in series to the DC level loop 11, the DC shunt circuit 15 and the AC/DC separation circuit. 13, another transistor switch (M14) is connected in series to the input end of the AC detection circuit 16, in this embodiment, each transistor switch (M11, M12, M13, M14) is a half-effect of the gold oxide a transistor, each having a control terminal (gate) for controlling conduction; a first switching transistor (M9) consisting of a gold oxide half field effect transistor having a drain and a source a gate whose source is connected to a DC power supply (V _DD ) The poles are respectively connected to the control ends of the respective transistor switches (M11, M12, M13, M14), and a resistor is connected in series between the drain and the ground. In this embodiment, the resistor is composed of a gate and a drain. The gate electrode of the first switching transistor (M9) constitutes a control terminal and is controlled by a first external control voltage (V _bias 1).

With the aforementioned first switching circuit 17, it is possible to control its operation by the outside of the level conversion circuit.

The second switch circuit 18 is connected to the sixth transistor (M6) and the modified control terminal (gate) of the eighth transistor (M8); and includes: a second switch transistor (M15), The utility model is composed of a gold-oxygen half-field effect transistor, having a drain, a source and a gate, the source of which is connected to a ground, and the drain is respectively connected to the sixth transistor (M6) and the eighth The modified control terminal of the crystal (M8) is connected, and a resistor is connected in series between the drain and the DC power supply (V _DD ). In this embodiment, the resistor is a gold-oxygen half-field effect transistor which is connected by the gate and the drain. (M16); the gate of the second switching transistor (M15) constitutes a control terminal and is controlled by a second external control voltage ( _Vbias 2); wherein the second switching transistor (M15) 汲The voltage at the pole is the correction voltage (V _b ) of the current mirror circuit described above.

As can be seen from the above configuration, the first switch circuit 17 serves as a control circuit for the DC component elimination function of the present invention. If the first switch transistor (M9) is not turned on, each transistor switch (M11, M12, M13) M14) will also be closed, so that the DC component elimination function of the present invention can be further controlled. In addition, the second switch circuit 18 serves as a control circuit for the AC component mapping function of the present invention. The switching transistor (M15) is not turned on, and the sixth transistor (M6) and the eighth transistor (M8) on the current mirror circuit 160 of the stacked configuration are also turned off, so that the AC component of the present invention can be further controlled. Whether the mapping function is activated or not.

In addition, in the embodiment, all of the above electro-crystalline systems are field effect transistors.

In addition, the present invention can integrate the above-mentioned level conversion circuit into a digital controller, and thus the digital controller will include: a predetermined level conversion circuit; an analog-to-digital converter including an input terminal and an output terminal The input end is connected to the output end of the level conversion circuit; the digital pulse width modulator comprises an input end and an output end; and the input end thereof is connected to the analog digital converter through a digital compensator The output end of the foregoing digital pulse width modulator will connect and control the on and off periods of the power transistors in the DC-to-DC converter unit.

In summary, since the level conversion circuit of the present invention mostly uses a transistor or a loop controller composed of a transistor, it is quite easy to be completed in a semiconductor process, and can be further integrated into a digital controller, thereby constituting The invention has a digital controller with a level conversion function; furthermore, since the invention is integrated into a wafer, most components are not required to be mounted on the circuit board, and the occupied volume can be reduced, thereby improving the power of the power supply. Density; Moreover, since the present invention can be designed in a semiconductor process, all materials and specifications can be uniformly designed, so that the tolerance range can be avoided without frequent fine adjustment.

11. . . DC level loop

12. . . DC loop controller

13. . . AC/DC separation circuit

14. . . AC loop controller

15. . . DC shunt circuit

16. . . AC detection circuit

160. . . Current mirror circuit

17. . . First switching circuit

18. . . Second switching circuit

twenty one. . . DC to DC conversion unit

twenty two. . . Digital controller

221. . . Analog digital converter

222. . . Digital compensator

223. . . Digital pulse width modulator

twenty three. . . Quasi-conversion circuit

231. . . Differential amplifier

232. . . Reference voltage generating unit

233. . . protect the circuit

234. . . Dipole

235. . . capacitance

Figure 1: Circuit diagram of a level conversion circuit of the present invention.

Fig. 2 is a graph showing the relationship between the output voltage signal of the power supply and the AC voltage signal detected by the level conversion circuit of the present invention.

Fig. 3 is a waveform diagram of the output voltage of the power supply and the voltage detected by the level conversion circuit of the present invention.

Figure 4 is a circuit diagram of another preferred embodiment of the present invention.

Figure 5: Circuit diagram of an existing power supply.

11‧‧‧DC level loop

12‧‧‧DC loop controller

13‧‧‧ AC and DC separation circuit

14‧‧‧AC loop controller

15‧‧‧DC shunt circuit

16‧‧‧AC detection circuit

160‧‧‧current mirror circuit

Claims (9)

A level conversion circuit comprises: a constant current level loop, which is mainly composed of a level resistor connected in series with a first transistor, the first transistor having a control end for controlling the magnitude of the current flowing through the loop; a DC link controller has an input end and an output end, the output end of which is connected to the control end of the first transistor, and the input end is connected to the serial connection between the first transistor and the level resistor Connecting, thereby forming a feedback to cause the DC link controller to generate a voltage corresponding to a current flowing through the first transistor; an AC/DC separation circuit, mainly connected by an AC-DC input resistor to a third transistor The third transistor has a control end for controlling the magnitude of the current flowing through the loop; an AC loop controller having an input end and an output end, the output end of which is connected to the control end of the third transistor; The input terminal is connected to the serial connection node between the third transistor and the AC/DC input resistor; and the structure of the circuit feedback device causes the AC loop controller to generate and flow through the third transistor. The voltage corresponding to the current; the current-splitting shunt circuit includes a second transistor, the second electro-crystal system and the third transistor of the AC-DC separation circuit are connected in parallel, and the control end of the second transistor is also controlled by the DC circuit The output ends of the device are connected to each other and simultaneously connected to the control end of the first transistor; wherein the first and second transistors have the same specification characteristics; and an AC detection circuit is mainly composed of a fourth transistor and a The current mirror circuit and an AC output resistor have an input end and an output end, wherein the input end is connected in series with the fourth transistor, and the output end is connected in series with the AC output output resistor; wherein the fourth The transistor is connected to the output end of the AC circuit controller at the same time as the control terminal of the third transistor, and the fourth transistor has the same specification characteristics as the third transistor. The level conversion circuit of claim 1, further comprising a first switch circuit, wherein the first switch circuit is respectively connected to the AC/DC separation circuit, the DC level circuit, the DC shunt circuit and the AC detection circuit. And controlling the circuit to be turned on and off; and comprising: four transistor switches, wherein three transistor switches are respectively connected in series to the DC level loop, the DC shunt loop and the AC/DC separation loop, and another transistor switch string Connected to the input end of the AC detection circuit, each having a control terminal for controlling conduction; a first switching transistor having a drain, a source and a gate, the source of which is connected to the DC The power supply has a drain connected to the control end of each of the transistor switches, and a resistor connected in series between the drain and the ground; the gate of the first switch transistor constitutes a control end and is provided by a first external Controlled by voltage control. The level conversion circuit of claim 1 or 2, wherein the current mirror circuit is a stacked configuration; wherein the current mirror circuit of the stacked configuration further comprises: a fifth transistor, the source system Connected to a fixed voltage source terminal, the gate thereof serves as a control terminal; a sixth transistor whose source is connected in series to the drain of the fifth transistor, and the drain is connected in series to the fourth The drain of the transistor has a gate as a modified control terminal and is connected to a correction voltage; a seventh transistor has a source connected to a fixed voltage source terminal and a gate as a control terminal. The control end is connected to the gates of the sixth and fourth transistors and the gate of the fifth transistor to form a substantially stacked current mirror structure; and an eighth transistor whose source is connected in series The drain of the seventh transistor; the gate is used as a control terminal, and the control terminal is coupled with a correction voltage of the correction transistor of the sixth transistor. The level conversion circuit of claim 3, further comprising a second switching circuit comprising: a second switching transistor having a drain, a source and a gate, the source of which is connected to a grounding end, wherein the drain is respectively connected to the correction transistor of the sixth transistor and the eighth transistor, and a resistor is connected in series between the drain and the DC power source; and the gate of the second switching transistor is formed a control terminal is controlled by a second external control voltage; wherein the voltage on the drain of the second switching transistor is the correction voltage of the current mirror circuit. According to the level conversion circuit of claim 1, the above-mentioned level resistance, AC/DC input resistance and AC output resistance are realized by a structure of a transistor in a semiconductor process. The level conversion circuit according to claim 1 or 5, wherein the electro-crystal system in the DC level loop, the AC-DC separation loop, the DC shunt loop, and the AC detection circuit is composed of a field effect transistor; and the DC loop control The AC circuit controller and the AC circuit controller are composed of field effect transistors. According to the level conversion circuit of claim 4, the above-mentioned level resistance, AC/DC input resistance and AC output resistance are realized by a structure of a transistor in a semiconductor process. The level conversion circuit according to claim 4, wherein the electro-crystal system in the DC level loop, the AC-DC separation loop, the DC shunt loop, and the AC detection circuit is composed of a field effect transistor; and the DC loop controller and The AC loop controller is composed of a field effect transistor. A digital controller having a level conversion function, comprising: a quasi-conversion circuit, such as the level conversion circuit of any one of claims 1 to 8, and an analog-to-digital converter comprising an input terminal And an output end; the input end is connected to the output end of the level conversion circuit; and a digital pulse width modulator includes an input end and an output end; the input end is connected to the analogy through a digital compensator The output of the digital converter.