TWI457784B - 虛擬機器監視器運行時間完整性觀察器之硬體保護 - Google Patents

虛擬機器監視器運行時間完整性觀察器之硬體保護 Download PDF

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Publication number
TWI457784B
TWI457784B TW101148749A TW101148749A TWI457784B TW I457784 B TWI457784 B TW I457784B TW 101148749 A TW101148749 A TW 101148749A TW 101148749 A TW101148749 A TW 101148749A TW I457784 B TWI457784 B TW I457784B
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Taiwan
Prior art keywords
vmm
integrity
unit
viewer
hardware
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TW101148749A
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English (en)
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TW201342108A (zh
Inventor
Shamanna Datta
Albert J Munoz
Mahesh S Natu
Scott T Durrant
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Intel Corp
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    • A61B17/8066—Cortical plates, i.e. bone plates; Instruments for holding or positioning cortical plates, or for compressing bones attached to cortical plates specially adapted for particular bones for pelvic reconstruction
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Landscapes

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Description

虛擬機器監視器運行時間完整性觀察器之硬體保護
本發明之領域一般係關於電腦處理器架構，且更具體來說是關於虛擬機器監視器運行時間完整性觀察器之硬體保護。
雲端計算服務的消費者(和潛在消費者)已表達出由於關心基礎架構之保護其機密資訊的能力，而不願將機密資資料和工作量部署至雲端基礎架構中。在雲端環境中，這意味著為虛擬化環境提供足夠的安全性。
例如，在虛擬環境中(如大多數的基礎架構即服務(IaaS)部署)，虛擬機器監視器(VMM)的工作是提供安全服務給正在管理之虛擬機器(VM)。因此，VMM具有極高的資產價值，因為若其受到損害，則所有正在監視之VM(工作負載)的安全性也會受到損害。
存在如英特爾的可信賴執行技術(TXT)之技術確保VMM的啟動時間完整性。然而，目前還沒有任何技術確保VMM在運行時間的完整性。在典型的虛擬IaaS環境中，啟動的VMM可能一次持續運行超過一個月的時間，因此增加此關鍵資產(VMM)的易損性。
在下列說明中，提出了許多具體的細節。然而，了解 沒有這些具體的細節仍可實施本發明之實施例。在其他例子中，並未詳細顯示熟知的電路、結構及技術，以免混淆對本說明書的理解。
在本說明書中提到的「一個實施例」、「一實施例」、「一示範實施例」、等等，係表示所述之實施例可能包括一特定特徵、結構、或特性，但每個實施例可能不必包括此特定特徵、結構、或特性。此外，這樣的說法不一定係指相同的實施例。又，當說明與實施例關聯之特定特徵、結構、或特性時，應認為無論是否明確地說明，其在本領域之熟知技藝者的理解內能影響這類與其他實施例關聯之特徵、結構、或特性。
如之前詳細所述，若虛擬機器監視器(VMM)受到損害，則VMM正在管理之所有VM(工作負載)的安全性也會受到損害。本文所述之實施例為根VMM提供運行時間完整性保護。
第1圖繪示根據一實施例之用於虛擬機器監視器運行時間完整性觀察器的硬體保護之示範系統。CPU硬體120包括為執行虛擬機器(VM)110-114、主VMM 118和主VMM運行時間完整性觀察器程式116(「觀察器」)所必需的硬體。VMM 118係為獨立根VMM，其運行在裸金屬上並提供安全服務給VM 110-114且能夠保留選擇性控制處理器資源、實體記憶體、中斷管理、及透過CPU硬體120為VM 110-114所提供的資料I/O。
觀察器116係為監視主VMM 118之內容和行為的程 式(例如，用以偵測VMM 118中的有毒軟體或其他軟體或上述有毒軟體所導致的行為)。在一實施例中，觀察器116被載入從其中可見整個VMM的記憶體和資源之硬體範圍暫存器保護的連續記憶體空間中。因此，觀察器116可監視VMM的記憶體和資源。在一實施例中，定義硬體範圍暫存器135界定用於觀察器116的代碼所在之記憶體位址空間的界限。
硬體範圍暫存器135可以是部分的處理器核心分頁管理單元並協同處理器之記憶體管理架構來工作。在一實施例中，當VMM 118啟動並設定一鎖定位元時，VMM 118便設定硬體範圍暫存器135之值，其防止值後續被改變(除非發生再啟動)。
硬體範圍暫存器保護的連續記憶體空間防止平台上的其他實體(包括VMM 118)修改觀察器116或影響其行為。例如，一旦代碼轉換成範圍暫存器所定義之硬體範圍暫存器保護的連續記憶體空間，CPU硬體120就設定分頁管理硬體之內的內部識別符(例如，執行觀察器116)。此識別符指示處於觀察器模式。如之後將於本文更加詳細所述，執行觀察器116將被觸發作為某些事件發生的結果。由此，只有當處理器執行將控制轉移至觀察器116時才設定識別符。當處理器執行將控制轉移回VMM 118時便重設識別符。
例如，分頁管理硬體允許從觀察器116至任何其他記憶體空間(不包括系統管理碼空間)所進行的記憶體存 取。例如，分頁管理單元諮詢內部識別符以判斷是否允許記憶體存取。從不執行在硬體範圍暫存器135所定義之空間中的代碼至範圍暫存器135所定義之空間的存取被分頁管理硬體單元導向至異常終止分頁。在這種情況下，例如，在硬體範圍暫存器135所定義的空間之外執行的代碼將讀取所有1(0xff)。透過舉例，如由方塊箭頭160所指示，防止VMM 118存取VMM完整性觀察器116(例如，藉由分頁管理硬體單元來防止)。例如，若未設定識別符，則分頁管理單元引導請求至異常終止分頁。當設定識別符時，VMM 118不應該能夠進行記憶體存取，因為當偵測到事件且控制移至觀察器116時會先執行VMM 118。
在一實施例中，允許從執行在系統管理模式135中的代碼存取範圍暫存器135所定義的記憶體空間。因此，系統管理模式被視為是一種監管模式且允許能存取觀察器116。執行在系統管理模式中的代碼可在可信賴的計算庫之內。系統管理模式可允許進行如可靠度、可用性、和可服務性(RAS)的監管功能。例如，第2圖繪示能夠存取220觀察器116的代碼空間(例如，為了進行RAS功能)，且防止從觀察器116存取215 SMI處理器210的代碼空間的示範SMI處理器210(其可在可信賴的計算庫之內)。
在一實施例中，由於硬體保證不可改變的觸發機制呼叫執行觀察器116而執行觀察器116。例如，在一實施例中，使用硬體計時器130(其可以是隨機的)來產生使 VMM 118先被執行且控制被帶入觀察器116(其被載入受保護之記憶體空間中)的事件132。例如，硬體計時器130最初可以上界值和下界值來編程以用隨機在這兩個值之間的值產生計時器事件132。使用計時器130中之上和下界值並使計時器130用硬體隨機在這兩個界線之間的值產生計時器事件132的優點在於可能進入的有毒軟體不能輕易猜測何時將呼叫觀察器。這使得有毒軟體更難隱藏避開觀察器116。這增加了抗有毒軟體的限制，其會估計何時觀察器116變成啟動且試圖在那段時間期間隱藏。在其他實施例中，由於如由自發事件142所指之壞的I/O埠口和控制暫存器或機器特定暫存器(MSR)執行之某些事件(本文稱為「自發事件」)而呼叫觀察器116，且控制被帶至觀察器116。
在呼叫執行觀察器116之後，其操作在不受有毒軟體影響的硬體受保護之區域中並密碼地驗證VMM的完整性165。在一實施例中，觀察器116使用熟知的密碼演算法(例如，SHA-2)以計算第一次呼叫期間的代碼及/或資料之部分的雜湊(例如，當機器最初啟動並進行第一次呼叫時)並將其儲存在硬體範圍暫存器保護的記憶體空間中。接著，當在VMM 118之運行時間期間後續呼叫觀察器116時，觀察器116對代碼及/或資料之那些部分重覆雜湊操作以判斷雜湊值是否相同。若它們相同，則VMM 118的完整性不會受到損害。若它們不同，則VMM 118的完整性會受到損害。在另一實施例中，VMM 118的雜湊值係以 不同方式來產生，例如，在編譯期間(在這種情況下它可被發出)。
在一實施例中，次級觀察器程式140被包括在VMM118內。次級觀察器程式140可散佈在整個記憶體。次級觀察器程式140能運行在VMM情境中。此外，次級觀察器程式140能隨著中斷啟動而運行。在次級觀察器程式140被包括在VMM 118內的實施例中，觀察器程式116驗證次級觀察器程式140的完整性並接著將驗證VMM 118的完整性之責任部分或全部地轉移至次級觀察器。
在一實施例中，CPU硬體120的一組硬體暫存器130係用於安全報告機制以報告觀察器116的發現。在一實施例中，這組硬體暫存器130能只被觀察器116寫入，但能被任何其他軟體實體讀取。例如，一組一或更多非核心處理器可用於報告。這組非核心暫存器可只被觀察器116寫入，但能夠被任何其他軟體實體讀取。例如，這組非核心暫存器只有當處於觀察器模式時才可被寫入，如由前面描述的識別符所識別。因此，若不是處於觀察器模式，則將不允許寫入。當處於觀察器模式，只有觀察器應執行(因為先執行VMM)且被允許寫至這組非核心暫存器。
在另一實施例中，CPU硬體120可提供通過內嵌於處理器及/或晶片組內的其他微控制器之安全路徑以輸出報告給管理實體(除了或代替使用這組用於報告的硬體暫存器130)。上述管理實體可包括例如系統管理應用程式或雲端管理應用程式。
在報告完整性檢查的結果之後，執行觀察器116離開170且控制被轉移回VMM 118以回復其執行。透過舉例，觀察器116發出使VMM 118回復其執行的指令架構觸發(例如，VMRESUME)指令。
第3圖係繪示根據一實施例之提供VMM運行時間完整性檢查應用程式之硬體保護的系統所進行之示範操作的流程圖。將關於第1圖之示範實施例來說明第3圖。然而，應了解關於第3圖所述之操作能由不同於關於第1圖所述之實施例進行，而關於第1圖所述之實施例能進行不同於關於第3圖所述之操作。
在操作310中，經歷了將觸發執行觀察器116的事件。例如，事件可以是硬體計時器130所產生的計時器事件132。作為另一實例，事件可以是如壞的I/O埠口和控制暫存器或有毒軟體所進行的SMR執行之自發事件142。流程從操作310移至操作315。
在操作315中，事件使得硬體120先執行VM 118並執行觀察器116。例如，一旦事件發生，晶片組就顯示信號以使處理器在下個指令邊界進入觀察器模式。如之前所述，在一實施例中，觀察器116被載入透過硬體範圍暫存器而防止被修改或影響其行為(包括藉由VMM 118)之連續記憶體空間的區域中。
流程接著移至操作320，其中觀察器116驗證VMM的完整性。例如，這可包括觀察器116分析項目之原因(例如，其被執行的原因)且產生VMM 118的代碼及/或 資料之部分的密碼雜湊並將其與先前所儲存之值比較。
在有單一觀察器之實施例中(亦即，在沒有次級觀察器140之實施例中)，觀察器116進行所有分析且自中斷關閉可能耗費不超過200微秒來分析項目的原因。
在除了觀察器116之外還有次級觀察器140之實施例中，觀察器116驗證運行在VMM情境中的次級觀察器140。次級觀察器程式140能隨著中斷啟動而運行。次級觀察器140可完全、或部分地進行VMM有毒軟體檢查的責任。
流程從操作320移至操作325。在操作325中，觀察器116報告其發現。例如，觀察器116寫至暫存器150以指示是否已損害VMM 118的完整性。作為另一實例，除了或代替寫入暫存器150之外，觀察器116還報告發現(例如，VMM 118之完整性的狀態)給如系統管理應用程式或雲端管理應用程式的管理實體。在這種情況下，CPU硬體120可提供安全路徑通過內嵌於處理器及/或晶片組內的微控制器。
在有次級觀察器140之實施例中，次級觀察器140將其驗證結果回傳至主要觀察器116且主要觀察器116在一實施例中報告如上述之結果。在另一實施例中，來自次級觀察器140的結果之發出報告係使用平台基礎的密碼硬體元件(可信賴的平台模組(TPM))來產生。
在一實施例中，外部伺服器(管理控制台)使用完整性檢查的結果。例如，寫至暫存器150的結果可由晶片組 輸出給管理控制台，這樣可管理多個伺服器。作為另一實例，發出報告(使用TPM元件發出)被輸出給管理控制台。一旦判定完整性受到損害，這些管理控制台可採取行動。例如，可能使得機器關機。作為另一實例，可能使得通知(例如，電子郵件、正文信息等)自動產生並發送至管理員及/或電話被自動安置到管理員。管理控制台可產生鑑識文字檔或之後能被執行機構使用和分析的其他記錄檔案。
流程從操作325移至操作330，其中觀察器116離開。例如，觀察器116發出離開觀察器模式的觸發(例如，VMRESUME指令)，其將使得VMM 118回復其執行。流程接著移至操作335，其中VMM 118回復其執行。
在另一實施例中，CPU硬體120可提供安全路徑通過內嵌於處理器及/或晶片組內的其他微控制器以輸出報告給管理實體(除了或代替使用這組用於報告的硬體暫存器130)。上述管理實體可包括例如系統管理應用程式或雲端管理應用程式。
因此，本文所述之實施例描述了在最初VMM已透過處理器硬體驅動的運行時間VMM完整性監視器(觀察器)被載入之後檢查VMM完整性的能力。如之前所述，可週期性地及/或一旦某些事件發生時進行檢查，藉此提供對VMM完整性之持續的保證。此外，實施例為本文所述之運行時間完整性檢驗器提供受保護之執行空間。由此，VMM的運行時間完整性能受到保護，藉此為雲端環 境中的虛擬化伺服器之部署解決現今存在的安全性考量。
示範核心架構、處理器、及電腦架構
基於不同目的，處理器核心可以不同方式，且在不同處理器中實作。例如，上述核心之實作可包括：1)預期用於通用計算的通用有序核心；2)預期用於通用計算的高效能通用亂序核心；3)預期主要用於圖形及/或科學(生產量)計算的專用核心。不同處理器之實作可包括：1)CPU，包括一或更多預期用於通用計算的通用有序核心及/或一或更多預期用於通用計算的通用亂序核心；及2)協處理器，包括一或更多預期主要用於圖形及/或科學(生產量)的專用核心。上述不同的處理器導致不同的電腦系統架構，其可包括：1)在與CPU分開之晶片上的協處理器；2)在與CPU相同封裝中的單獨晶粒上的協處理器；3)在與CPU相同之晶粒上的協處理器(在此情況下，這類協處理器有時是指專用邏輯，例如整合圖形及/或科學(生產量)邏輯、或稱為專用核心；及4)單晶片系統，可在相同晶粒上包括所述之CPU(有時稱為應用核心或應用處理器)、上述協處理器、及額外功能。在說明示範處理器及電腦架構之後接著說明示範核心架構。
示範核心架構 有序和亂序核心方塊圖
第4A圖係繪示根據本發明之實施例之示範有序管線 和示範暫存器更名、亂序發出/執行管線兩者的方塊圖。第4B圖係繪示根據本發明之實施例之包括在處理器中的有序架構核心之示範實施例和示範暫存器更名、亂序發出/執行架構核心兩者的方塊圖。第4A-B圖中的實線框繪示有序管線和有序核心，而非必要附加的虛線框繪示暫存器更名、亂序發出/執行管線和核心。假定有序態樣係亂序態樣的子集，將說明亂序態樣。
在第4A圖中，處理器管線400包括提取級402、長度解碼級404、解碼級406、分配級408、更名級410、排程(亦稱為調度或發出)級412、暫存器讀取/記憶體讀取級414、執行級416、寫回/記憶體寫入級418、例外處理級422、及提交級424。
第4B圖顯示包括耦接執行引擎單元450之前端單元430的處理器核心490，且這兩者都耦接記憶體單元470。核心490可以是精簡指令集計算(RISC)核心、複雜指令集計算(CISC)核心、超長指令集(VLIW)核心、或混合或替代的核心類型。作為另一選擇，核心490可以是專用核心，例如，網路或通訊核心、壓縮引擎、協處理器核心、通用計算圖形處理單元(GPGPU)核心、圖形核心或之類。
前端單元430包括耦接指令快取單元434的分支預測單元432，指令快取單元434耦接指令轉譯後備緩衝器(TLB)436，指令TLB 436耦接指令提取單元438，指令提取單元438耦接解碼單元440。解碼單元440(或解碼 器)可解碼指令，並產生一或更多微操作、微碼進入點、微指令、其他指令、或其他控制信號作為輸出，其根據原始指令來解碼、或以其他方式反射、或得到。解碼單元440可使用各種不同機制來實作。適當的機制之實例包括，但不受限於查找表、硬體實作、可程式邏輯陣列(PLA)、微碼唯讀記憶體(ROM)等。在一實施例中，核心490包括微碼ROM或儲存用於某些微指令(例如，在解碼單元440中或在前端單元430內)之微碼的其他媒體。解碼單元440耦接在執行引擎單元450中的更名/分配單元452。
執行引擎單元450包括耦接引退單元454及一組一或更多排程單元456的更名/分配單元452。排程單元456表示一些不同排程器，包括保留站、中央指令窗等。排程單元456耦接實體暫存器檔案單元458。每個實體暫存器檔案單元458表示一或更多實體暫存器檔案，每個儲存一或更多不同的資料類型，例如純量整數、純量浮點數、填充整數、填充浮點數、向量整數、向量浮點數、狀態(例如，待執行之下個指令之位址的指令指標)等。在一實施例中，實體暫存器檔案單元458包含向量暫存器單元、寫入遮罩暫存器單元、及純量暫存器單元。這些暫存器單元可提供架構向量暫存器、向量遮罩暫存器、及通用暫存器。引退單元454重疊實體暫存器檔案單元458以顯示各種可實作暫存器更名和亂序執行的方式(例如，使用重排序緩衝器和引退暫存器檔案；使用未來檔案、歷史緩衝 器、及引退暫存器檔案；使用暫存器映射及一些暫存器等)。引退單元454和實體暫存器檔案單元458係耦接執行叢集460。執行叢集460包括一組一或更多執行單元462和一組一或更多記憶體存取單元464。執行單元462可執行各種操作(例如，移位、加法、減法、乘法)及對各種類型的資料(例如，純量浮點數、填充整數、填充浮點數、向量整數、向量浮點數)執行。儘管一些實施例可包括一些專用於特定功能或功能組的執行單元，但其他實施例可只包括一個執行單元或全部執行所有功能的多個執行單元。顯示排程單元456、實體暫存器檔案單元458、及執行叢集460可能是複數個，因為某些實施例產生分開的管線用於某些類型的資料/操作(例如，純量整數管線、純量浮點數/填充整數/填充浮點數/向量整數/向量浮點數管線、及/或記憶體存取管線，其各者均具有自己的排程單元、實體暫存器檔案單元、及/或執行叢集，且在分開的記憶體存取管線之例子中，某些實施例實作出只有此管線之執行叢集具有記憶體存取單元464)。亦應了解這裡使用分開的管線，這些管線之一或更多者可以是亂序發出/執行且其餘是有序的。
這組記憶體存取單元464係耦接記憶體單元470，其包括耦接耦接第2級(L2)快取單元476的資料快取單元474之資料TLB單元472。在一示範實施例中，記憶體存取單元464可包括載入單元、儲存位址單元、及儲存資料單元，各耦接記憶體單元470中的資料TLB單元472。指 令快取單元434更耦接在記憶體單元470中的第2級(L2)快取單元476。L2快取單元476耦接一或更多其他級的快取之且最終耦接主記憶體。
透過舉例方式，示範暫存器更名、亂序發送/執行核心架構可如下實作管線400：1)指令提取438進行提取和長度解碼級402和404；2)解碼單元440進行解碼級406；3)更名/分配單元452進行分配級408和更名級410；4)排程單元456進行排程級412；5)實體暫存器檔案單元458和記憶體單元470進行暫存器讀取/記憶體讀取級414；執行叢集460進行執行級416；6)記憶體單元470和實體暫存器檔案單元458進行寫回/記憶體寫入級418；7)各種單元可包括例外處理級422；及8)引退單元454和實體暫存器檔案單元458進行提交級424。
核心490可支援一或更多包括本文所述之指令的指令集(例如，x86指令集(具有已加入較新形式的一些擴充)；加州桑尼維爾之MIPS技術的MIPS指令集；加州桑尼維爾之ARM公司的ARM指令集(具有如NEON之非必要額外的擴充))。在一實施例中，核心490包括支援填充資料指令集擴充(例如，AVX1、AVX2)的邏輯，藉此允許許多多媒體應用所使用之操作能使用填充資料來被進行。
應了解核心可支援多執行緒(執行二或多個平行的操作組或執行緒)，並可以包括時間切割多執行緒、同步多執行緒(其中單一實體核心提供邏輯核心給實體核心係同 步多執行緒的每個執行緒)、或以上之組合(例如，如在Intel®超執行緒技術之後的時間切割提取和解碼和同步多執行緒)的各種方式來實行。
儘管在亂序執行的內容中說明了暫存器更名，但應了解可在有序架構中使用暫存器更名。儘管所述之處理器的實施例亦包括分開的指令和資料快取單元434/474及共享L2快取單元476，但其他實施例可具有用於指令和資料兩者的單一內部快取，例如，第1級(L1)內部快取、或多級之內部快取。在一些實施例中，系統可包括內部快取與位於核心及/或處理器外部的外部快取之組合。替代地，所有的快取可在核心及/或處理器的外部。
具體的示範有序核心架構
第5A-B圖繪示更具體之示範有序核心架構的方塊圖，其核心會是晶片中的多個邏輯方塊之其一者(包括相同類型及/或不同類型的其他核心)。邏輯方塊依據應用程式透過高頻寬互連網路(例如，環形網路)來與一些固定功能邏輯、記憶體I/O介面、及其他必要I/O邏輯通訊。
第5A圖係根據本發明之實施例之單一處理器核心連同其連接單晶片互連網路502的連線與其第2級(L2)快取504的區域子集之方塊圖。在一實施例中，指令解碼器500支援具有填充資料指令集擴充的x86指令集。L1快取506允許將快取記憶體低潛時地存取至純量和向量單元。 儘管在一(為了簡化設計的)實施例中，純量單元508和向量單元510使用單獨暫存器組(分別為純量暫存器512和向量暫存器514)，且傳輸於其間的資料被寫至記憶體而接著從第1級(L1)快取506讀回，但本發明之其他實施例可使用不同的方法(例如，使用單一暫存器組或包括一通訊路徑，其允許資料在沒被寫入和讀回的情況下傳輸於這兩個暫存器檔案之間)。
L2快取504的區域子集係為部分的全域L2快取，其分成單獨的區域子集，每個處理器核心一個。每個處理器核心具有直接存取路徑至自己的L2外取504之區域子集。處理器核心所讀取的資料係儲存在其L2快取子集504中且能與存取其自己區域L2快取子集之其他處理器核心並行地快速存取。處理器核心所寫入的資料係儲存在其自己的L2快取子集504中且若需要的話會從其他子集清除。環形網路確保共享資料的一致性。環形網路係為雙向的以允許如處理器核心、L2快取及其他邏輯方塊的代理器能在晶片內彼此通訊。每個環形資料路徑在每個方向上係為1012位元寬。
第5B圖係根據本發明之實施例之第5A圖中的處理器核心之一部分的展開圖。第5B圖包括L1快取504之L1資料快取506A部分、以及關於向量單元510和向量暫存器514的更多細節。具體來說，向量單元510係16寬的向量處理單元(VPU)(參見16寬的ALU 528)，其執行整數、單精度浮點數、及雙精度浮點數指令之一或更多 者。VPU以攪和單元520來支援攪和暫存器輸入、以數字轉換單元522A-B來支援數字轉換、且以複製單元524來支援複製記憶體輸入。寫入遮罩暫存器526允許斷言所得之向量寫入。
具有整合記憶體控制器和圖形的處理器
第6圖係根據本發明之實施例之可具有一個以上之核心、可具有整合記憶體控制器、及可具有整合圖形的處理器600之方塊圖。第6圖中的實線框繪示具有單核心602A、系統代理器610、一組一或更多匯流排控制器單元616的處理器600，而非必要添加的虛線框繪示具有多個核心602A-N、在系統代理器單元610中的一組一或更多整合記憶體控制器單元614、及專用邏輯608的另一處理器600。
因此，處理器600之不同實作可包括：1)具有為整合圖形及/或科學(生產量)邏輯(其可包括一或更多核心)之專用邏輯608的CPU、及為一或更多通用核心(例如，通用有序核心、通用亂序核心、這兩者之組合)的核心602A-N；2)具有為預期主要用於圖形及/或科學(生產量)的大量專用核心之核心602A-N的協處理器；及3)具有為大量通用有序核心之核心602A-N的協處理器。由此，處理器600可以是通用處理器、協處理器、或專用處理器，例如，網路或通訊處理器、壓縮引擎、圖形處理器、GPGPU(通用圖形處理單元)、高產量多重整合核心 (MIC)協處理器(包括30個以上之核心)、內嵌處理器或之類。處理器可實作在一或更多晶片上。處理器600使用如BiCMOS、CMOS、或NMOS的一些處理技術，可以是一部分的一或更多基板及/或可實作在一或更多基板上。
記憶體階層包括核心內之一或多級的快取、一組或一或更多共享快取單元606、及耦接這組整合記憶體控制器單元614的外部記憶體(未顯示)。這組共享快取單元606可包括如第2級(L2)、第3級(L3)、第4級(L4)、或其他級之快取的一或更多中級快取(LLC)、最後一級快取(LLC)及/或以上之組合。儘管在一實施例中，環形基礎的互連單元612使整合圖形邏輯608，這組共享快取單元606、及系統代理器單元610/整合記憶體控制器單元614互連，但其他實施例可使用一些熟知技術來使上述單元互連。在一實施例中，在一或更多快取單元606與核心602A-N之間維持一致性。
在一些實施例中，一或更多核心602A-N能夠進行多執行緒。系統代理器610包括那些協同和操作核心602A-N的元件。系統代理器單元610可包括例如電源控制單元(PCU)及顯示單元。PCU可以是或包括調節核心602A-N和整合圖形邏輯608之電源狀態所需的邏輯和元件。顯示單元係用來驅動一或更多外部連接的顯示器。
核心602A-N在架構指令集方面可以是同型的或不同型的；意即，二或更多之核心602A-N也許能夠執行相同 指令集，而其他也許能夠僅執行指令集的子集或不同指令集。
示範電腦架構
第7-10圖係示範電腦架構的方塊圖。本技術中所知用於膝上型電腦、桌上型電腦、手持PC、個人數位助理、工程工作站、伺服器、網路裝置、網路集線器、交換器、內嵌處理器、數位信號處理器(DSP)、圖形裝置、視頻遊戲裝置、機上盒、微控制器、手機、可攜式媒體播放器、手持裝置、及各種其他電子裝置的其他系統設計和組態亦為適用的。一般來說，如本文所揭露之能夠結合處理器及/或其他執行邏輯之種類繁多的系統或電子裝置通常係為適用的。
現在參考第7圖，所顯示的係依照本發明之一實施例之系統700的方塊圖。系統700可包括一或更多耦接控制器集線器720的處理器710、715。在一實施例中，控制器集線器720包括一圖形記憶體控制器集線器(GMCH)790及一輸入/輸出集線器(IOH)750(其可在分開的晶片上)；GMCH 790包括耦接記憶體740和協處理器745的記憶體和圖形控制器；IOH 750將輸入/輸出(I/O)裝置760耦接至GMCH 790。替代地，記憶體與圖形控制器之一或兩者係整合在處理器內(如本文所述)，記憶體740和協處理器745直接耦接處理器710、及在具有IOH 750之單晶片中的控制器集線器720。
在第7圖中以虛線來表示額外處理器715的非必要性。每個處理器710、715可包括一或更多本文所述之處理核心且可以是一些形式的處理器600。
記憶體740可以是例如動態隨機存取記憶體(DRAM)、相變記憶體(PCM)、或這兩者之組合。針對至少一實施例，控制器集線器720經由多點下傳匯流排，例如前端匯流排(FSB)、如快速通道互連(QPI)的點對點介面、或類似連線795來與處理器710、715通訊。
在一實施例中，協處理器745係為專用處理器，例如，高產量MIC處理器、網路或通訊處理器、壓縮引擎、圖形處理器、GPGPU、嵌入式處理器或之類。在一實施例中，控制器集線器720可包括整合圖形加速器。
實體資源710、715之間在包括架構、微架構、熱、功率消耗特性等之度量範圍方面會存在各種差異。
在一實施例中，處理器710執行控制一般類型之資料處理操作的指令。內嵌在指令內的可以是協處理器指令。處理器710辨識這些協處理器指令為應由所附接之協處理器745所執行的類型。因此，處理器710在協處理器匯流排或其他互連上發出這些協處理器指令(或代表協處理器指令的控制信號)至協處理器745。協處理器745接受並執行收到的協處理器指令。
現在參考第8圖，所顯示的係依照本發明之實施例之第一更具體示範系統800的方塊圖。如第8圖所示，多處 理器系統800係為點對點互連系統，且包括經由點對點互連850耦接的第一處理器870和第二處理器880。處理器870和880之各者可以是一些形式的處理器600。在本發明之一實施例中，處理器870和880分別係為處理器710和715，而協處理器838係為協處理器745。在另一實施例中，處理器870和880分別係為處理器710和協處理器745。
顯示處理器870和880分別包括整合記憶體控制器(IMC)單元872和882。處理器870亦包括點對點(P-P)介面876和878作為其匯流排控制器單元的一部分；同樣地，第二處理器880包括P-P介面886和888。處理器870、880可使用P-P介面電路878、888經由點對點(P-P)介面850來交換資訊。如第8圖所示，IMC 872和882將處理器耦接至各自的記憶體，即記憶體832和記憶體834，其可以是部分區域地附接於各自處理器的主記憶體。
處理器870、880各可使用點對點介面電路876、894、886、898經由個別的P-P介面852、854來與晶片組890交換資訊。晶片組890可選擇性地經由高效能介面839與協處理器838交換資訊。在一實施例中，協處理器838係為專用處理器，例如，高產量MIC處理器、網路或通訊處理器、壓縮引擎、圖形處理器、GPGPU、嵌入式處理器或之類。
共享快取(未顯示)可包括在任一處理器中或兩處理 器之外，還可經由P-P互連與處理器連接，使得若處理器置於低功率模式中，則任一或兩處理器之區域快取資訊可儲存在共享快取中。
晶片組890可經由介面896來耦接第一匯流排816。在一實施例中，第一匯流排816可以是周邊元件互連(PCI)匯流排、或如PCI快捷匯流排或另一第三代I/O互連匯流排的匯流排，雖然本發明之範圍並不以此為限。
如第8圖所示，各種I/O裝置814可與匯流排橋接器818一起耦接第一匯流排816、其中匯流排橋接器818耦接第一匯流排816和第二匯流排820。在一實施例中，一或更多如協處理器、高產量MIC處理器、GPGPU的、加速器(例如，圖形加速器或數位信號處理(DSP)單元)、現場可程式閘陣列、或任何其他處理器的額外處理器815係耦接第一匯流排816。在一實施例中，第二匯流排820可以是低針腳數(LPC)匯流排。在一實施例中，各種裝置可耦接第二匯流排820，包括例如鍵盤及/或滑鼠822、通訊裝置827及如磁碟機或其他可包括指令/代碼和資料830的大容量儲存裝置之儲存單元828。再者，音頻I/O 824可耦接第二匯流排820。請注意其他架構係可能的。例如，系統可實作多點下傳匯流排或其他上述架構而不是第8圖之點對點架構。
現在參考第9圖，所顯示的係依照本發明之實施例之第二更具體示範系統900的方塊圖。第8和9圖中的相似元件具有相同參考數字，且第8圖之某些態樣已從第9圖 省略以避免模糊第9圖之其他態樣。
第9圖繪示處理器870、880分別可包括整合記憶體和I/O控制邏輯(「CL」)872和882。因此，CL 872、882包括整合記憶體控制器單元且包括I/O控制邏輯。第9圖繪示不只記憶體832、834耦接CL 872、882，而且還繪示I/O裝置914亦耦接控制邏輯872、882。傳統I/O裝置915係耦接晶片組890。
現在參考第10圖，所顯示的係依照本發明之實施例之SoC 1000的方塊圖。第6圖中的相似元件具有相同參考數字。而且，虛線框在更進階的SoC上是非必要的特徵。在第10圖中，互連單元1002係耦接：包括一組一或更多核心202A-N和共享快取單元606的應用處理器1010、系統代理器單元610、匯流排控制器單元616、整合記憶體控制器單元614、可包括整合圖形邏輯、影像處理器、音頻處理器、和視頻處理器的一組一或更多協處理器1020、靜態隨機存取記憶體(SRAM)單元1030、直接記憶體存取(DMA)單元1032、及用於耦接一或更多外部顯示器的顯示單元1040。在一實施例中，協處理器1020包括專用處理器，例如網路或通訊處理器、壓縮引擎、GPGPU、高產量MIC處理器、嵌入式處理器或之類。
本文所述之機制的實施例可以硬體、軟體、韌體、或上述實作方法之組合來實作。本發明之實施例可實作成執行在包含至少一處理器、儲存系統(包括揮發性和非揮發 性記憶體及/或儲存元件)、至少一輸入裝置、及至少一輸出裝置的可程式系統上的電腦程式或程式碼。
可對輸入指令施用如第8圖所示之代碼830的程式碼來執行本文所述之功能並產生輸出資訊。可以已知方式來將輸出資訊應用於一或更多輸出裝置。為了此應用之目的，處理系統包括任何具有處理器(例如，數位信號處理器(DSP)、微控制器、專用積體電路(ASIC)、或微處理器)之系統。
程式碼可以高階程序或物件導向程式語言來實作以與處理系統通訊。若需要的話，程式碼亦可以組合或機器語言來實作。事實上，本文敘述的機制並不受限於此領域的任何特定程式語言。在任何情況下，語言可以是已編譯或已轉譯之語言。
至少一實施例的一或更多態樣可藉由儲存在機器可讀媒體上的代表指令來實作，其表現在處理器內的各種邏輯，當機器讀取指令時，會使機器組裝邏輯來執行本文描述的技術。這樣的表現，稱為「IP核心」，可儲存在有形的機器可讀媒體上並供應至各種顧客或製造廠來下載至實際產生邏輯的製造機器或處理器中。
並非限制地，上述機器可讀儲存媒體可包括機器或裝置製造或形成的物件之非暫態、有形的排列，包括如硬碟、任何類型之磁碟(包括軟碟、光碟、唯讀光碟機(CD-ROM)、可抹寫光碟(CD-RW)、及磁光碟機)、如唯讀記憶體(ROM)的半導體裝置、如動態隨機存取記 憶體(DRAM)、靜態隨機存取記憶體(SRAM)的隨機存取記憶體(RAM)、可抹除可程式化唯讀記憶體(EPROM)、快閃記憶體、電子可抹除可程式化唯讀記憶體(EEPROM)、相變記憶體(PCM)、磁性或光學卡、或可適用於儲存電子指令的任何其他類型之媒體的儲存媒體。
因此，本發明之實施例也包括非暫態、有形的機器可讀媒體，其內含指令或包含設計資料，如硬體描述語言(HDL)，其定義本文描述的結構、電路、設備、處理器及/或系統特徵。上述實施例也可指程式產品。
儘管圖示中的流程圖顯示了本發明之某些實施例所進行的操作有特定順序，但應可了解到這樣的順序只是示範用的(例如，其他實施例可以不同順序來進行操作、合併某些操作、重疊某些操作、等等)。
在上面敘述中，為了解釋之目的，提出了許多具體細節以提供對於本發明之實施例的全面性了解。然而，本領域之熟知技術者將清楚明白無需這些具體細節便可實行一或更多其他實施例。所述之特定實施例不會提出來限制本發明，但可用來繪示本發明之實施例。本發明之範圍不是根據上面提出的具體實例來決定，而是僅根據下列之申請專利範圍來決定。
110‧‧‧虛擬機器
112‧‧‧虛擬機器
114‧‧‧虛擬機器
116‧‧‧觀察器
118‧‧‧主VMM
120‧‧‧CPU硬體
130‧‧‧計時器
132‧‧‧計時器事件
135‧‧‧範圍暫存器
142‧‧‧自發事件
160‧‧‧方塊箭頭
210‧‧‧SMI處理器
310-335‧‧‧操作
400‧‧‧管線
402‧‧‧提取級
404‧‧‧長度解碼級
406‧‧‧解碼級
408‧‧‧分配級
410‧‧‧更名級
412‧‧‧排程級
414‧‧‧暫存器讀取/記憶體讀取級
416‧‧‧執行級
418‧‧‧寫回/記憶體寫入級
422‧‧‧例外處理級
424‧‧‧提交級
430‧‧‧前端單元
432‧‧‧分支預測單元
434‧‧‧指令快取單元
436‧‧‧指令轉譯後備緩衝器
438‧‧‧指令提取單元
440‧‧‧解碼單元
450‧‧‧執行引擎單元
452‧‧‧更名/分配單元
454‧‧‧引退單元
456‧‧‧排程單元
458‧‧‧實體暫存器檔案單元
460‧‧‧執行叢集
462‧‧‧執行單元
464‧‧‧記憶體存取單元
470‧‧‧記憶體單元
472‧‧‧資料TLB單元
474‧‧‧資料快取單元
476‧‧‧第2級(L2)快取單元
490‧‧‧核心
500‧‧‧指令解碼器
502‧‧‧互連網路
504‧‧‧L2快取
506‧‧‧L1快取
508‧‧‧純量單元
510‧‧‧向量單元
512‧‧‧純量暫存器
514‧‧‧向量暫存器
506A‧‧‧L1資料快取
528‧‧‧16寬ALU
520‧‧‧攪和單元
524‧‧‧複製單元
526‧‧‧寫入遮罩暫存器
522A‧‧‧數字轉換單元
522B‧‧‧數字轉換單元
600‧‧‧處理器
602A-N‧‧‧核心
604A-N‧‧‧快取單元
606‧‧‧共享快取單元
608‧‧‧專用邏輯
610‧‧‧系統代理器
612‧‧‧環形基礎的互連單元
614‧‧‧整合記憶體控制器單元
616‧‧‧匯流排控制器單元
700‧‧‧系統
710‧‧‧處理器
715‧‧‧處理器
720‧‧‧控制器集線器
740‧‧‧記憶體
745‧‧‧協處理器
750‧‧‧輸入/輸出集線器
760‧‧‧輸入/輸出裝置
790‧‧‧圖形記憶體控制器集線器
795‧‧‧連線
800‧‧‧系統
850‧‧‧點對點互連
870‧‧‧第一處理器
880‧‧‧第二處理器
838‧‧‧協處理器
872‧‧‧整合記憶體控制器單元
882‧‧‧整合記憶體控制器單元
876‧‧‧對點介面電路
878‧‧‧對點介面電路
886‧‧‧對點介面電路
888‧‧‧對點介面電路
894‧‧‧對點介面電路
898‧‧‧對點介面電路
832‧‧‧記憶體
834‧‧‧記憶體
852‧‧‧P-P介面
854‧‧‧P-P介面
890‧‧‧晶片組
839‧‧‧高效能介面
896‧‧‧介面
816‧‧‧第一匯流排
814‧‧‧I/O裝置
818‧‧‧匯流排橋接器
820‧‧‧第二匯流排
822‧‧‧鍵盤/滑鼠
824‧‧‧音頻I/O
827‧‧‧通訊裝置
828‧‧‧儲存單元
830‧‧‧代碼和資料
900‧‧‧系統
872‧‧‧I/O控制邏輯
882‧‧‧I/O控制邏輯
914‧‧‧I/O裝置
915‧‧‧傳統I/O裝置
1000‧‧‧單晶片系統
1002‧‧‧互連單元
1010‧‧‧應用處理器
1020‧‧‧協處理器
1030‧‧‧靜態隨機存取記憶體單元
1032‧‧‧直接記憶體存取單元
1040‧‧‧顯示單元
本發明僅經由在附圖中的舉例，而非限定來說明，在 附圖中的相同參考數字係指類似元件，而其中：第1圖繪示根據一實施例之用於虛擬機器監視器運行時間完整性觀察器的硬體保護之示範系統；第2圖繪示示範SMI處理器210能存取第1圖之觀察器的代碼空間且防止從第1圖之觀察器存取SMI處理器的代碼空間；第3圖係繪示根據一實施例之提供VMM運行時間完整性檢查應用程式之硬體保護的系統所進行之示範操作的流程圖；第4A圖係繪示根據本發明之實施例之示範有序管線和示範暫存器更名、亂序發出/執行管線兩者的方塊圖；第4B圖係繪示根據本發明之實施例之包括在處理器中的有序架構核心之示範實施例和示範暫存器更名、亂序發出/執行架構核心兩者的方塊圖；第5A圖係根據本發明之實施例之單一處理器核心連同其連接單晶片互連網路的連線與其第2級(L2)快取的區域子集之方塊圖；第5R圖係根據本發明之實施例之第5A圖中的處理器核心之一部分的展開圖；第6圖係繪示根據本發明之實施例之可具有一個以上之核心、可具有整合記憶體控制器、及可具有整合圖形的處理器之方塊圖；第7圖係依照本發明之一實施例之系統的方塊圖；第8圖係依照本發明之實施例之第一更具體示範系統 的方塊圖；第9圖係依照本發明之實施例之第二更具體示範系統的方塊圖；及第10圖係依照本發明之實施例之SoC的方塊圖。
110‧‧‧虛擬機器
112‧‧‧虛擬機器
114‧‧‧虛擬機器
116‧‧‧觀察器
118‧‧‧主VMM
120‧‧‧CPU硬體
130‧‧‧計時器
132‧‧‧計時器事件
135‧‧‧範圍暫存器
140‧‧‧次級觀察器程式
142‧‧‧自發事件
150‧‧‧暫存器
160‧‧‧方塊箭頭
165‧‧‧完整性
170‧‧‧離開

Claims (13)

  1. 一種設備，包含：一組一或更多硬體範圍暫存器，用來保護用來儲存一虛擬機器監視器(VMM)運行時間完整性觀察器的一連續記憶體空間，其中該組硬體範圍暫存器是用來保護該VMM運行時間完整性觀察器免於當載入該連續記憶體空間中時被修改；及該VMM運行時間完整性觀察器，用來當該VMM運行時間完整性觀察器被執行時對一VMM進行在該VMM之運行時間期間的一完整性檢查。
  2. 如申請專利範圍第1項所述之設備，更包含：一硬體計時器，用來產生一事件以在該VMM之運行時間期間呼叫該VMM運行時間完整性觀察器的執行。
  3. 如申請專利範圍第2項所述之設備，其中在產生該事件之後立即先執行該VMM。
  4. 如申請專利範圍第1項所述之設備，其中該VMM運行時間完整性觀察器當被執行時更用來報告該完整性檢查的結果。
  5. 如申請專利範圍第4項所述之設備，其中該VMM運行時間完整性觀察器用來報告該完整性檢查的結果給一系統管理應用程式及一雲端管理應用程式之其一者。
  6. 如申請專利範圍第4項所述之設備，更包含：一組一或更多硬體報告暫存器；及其中該VMM運行時間完整性觀察器係用來寫入該組 硬體報告暫存器以指示是否已損害該VMM。
  7. 如申請專利範圍第6項所述之設備，其中該組硬體報告暫存器只可被該VMM運行時間完整性觀察器寫入以及可被任一實體讀取。
  8. 一種在一計算系統中的電腦實作方法，包含：將一虛擬機器監視器(VMM)運行時間完整性觀察器載入該計算系統的一連續記憶體空間中，其中該連續記憶體空間係藉由保護載入之該VMM運行時間完整性觀察器免於修改的一組一或更多硬體範圍暫存器來保護；偵測一事件以呼叫該VMM運行時間完整性觀察器的執行；反應於偵測到的該事件，執行該VMM運行時間完整性觀察器；及藉由該VMM運行時間完整性觀察器來對一VMM進行在該VMM之運行時間期間的一完整性檢查。
  9. 如申請專利範圍第8項所述之電腦實作方法，其中該事件係藉由被配置以週期性地產生事件的一硬體計時器產生。
  10. 如申請專利範圍第8項所述之電腦實作方法，其中反應於偵測到的該事件，先執行該VMM。
  11. 如申請專利範圍第8項所述之電腦實作方法，更包含：藉由該VMM運行時間完整性觀察器來報告該完整性檢查的一結果。
  12. 如申請專利範圍第11項所述之電腦實作方法，其中報告包括將該完整性檢查的該結果寫至一組一或更多硬體報告暫存器。
  13. 如申請專利範圍第11項所述之電腦實作方法，其中報告包括報告該完整性檢查的該結果給一系統管理應用程式及一雲端管理應用程式之其一者。
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