TWI456575B - Method for programming memory array - Google Patents

Claims (11)

A method for staging a memory array, wherein the memory array comprises a memory cell serially connected by a first transistor, a plurality of memory cells and a second transistor, and the memory array is stylized The method includes: turning off a switching memory cell in the memory cells during a setting phase, and applying a first voltage and a second voltage to a first source/drain region of the switching memory cell and a first a two source/drain region; and in a stylized phase, floating a bit line connected to the memory string and providing a ramp signal to a word line electrically connected to the switching memory . The method for staging a memory array according to claim 1, wherein the memory array further comprises a third transistor, the source terminal of the third transistor being electrically connected to the bit line, and being applied The step of the first voltage and the second voltage to the first source/drain region and the second source/drain region of the switching memory cell includes: turning on the memory cells except the switching memory cell a memory cell; conducting the first transistor, the second transistor and the third transistor; providing the first voltage to a drain terminal of the third transistor; and providing the second voltage to the second transistor A common source line electrically connected to the crystal. The method for programming a memory array according to claim 2, further comprising: in the stylizing phase, turning off the third transistor to float the bit line connected to the memory cell string. The method for staging a memory array according to claim 1, wherein the step of providing the ramp signal to the word line electrically connected to the switching memory comprises: one in the stylization phase a first sub-period providing a first sub-slope wave signal whose voltage level gradually rises to the word line; and during a second sub-segment of the stylized phase, providing a second sub-level of the voltage level gradually decreasing The ramp signal is connected to the word line, wherein the ramp signal is composed of the first sub-slope signal and the second sub-slope signal. The method for staging a memory array according to claim 1, wherein when the voltage difference between the first voltage and the second voltage is greater than a predetermined voltage, the program is programmed in the stylization phase. a selected memory cell adjacent to the switching memory cell in the memory cell, when the voltage difference between the first voltage and the second voltage is not greater than the predetermined voltage, prohibiting the selected memory cell in the stylized phase Stylized. A method for staging a memory array, wherein the memory array comprises a memory cell serially connected by a first transistor, a plurality of memory cells and a second transistor, and the memory array is stylized The method includes: turning off a switching memory cell of the memory cells during a setting phase, applying a first voltage to a first source/drain region of the switching memory cell, and turning off the second transistor And in a stylized phase, floating a bit line connected to the memory cell string, and applying a second voltage to a second source/drain region of the switching memory cell, and providing a ramp wave The signal is to a word line connected to the switching memory cell. The method for staging a memory array according to claim 6, wherein the memory array further comprises a third transistor, the source terminal of the third transistor being electrically connected to the bit line, and being applied The step of switching the first voltage to the first source/drain region of the switching memory cell includes: turning on a memory cell of the memory cells other than the switching memory cell; and turning on the first transistor and the third battery a crystal; and providing the first voltage to a drain terminal of the third transistor. The stylized method of the memory array of claim 7, further comprising: in the stylizing phase, turning off the third transistor to float the bit line connected to the memory cell string. The method for staging a memory array according to claim 6, wherein the applying the second voltage to the second source/drain region of the switching memory cell comprises: turning on the second transistor; And providing the second voltage to a common source line electrically connected to the second transistor. The method for staging a memory array according to claim 6, wherein the step of providing the ramp signal to the word line electrically connected to the switching memory comprises: one in the stylization phase a first sub-period providing a first sub-slope wave signal whose voltage level gradually rises to the word line; and during a second sub-segment of the stylized phase, providing a second sub-level of the voltage level gradually decreasing The ramp signal is connected to the word line, wherein the ramp signal is composed of the first sub-slope signal and the second sub-slope signal. The method for staging a memory array according to claim 6, wherein when the voltage difference between the first voltage and the second voltage is greater than a predetermined voltage, the program is programmed in the stylization phase. a selected memory cell adjacent to the switching memory cell in the memory cell, when the voltage difference between the first voltage and the second voltage is not greater than the predetermined voltage, prohibiting the selected memory cell in the stylized phase Stylized.