TWI451499B - Method of fabricating transistors and an transistor structure for improving short channel effect and drain induced barrier lowering - Google Patents

Description

Method for fabricating MOS transistor and MOS structure for improving short channel effect and buckling induced band reduction effect

The invention relates to a semiconductor device, a manufacturing method thereof and an improvement method, in particular to a method for fabricating a metal oxide semiconductor transistor and a metal oxide semiconductor transistor structure for improving a short channel effect and a drain-inducing band reduction effect.

As the line width of semiconductor processes continues to shrink, the size of metal oxide semi-transistors (MOSFETs) continues to evolve toward miniaturization. However, how to increase carrier mobility in the current case where the line width of semiconductor processes has developed to the bottleneck Increasing the speed of MOS transistors has become a major issue in the field of semiconductor technology.

Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used, which utilizes a lattice constant of germanium (SiGe) different from that of single crystal Si to make germanium The bismuth layer is structurally strained to form a strain enthalpy. Since the lattice constant of the tantalum layer is larger than that of the tantalum, this causes a change in the band structure of the tantalum, which causes an increase in carrier mobility, thereby increasing the speed of the PMOS transistor.

In addition, a selective epitaxial growth method is also used. After the gate is formed, a doped germanium is embedded in a predetermined region of the source/drain to form a squeezed strained germanium film to enhance the hole mobility of the PMOS. In general, in the selective epitaxial growth process, the germanium germanium filled in the predetermined region of the source/drain can improve the mobility of the strained PMOS, but at the same time, the electron mobility of the NMOS is also compromised. This in turn affects the performance of the transistor. Therefore, in the integrated process of forming a PMOS and an NMOS, when performing epitaxial growth and deuterium, a tantalum nitride is usually used as a mask to completely cover the NMOS region, and after the epitaxial deposition is completed, The tantalum nitride covering the NMOS is removed using hot phosphoric acid. However, when removing tantalum nitride, the hot phosphoric acid also erodes the surface of the germanium substrate located in the predetermined region of the NMOS source/drain, so that it moves downward relative to the dielectric surface between the gate dielectric layer of the NMOS and the substrate. Subsequent implantation of NMOS source/drain dopants will cause the p/n junction to be deeper than the pre-set depth, which will eventually lead to short channel effects and buck-induced energy band reduction (Drain Induced Barrier Lowering) , DIBL) effect.

Therefore, there is still a need for a MOS semi-transistor element and a method of manufacturing the same to improve the above problems.

In view of the above, it is a primary object of the present invention to provide a method of fabricating a metal oxide semi-transistor to improve the interface down-shift problem caused by the conventional removal of a mask on an NMOS.

According to the patent application scope of the present invention, a process of a metal oxide semi-electrode crystal formed on a substrate comprising a first type well and a second type well is disclosed, the process comprising the following steps First, a first gate is formed in the first well and a second gate is in the second well, and then a third sidewall is formed on the first gate, and then an epitaxial layer is formed respectively. Layered on the substrate on both sides of the first gate, and then forming a fourth sidewall on the second gate, and then forming a germanium overlay on the surface of the epitaxial layer and the fourth sidewall The surface of the substrate on both sides of the sub-substrate, then forming a first source/drain doped region in the substrate on both sides of the first gate and respectively forming a second source/drain doping The region is in the substrate on both sides of the second gate. According to the patent application of the present invention, the epitaxial layer is a germanium epitaxial layer. According to the patent application of the present invention, when the epitaxial layer is formed, the second well and the second gate are covered by a mask layer, and after the epitaxial layer is formed, at least part of the mask is removed. Floor.

According to the patent application scope of the present invention, there is further disclosed a metal oxide semi-transistor structure for improving a short channel effect and a drain-induced energy band reduction effect, the metal oxide semi-transistor structure comprising the following structure: a substrate comprising a P-type well a gate is disposed on the substrate of the P-type well, a sidewall is disposed on both sides of the gate, and an N-type source/drain-doped region is disposed in the substrate on both sides of the gate, A capping layer overlies the N-type source/drain doped region and a metal halide is disposed over the capping layer.

The present invention is characterized in that after the epitaxial layer is completed, a germanium cap layer is formed on the gate side of the PMOS and NMOS, that is, the source/drain doping regions of the PMOS and the NMOS, respectively. For the NMOS, it is possible to fill the surface down-shifted portion of the substrate surface near the NMOS gate when removing the mask layer, maintain the p/n junction at a predetermined depth, and avoid the short channel effect of the NMOS. The energy band induced by the bungee is reduced. In addition, after the epitaxial layer is completed, the mask layer may also form sidewalls of the NMOS gate.

1 to 9 are schematic views showing the process of fabricating a gold-oxygen semi-electrode according to the present invention. As shown in FIG. 1, a substrate 10 is first provided to include a first well 12 and a second well 14, wherein the first well 12 can be N-type or P-type, and the second well 14 can be relatively For the P type or the N type, in the following embodiments, the first type well 12 is an N type well and the second type well 14 is a P type well as an example, that is, in the following embodiments, A PMOS will eventually form on the well 12 and an NMOS will eventually form in the second well 14. In addition, the first well 12 and the second well 14 are surrounded by a shallow trench isolation (STI) 15 in the substrate 10 at the periphery thereof.

Then, a first gate 16 is formed on the first well 12 and a second gate 18 is formed on the second well 14, wherein the first gate 16 includes a first dielectric layer 20 disposed on the first gate 16 On the substrate 10, a first conductive layer 22 is disposed on the first dielectric layer 20, a first cap layer 24 is disposed on the first conductive layer 22, and a first sidewall 26 is disposed on the first dielectric layer 20. The first conductive layer 22 and the sidewall of the first cap layer 24. The second gate 18 includes a second dielectric layer 28 disposed on the substrate 10, a second conductive layer 30 disposed on the second dielectric layer 28, a second cap layer 32, and a second sidewall 34. The sidewalls of the second dielectric layer 28, the second conductive layer 30, and the second cap layer 32 are disposed. For example, the first dielectric layer 20 and the second dielectric layer 28 may be formed of a ruthenium oxide layer formed by a process such as thermal oxidation or deposition, or a high dielectric constant material layer having a dielectric constant greater than 4. The first conductive layer 22 and the second conductive layer 30 may be a conductive material such as polysilicon or may be a metal material having a specific work function, and the first cap layer 24 and the second cap layer 32 may be a tantalum nitride layer. It is composed, and the first cap layer 24 and the second cap layer 32 can be selectively formed. The first sidewall spacer 26 and the second sidewall spacer 34 are for subsequently forming a low doped region of a source/drain extension or the like, which may then remain in the structure or be removed. Then, the first gate 16 is used as a mask to form a first low doped region 36 in the substrate 10 on both sides of the first gate 16.

Thereafter, as shown in FIG. 2, a third sidewall 38 is further formed on the sidewall of the first gate 16, and while the third sidewall 38 is formed, a mask layer 40 is formed to cover the second well 14 and The second gate 18. The third sidewall sub-38 and the mask layer 40 may be formed by, for example, forming a tantalum nitride layer to cover the first well 12, the second well 14, the first gate 16, and the second gate. 18, after which a patterned photoresist (not shown) is formed to cover the second well 14 and the second gate 18, and the tantalum nitride layer not covered by the photoresist is removed by etching to form a third sidewall 38, and finally The photoresist is removed, and the tantalum nitride layer originally under the photoresist becomes the mask layer 40.

An epitaxial layer 42 is then formed in the substrate 10 on both sides of the first gate 16 respectively. In accordance with a preferred embodiment of the present invention, the PMOS epitaxial layer 42 may comprise only one germanium epitaxial layer 44, as shown in FIG. 2; and in accordance with another preferred embodiment of the present invention, as shown in FIG. The epitaxial layer 42 may also include a germanium epitaxial layer 44 and a single crystal germanium layer 46 on the germanium epitaxial layer 44. In general, the germanium epitaxial layer 44 can be formed by an embedded silicon Germanium (e-SiGe) process, for example, by the mask layer 40, the first gate 16 and the third sidewall. The protection of 38 is to etch two grooves (not shown) in the substrate 10 on both sides of the first gate 16 , and then pass the source material gas and the source material gas into the reaction chamber. Selectively forming the germanium epitaxial layer 44, or after the germanium epitaxial layer 44 is grown to a predetermined thickness, the germanium source material gas is turned off, and a single crystal germanium layer can be formed on the germanium epitaxial layer 44. 46. That is, in the present invention, the single crystal germanium layer 46 can be adjusted in thickness according to the process, and the single crystal germanium layer 46 can be selected, and even the germanium concentration in the germanium epitaxial layer 44 can be changed in a gradient according to the adjustment. .

After completing the embedded germanium (e-SiGe) process, as shown in FIG. 4, the first well 12 and the first gate 16 and the third sidewall 38 are covered by a patterned photoresist (not shown). . Next, a portion of the mask layer 40 is etched to form a fourth sidewall spacer 48 on the sidewall of the second gate 18, and then the photoresist is removed. According to another preferred embodiment of the present invention, the fourth sidewall spacer 48 can be formed by completely removing the third sidewall sub-38 and the mask layer 40, and then, as shown in FIG. 5, forming a After the material layer 50 conformably covers the second well 14, the first well 12, the first gate 16, and the second gate 18, as shown in FIG. 6, the portion of the material layer 50 is removed to be respectively A seventh sidewall 52 and a fourth sidewall 48 are formed on a gate 16 and a second gate 18. The process of the above-mentioned side wall is only a preferred embodiment of the present invention, and all changes and modifications made by the scope of the present invention should be within the scope of the present invention. Subsequent processes will be described in the fourth diagram.

As shown in FIG. 7, a cover layer 54 is formed on the surface of the epitaxial layer 42 on both sides of the first gate 16 and the surface of the substrate 10 on both sides of the second gate 18, and it can be said that the germanium cover layer 54 is formed on the surface. The locations of the source/drain doped regions are predetermined to be formed in the first well 12 and the second well 14. The ruthenium cover layer 54 may be a single crystal ruthenium. The formation of the ruthenium material may be, for example, formed by the above-described method of forming the epitaxial layer 42. Even the same reaction chamber as the epitaxial layer 42 may be used, and the material of the ruthenium source material may be again used. Opened and formed. In accordance with a preferred embodiment of the present invention, the ruthenium cover layer 54 has a thickness of 50 to 150 angstroms.

As shown in FIG. 8, the first well 12 is covered by a patterned photoresist (not shown), and the photoresist, the fourth sidewall 48 and the second gate 18 are doped as masks, respectively. A second low doped region 56 is in the substrate 10 on either side of the second gate 18. Then, a fifth sidewall 58 and a sixth sidewall 60 are formed on the sidewalls of the third sidewall 38 and the fourth sidewall 48, respectively, and the first cap layer 24 and the second cap layer 32 are removed. The first conductive layer 22 and the second conductive layer 30 are exposed. Next, a P-type first source/drain doping region 62 is formed in the substrate 10 on both sides of the first gate 16 and an N-type second source/drain doping region 64 is formed. In the substrate 10 on both sides of the two gates 18, at this time, the PMOS 66 and NMOS 68 of the present invention have been completed. Of course, the order in which the first source/drain doping region 62 and the second source/drain doping region 64 are formed may be changed according to the product process. In addition, the position formed by the first source/drain doping region 62 and the epitaxial layer 42 partially overlap.

As shown in FIG. 9, a metal deuteration process is performed to cause at least a portion of the exposed first conductive layer 22, the second conductive layer 30, and the germanium cap layer 54 to become the metal germanium layer 55. Then, other strain memory technologies (SMT) such as contact etch stop layer (CESL) and dual stress layer (DSL) can be selectively integrated to further improve the performance of the MOS. Subsequently, an internal electrical connection line can be fabricated, for example, an interlayer dielectric layer is formed to cover the PMOS 66 and the NMOS 68, and contact plugs are formed in the interlayer dielectric layer to electrically connect the first gate 16 and the second gate 18, respectively. The first source/drain doping region 62 and the second source/drain doping region 64 and the like are not so much. In addition, the present invention is also applicable to an embedded SiC process to improve NMOS current drive. For example, when the steps of FIG. 2 or FIG. 3 are performed, the germanium epitaxial layer is replaced with a tantalum carbide epitaxial layer.

Since the above embodiment forms a mask layer 40 on the second well 14 when the epitaxial layer 42 is formed, at least a portion of the mask layer 40 is removed after the epitaxial layer 42 is completed. When removed, the surface of the substrate 10 on both sides of the second gate 18 is etched, which will inevitably cause the surface of the substrate 10 on both sides of the second gate 18 to be opposite to the second dielectric layer. 28 and the interface 11 of the substrate 10 are lowered, and the position of the interface 11 is shown in Fig. 4. Therefore, one feature of the present invention is that after the mask layer 40 is partially removed, a source/drain doping region of the PMOS 66 and the NMOS 68 is formed on both sides of the gates of the PMOS 66 and the NMOS 68, that is, the source/drain doping regions of the PMOS 66 and the NMOS 68, respectively. Cover layer 54. Referring to FIG. 9, the germanium cap layer 54 can fill the bottom surface of the substrate near the NMOS gate for the NMOS 68 to maintain the p/n junction at a predetermined depth to avoid the short channel effect of the NMOS. The extremely induced energy band reduction effect, in addition, since the surface of the substrate 10 is lowered, the portion of the germanium cap layer 54 which is later formed on the NMOS 68 is lower than the interface 11. For PMOS 66, germanium cap layer 54 is primarily used to form metal germanide 55. In addition, after the epitaxial layer 42 is completed, the mask layer 40 originally used to protect the second well 14 and the second gate 18 may also form a sidewall of the gate of the NMOS 68.

In addition, the present invention also provides an N-type oxy-oxygen semi-transistor structure which improves short-channel effect and drain-induced energy band-reducing effect, and FIG. 10 illustrates a preferred embodiment according to the present invention. A side view of a N-type gold oxide semi-electrode. As shown in FIG. 10, the structure of the NMOS 168 of the present invention comprises: a substrate 100 comprising a P-well 114, a gate 118 disposed on the substrate 10 of the P-well 114, and a sidewall 150 disposed at the gate. 118, a shallow doped region 156 is disposed in the substrate 100 below the sidewall sub-150, and an N-type source/drain doping region 164 is disposed in the substrate 100 on both sides of the gate 150, covered by a cover layer 154 A N-type source/drain doping region 164 and a metal telluride 155 are disposed on the germanium cap layer 154. In addition, a shallow trench isolation (STI) 115 surrounds the substrate 100 on the periphery of a P-well 114. The gate 118 includes a dielectric layer 128 disposed on the substrate 100 and a conductive layer 130 disposed on the dielectric layer 128. Further, the sidewall spacer 150 is a composite sidewall including a sidewall 134, a sidewall 148, and a sidewall. The sub-160 is disposed on the sidewall of the gate 118. Further, the ruthenium cover layer 154 has a thickness of 50 to 150 angstroms and is composed of single crystal ruthenium. Furthermore, the outer surface of the metal telluride 155 is elevated compared to the interface between the dielectric layer 128 and the substrate 100.

In summary, one feature of the present invention is that the source/drain doping region 164 of the NMOS 168 has a germanium cap layer 154 that avoids the short channel effect of the NMOS and the band-reduction effect induced by the drain.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 100‧‧‧ base

12‧‧‧First Well

14‧‧‧Second type well

15, 115‧‧‧ shallow trench isolation

16‧‧‧First Gate

18‧‧‧second gate

20‧‧‧First dielectric layer

22‧‧‧First conductive layer

24‧‧‧First cover

26‧‧‧First side wall

28‧‧‧Second dielectric layer

30‧‧‧Second conductive layer

32‧‧‧Second top cover

34‧‧‧Second side wall

36‧‧‧First low doped area

38‧‧‧ third side wall

40‧‧‧mask layer

42‧‧‧ epitaxial layer

44‧‧‧矽锗 矽锗 layer

46‧‧‧ Single crystal layer

48‧‧‧ fourth side wall

50‧‧‧Material layer

52‧‧‧ seventh side wall

54‧‧‧矽 overlay

55‧‧‧Metalized layer

56‧‧‧Second low doped area

58‧‧‧ Fifth side wall

60‧‧‧ sixth side wall

62‧‧‧First source/deuterium doped region

64‧‧‧Second source/drain-doped region

66‧‧‧ PMOS

68, 168‧‧‧ NMOS

114‧‧‧P type well

118‧‧‧ gate

156‧‧‧ shallow doped area

128‧‧‧ dielectric layer

134, 148, 150, 160‧‧‧ side wall

154‧‧‧矽 overlay

155‧‧‧Metal Telluride

164‧‧‧N type source/drain doping area

11‧‧‧ interface

1 to 9 are schematic views showing the process of fabricating a gold-oxygen semi-electrode according to the present invention.

Figure 10 is a side elevational view of a gold oxide semi-electrode in accordance with a preferred embodiment of the present invention.

10‧‧‧Base

12‧‧‧First Well

14‧‧‧Second type well

15‧‧‧Shallow trench isolation

16‧‧‧First Gate

18‧‧‧second gate

20‧‧‧First dielectric layer

22‧‧‧First conductive layer

26‧‧‧First side wall

28‧‧‧Second dielectric layer

30‧‧‧Second conductive layer

34‧‧‧Second side wall

36‧‧‧First low doped area

38‧‧‧ third side wall

42‧‧‧ epitaxial layer

44‧‧‧矽锗 矽锗 layer

46‧‧‧ Single crystal layer

48‧‧‧ fourth side wall

54‧‧‧矽 overlay

55‧‧‧Metalized layer

56‧‧‧Second low doped area

58‧‧‧ Fifth side wall

60‧‧‧ sixth side wall

62‧‧‧First source/deuterium doped region

64‧‧‧Second source/drain-doped region

66‧‧‧ PMOS

68‧‧‧NMOS

11‧‧‧ interface

Claims (19)

A process for a gold-oxygen semiconductor, comprising: providing a substrate comprising a first type well and a second type well; forming a first gate to the first type well and a second gate to the second type Forming a third sidewall on the first gate; forming an epitaxial layer in the substrate on each side of the first gate; forming a fourth sidewall on the second gate; respectively forming a cover layer on the surface of the epitaxial layer and the substrate surface on both sides of the fourth sidewall; forming a first source/drain doped region on the substrate on both sides of the first gate And forming a second source/drain doped region in the substrate on both sides of the second gate. The method of claim 1, wherein before forming the third sidewall, the method further comprises: forming a first low doped region in the substrate on each side of the first gate. The method of claim 1, wherein after forming the germanium cap layer and before forming the first source/drain doping region, further comprising: forming a second low doping region in the second And a sidewall of the third sidewall and a sixth sidewall are respectively formed on the sidewall of the third sidewall and the fourth sidewall. The method of claim 1, wherein a mask layer is formed to cover the second well and the second gate while forming the third sidewall. The method of claim 4, wherein after forming the epitaxial layer, further comprising: removing a portion of the mask layer to form the fourth sidewall. The method of claim 4, wherein the mask layer is used as a mask for the second type well when the epitaxial layer is formed. The method of claim 4, after the forming the epitaxial layer, further comprising: removing the mask layer and the third sidewall; forming a material layer covering the second well, the first a type well, the first gate and the second gate; and removing a portion of the material layer to form a seventh sidewall and the fourth sidewall on the first gate and the second gate, respectively child. The method of claim 1, wherein the epitaxial layer comprises a tantalum epitaxial layer. The method of claim 1, wherein the epitaxial layer comprises a germanium epitaxial layer and a single crystal germanium layer on the germanium epitaxial layer. The method of claim 1, wherein the second source/drain is formed After the miscellaneous zone, another inclusion; a metal deuteration process is performed on the crucible cover layer. The method of claim 1, wherein the first gate comprises: a first dielectric layer disposed on the substrate, a first conductive layer disposed on the first dielectric layer, and a first sidewall The sub-layer is disposed on sidewalls of the first dielectric layer and the first conductive layer. The method of claim 1, wherein the second gate comprises: a second dielectric layer disposed on the substrate, a second conductive layer disposed on the second dielectric layer, and a second sidewall The sub-layer is disposed on sidewalls of the second dielectric layer and the second conductive layer. The method of claim 1, wherein the ruthenium cover layer has a thickness of 50 to 150 angstroms. The method of claim 1, wherein the epitaxial layer overlaps a portion of the first source/drain doped region. A gold-oxygen semi-transistor structure for improving short-channel effect and bungee-induced energy band reduction effect, comprising: a substrate comprising a P-type well; a gate disposed on the substrate of the P-type well; a dielectric layer Between the gate and the substrate, wherein the substrate and the dielectric layer have an interface; a sidewall is disposed on the gate; An N-type source/drain doping region is disposed in the substrate on both sides of the gate; a germanium cap layer covers the N-type source/drain doped region, and a portion of the germanium cap layer is low And the metal bismuth compound is disposed on the enamel cover layer. The structure of claim 15 further comprising a shallow doped region disposed in the substrate below the sidewall. The structure of claim 15, wherein the enamel cover layer has a thickness of 50 to 150 angstroms. The structure of claim 15, wherein the gate comprises a dielectric layer disposed on the substrate and a conductive layer disposed on the dielectric layer. The structure of claim 18, wherein the outer surface of the metal halide is elevated compared to the interface between the dielectric layer and the substrate.