TWI451286B - The system and methods of burglarproof apparatus for the central processing unit - Google Patents

Description

Central processor anti-theft device, system thereof and method thereof

The present invention relates to anti-theft systems, and more particularly to central processor anti-theft devices, systems thereof, and methods therefor.

Computers are a must-have tool for many people to work or play. Due to the advancement of computer technology, the computing power of personal computers, workstations or servers has been further improved. In particular, workstations and servers usually have a plurality of central processing units (CPUs). The most important component in a computer is the central processing unit, and the main part of the overall cost of the computer is the cost of the central processing unit.

In addition, in the current market environment where computer components are easy to sell, usually the owner or custodian of the computer may think that the risk of computer components being stolen is greater than the risk of the entire computer being stolen. The central processor is small, easy to install and disassemble, expensive, and after the central processor is stolen, the computer's mainframe may remain in place and not easily perceived by managers. More importantly, a workstation or server can typically have two, three or more central processors, and workstations or servers with multiple central processors can be removed, regardless of whether one or more central processors are removed. As long as a central processing unit is still in place, the workstation or server can continue to operate, and it is not easy for managers to detect abnormalities if they do not carefully check the internal parts of the computer.

Embodiments of the present invention provide a central processor anti-theft system for monitoring at least one central processor of a computer, and the central processor anti-theft system includes a central processor anti-theft device and an alarm device. The central processor anti-theft device includes a capacitor, a detection circuit, a control circuit, and a transmission circuit. The capacitor is electrically coupled to a power supply of the computer. The detecting circuit has a first end and at least a second end, and the first end of the detecting circuit is electrically coupled to the capacitor. The second end of the detection circuit is electrically coupled to the central processing unit. When the central processor is electrically separated from the second end of the detection circuit, the detection circuit generates a detection signal accordingly. The control circuit is electrically coupled to the second end of the capacitor and the detecting circuit. The control circuit generates a status signal based on the detected signal. The transmission circuit is electrically coupled to the control circuit and the capacitor, and the transmission circuit receives the status signal from the control circuit and transmits the status signal to the alarm device. When the central processor is electrically separated from the second end of the detection circuit, the alarm device generates an alarm signal according to the status signal. When the computer's power supply is powered off, the capacitor is used to provide power to the control circuit, the detection circuit, and the wireless transmission circuit.

The embodiment of the invention further provides a central processor anti-theft method, which is implemented in the central processor anti-theft device, and the central processor anti-theft device comprises a capacitor, a detecting circuit and a control circuit. The capacitors provide power to the detection circuit and the control circuit, respectively. The detection circuit is electrically coupled to at least one central processor of the computer. The method includes the following steps. First, the detection circuit obtains a first state value of the central processing unit when the computer is powered on. Then, the detecting circuit obtains the second state value of the central processing unit after the computer is turned on. Then, the control circuit compares the first state value with the second state value, and accordingly determines whether the central processor is electrically separated from the detecting circuit.

The embodiment of the invention further provides a central processor anti-theft device for installing on a computer having at least one central processor, the central processor anti-theft device comprising a capacitor, a detection circuit and a control circuit. The capacitor is electrically coupled to a power supply of the computer. The detecting circuit has a first end and at least one second end. The first end of the detecting circuit is electrically coupled to the capacitor, and the second end of the detecting circuit is electrically coupled to the at least one central processing unit. When the central processor is electrically separated from the second end of the detection circuit, the detection circuit generates a detection signal accordingly. The control circuit is electrically coupled to the capacitor and the second end of the detection circuit, and the control circuit generates a status signal according to the detection signal. When the power supply of the computer is powered off, the capacitor is used to provide power to the control circuit and the detection circuit.

In summary, the central processor anti-theft system and method thereof provided by the embodiments of the present invention can monitor whether the central processor of the computer is removed or stolen. When the central processor is removed, the control circuit generates a status signal and provides an alert. The central processor anti-theft device of the central processor anti-theft system can wirelessly transmit status signals to the alarm device of the central processor anti-theft system to generate an alarm. In addition, the central processor anti-theft system can continue to function when the computer's power supply is powered down. In other words, the central processor anti-theft system can continuously monitor whether the central processor has been removed or stolen while the computer is powered off.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

[Embodiment of Central Processor Anti-theft System]

Please refer to FIG. 1. FIG. 1 is a circuit block diagram of a central processor anti-theft system according to an embodiment of the present invention. The central processor anti-theft system 100 is used to monitor at least one central processor (15, 16) of a computer (not shown). In the present embodiment, the two central processors 15, 16 are monitored as an example, but the present invention is not limited thereto. The central processor anti-theft system 100 includes a central processor anti-theft device 1 and an alarm device 17. The central processor theft prevention device 1 includes a capacitor 11, a detection circuit 14, a control circuit 12, and a wireless transmission circuit 13.

The capacitor 11 is electrically coupled to the power supply 10 of the computer. The detection circuit 14 having a first end and a second end DA ^DB, DB,, and the first terminals of the DA detecting circuit 14 is electrically coupled to the capacitor 11. The second ends DB and DB' of the detecting circuit 14 are electrically coupled to the central processing units 15 and 16, respectively. The control circuit 12 is electrically coupled to the capacitor 11 and the second ends DB, DB' of the detection circuit 14. The wireless transmission circuit 13 is electrically coupled to the control circuit 12 and the capacitor 11.

Referring to FIG. 1, the capacitor 11 of FIG. 1 is only a schematic diagram. In fact, the capacitor 11 usually has two ends, one end of the capacitor 11 can be connected to the voltage output end of the power supply 10, and the other end of the capacitor 11 is connected to the central processor anti-theft system. 100 shared ground with the computer. When the power supply 10 of the computer is powered (or when the computer is turned on), the capacitor 11 supplies power from the power supply 10 to the control circuit 12, the detection circuit 14 and the wireless transmission circuit 13, while the capacitor 11 is continuously charged. In other words, the capacitor 11 continuously stores power from the power supply 10. When the power supply 10 is powered off, since the capacitor 11 has stored power, the capacitor 11 can continue to supply power to the control circuit 12, the detection circuit 14, and the wireless transmission circuit 13.

It should be noted that if the capacitor 11 is not coupled between the CPU anti-theft device 1 and the power supply 10, the CPU anti-theft device 1 cannot continue to monitor the central processing when the power supply 10 is powered off. Whether the device was removed. In addition, in order for the central processor theft prevention device 1 to reduce the power consumption of the capacitor 11, the central processor theft prevention device 1 can be enabled when the central processing unit 15 or 16 is removed, whereby the central processing unit is not removed. When it is stolen, the power consumed by the central processor theft prevention device 1 can be minimized, but the invention is not limited thereto. Next, the operation of the central processor theft prevention device 1 will be described in detail.

Referring back to FIG. 1, the detecting circuit 14 is configured to detect whether the central processing unit 15 (or 16) is removed. In the present embodiment, the detecting circuit 14 is implemented as a resistor R1 (or R2), but the present invention is not limited thereto. The method of implementing the detecting circuit 14 by a passive component such as a resistor can reduce power consumption. The first terminal DA of the detection circuit 14 is connected to the capacitor 11. In the present embodiment, the power supply 10 or the capacitor 11 (in the case where the power supply 10 is not powered) provides a voltage of 3.3 volts to the detection circuit 14. The second end DB (or DB') of the detection circuit 14 can be connected to one of the pins of the central processing unit, which can be the ground pin of the central processing unit. In the event that the central processor is not removed, the second end DB (or DB') of the detection circuit 14 can have the same voltage level as the ground. When the central processing unit 15 (or 16) is removed or stolen, the second end DB (or DB') of the detecting circuit 14 is electrically separated from the ground, so the second end DB of the detecting circuit 14 (or DB') is pulled up to a voltage level of 3.3 volts.

In other words, when the central processing unit 15 (or 16) is electrically coupled to the second end DB (or DB') of the detecting circuit 14, the second end DB (or DB') of the detecting circuit 14 has the first a voltage level (for example, ground), when the central processing unit 15 (or 16) is electrically separated from the second end DB (or DB') of the detecting circuit 14, the second end DB of the detecting circuit 14 (or DB') has a second voltage level. When the central processing unit 15 (or 16) is electrically separated from the second end DB (or DB') of the detecting circuit 14, the detecting circuit 14 can generate the detecting signal Vc according to the detection signal Vc. The second voltage level (3.3 volts in this embodiment).

Referring back to FIG. 1, the control circuit 12 generates a status signal CS based on the detection signal Vc. The source of power for control circuit 12 is power supply 10 or capacitor 11 (in the case where power supply 10 is not powered), as shown in the 3.3 volt voltage source. The control circuit 12 can be implemented using a Complex Programmable Logic Device (CPLD), but the present invention is not limited thereto. When the control circuit 12 is implemented using a conventional complex programmable logic device (CPLD), the programming information of the complex programmable logic device (CPLD) does not disappear even after the power supply is stopped, and the complex programmable logic device (CPLD) is re-powered. ) You can continue to execute the originally set programming instructions. In addition, in order to save power consumption, the control circuit 12 may be designed to transmit the status signal CS and transmit it to the wireless transmission circuit 13 only when the central processing unit 15 (or 16) is removed, but the present invention is not limited thereto. The control circuit 12 can also transmit the status signal CS to the wireless transmission circuit 13 to cause the wireless transmission circuit to transmit a status signal to the alarm device 17.

It should be noted that the control circuit 12 can receive a reset signal RST that is transmitted to the control circuit 12 when the computer is turned back on, whereby the control circuit 12 can obtain the state of the central processor when the computer is restarted. . For example, the control circuit 12 can determine the number of central processors when the computer is turned back on according to the voltage level of the second end DB (or DB') of the detection circuit. The number of central processors when the computer is turned back on can also be used as a basis for the control circuit 12 to determine whether the number of central processors installed in the computer has changed.

Referring back to FIG. 1, the wireless transmission circuit 13 receives the status signal CS from the control circuit 12 and wirelessly transmits the status signal CS to the alarm device 17. The source of power for the wireless transmission circuit 13 is the power supply of the power supply 10 or capacitor 11 (in the case where the power supply 10 is not powered), such as the 3.3 volt voltage source shown in FIG. The wireless transmission circuit 13 may be a radio frequency circuit or an infrared transmission circuit, but the present invention does not limit the embodiment of the wireless transmission circuit 13. The wireless transmission circuit 13 can also be replaced by a wired transmission circuit. Compared with the wired transmission circuit, the wireless transmission circuit 13 can prevent the thief from removing the transmission cable and failing to detect the central processor 15 (or 16) being stolen. Case.

Referring back to FIG. 1, the alarm device 17 includes a remote host 171, an alarm 172, and a storage unit 173. The remote host 171 is electrically coupled to the alarm 172 and the storage unit 173. The remote host 171 has a wireless receiver corresponding to the wireless transmission circuit 13, for example, the remote host 171 is a computer having a radio frequency receiver. When the central processing unit 15 (or 16) is electrically separated from the second end DB (or DB') of the detecting circuit, the alarm device 17 generates an alarm signal in accordance with the status signal CS. The alarm signal can be sent through the alarm 172, which can be a light, sound, etc., which is easily noticeable. For example, the alarm is a display or an audio device. The administrator of the computer can know that the central processing unit 15 (or 16) is removed according to the alarm signal, and then rush to the location of the computer to confirm the status of the computer.

In addition, the remote host 171 can also store the status signal CS to the storage unit 173 for the administrator to look up later. The manner in which the storage unit 173 stores the status signal CS may be the time at which the source computer including the status signal CS and the status signal CS occur. For example, the storage unit 173 can store the status signal CS, the source computer of the status signal CS, and the time when the status signal CS occurs as a piece of data. The alarm device 17 can use the data stored in the storage unit 173 to match the video (or monitoring) device and the access control system to find out who is present when the central processor 15 (or 16) is removed or stolen. Evidence that the central processor 15 (or 16) was removed or stolen.

[Embodiment of Central Processor Anti-theft Method]

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 2 is a control state diagram of a control circuit of the central processor anti-theft device according to the embodiment of the present invention. The central processor theft prevention method of the present embodiment can be implemented in the central processor theft prevention device 1 of the central processor theft prevention system 100 of FIG. 1, and is explained by taking two central processors as an example. Before describing the central processor theft prevention method of the present embodiment, the control flow of the control circuit 12 of Fig. 1 will be further explained. First, in state S10, the state value of the central processing unit before the computer is turned on is set. Before the computer has been turned on, the control circuit 12 can set an initial value of the state value of the central processor, for example, the state value is set to X, and the state value represents a state value when the computer is not turned on, and is used when the central processor is removed. Make a difference.

Then, in state S20, the central processor state value when the computer is powered on (or referred to as the power-on instant) is set. When the user of the computer presses the power button of the computer, the computer is activated and the control circuit 12 receives the reset signal RST at which the power button is pressed, whereby the control circuit 12 can determine whether the installation of the central processor is correct. For example: determine if the central processor of the computer is fully equipped with a central processor. If the central processor is not installed correctly, the status value is High. If the central processor is installed correctly, the status value is Low. In addition, the control circuit 12 can record the state value of the central processing unit at the time of power-on, and can use the status value at this time as a comparison reference point for the subsequent monitoring of the state of the central processing unit.

Next, in state S30, it is monitored whether the state value of the central processor changes after the computer is turned on. State S30 can be continued as long as capacitor 11 is energized and capacitor 11 is sufficient to provide power to the central processor anti-theft device 1. Until the capacitor 11 is depleted or insufficient to provide power, the central processor theft prevention device 1 returns to the state S10. When the control unit 12 finds that the state of the central processor is different from that at the time of power-on, the control circuit 12 can perform a determination as to whether to trigger the wireless transmission circuit to transmit the status signal according to the design of the algorithm. The algorithm of the control circuit 12 of the central processor anti-theft system 100 will be exemplified in the following description. The flow of steps of the central processor theft prevention method of the present embodiment will be described first.

Please refer to FIG. 1 to FIG. 3 simultaneously. FIG. 3 is a flowchart of a method for preventing theft of a central processing unit according to an embodiment of the present invention. The state diagram of Figure 2 can be implemented using the flow chart of Figure 3. First, in step S310, the first state value of the central processing unit 15, 16 is set before the computer is turned on. In Fig. 2, the first state value of the central processing unit 15 (or 16) is set in accordance with the voltage level of the second terminal DB (or DB') of the detecting circuit 14.

Then, in step S320, the detecting circuit 14 obtains the first state value of the central processing unit when the computer is turned on. When the user of the computer presses the power button of the computer, the control circuit 12 can determine whether the installation of the central processing unit 15, 16 is correct. If the central processing unit 15, 6 is not installed correctly or is not installed, the first status value is "1". If the central processor is installed correctly, the first state value is converted from the value X before power-on to a value of "0".

Next, in step S330, the detecting circuit 14 obtains the second state value of the central processing unit 15, 16 after the computer is turned on. If the central processing unit 15, 16 is removed (or referred to as not installed), the second status value is "1". If the central processor is not removed (or is installed), the second state value is a value of "0".

Then, in step S340, the control circuit 12 compares whether the first state value and the second state value are different. The control circuit 12 can determine whether the central processing unit 15, 16 is electrically separated from the detection circuit 14 accordingly. When the first state value is different from the second state value, step S350 is performed, otherwise, step S330 is performed again. In step S350, the control circuit 12 of the central processor theft prevention device 1 generates a status signal CS. The state signal CS can be a voltage value at which the control circuit 12 generates a high potential. Accordingly, the transmission circuit 13 of FIG. 1 can transmit the status signal CS to the alarm device 17. After the end of step S350, step S330 is performed again until the power of the capacitor 11 of Fig. 1 is exhausted. If the capacitor 11 is charged again, the above steps S310 to S350 can be executed again. The case where the capacitor 11 is charged again may be that the computer is turned on again or the power supply 10 of the computer resumes power supply.

Please refer to FIG. 3 and FIG. 4 simultaneously. FIG. 4 is a schematic diagram of an algorithm for the anti-theft method of the central processing unit according to the embodiment of the present invention. The algorithm of Figure 4 is the case of monitoring two central processors. The two central processors are a first central processing unit P0 and a second central processing unit P1, respectively. As can be seen from FIG. 4, the state signal CS before power-on is at a high voltage level. At the time of power on, if the first central processing unit P0 is not installed, the status signal CS is still at the high voltage level. At the time of power-on, if the first central processing unit P0 is installed, the status signal CS is changed from the high voltage level to the low (low) voltage level.

In this embodiment, the first central processing unit P0 needs to be installed in the slot corresponding to the device before the second central processing unit P1 can be installed. In other words, when the second central processing unit P1 is installed but the first central processing unit P0 is not installed, the status signal CS is at a high voltage level. It should be noted that the embodiment of FIG. 4 is only one embodiment of the present invention. In other embodiments, if any central processing unit is installed at the time of power on, the status signal CS will become a low voltage level. .

In the case after power-on, there are different algorithms depending on the situation at boot time. In the case where only one central processing unit is installed at the time of power-on (for example, the first central processing unit), the status signal CS maintains a low voltage level when the central processing unit still exists (or is called installed) after being turned on. When the central processor is removed (or is not installed) after powering on, the status signal CS changes to a high voltage level. In the case where both CPUs are installed at power-on, when any of the two central processors is removed (or is not installed) after being turned on, the status signal CS is changed to a high voltage level. .

Please refer to FIG. 3, FIG. 5A and FIG. 5B as a schematic diagram of another algorithm of the central processor anti-theft method according to the embodiment of the present invention. The principles of the algorithms of Figures 5A and 5B are the same as those of Figure 4, except that the number of monitored central processors is changed from two to three. Figure 5A illustrates several possible scenarios for the installed central processor when the computer is powered on. Fig. 5B illustrates the state of the central processing unit after power-on, which is derived from the state of the central processing unit at power-on. In principle, after the power is turned on, if the central processing unit is removed (or not installed), the status signal is changed from the low voltage level to the high voltage level.

[Possible efficacy of the embodiment]

According to an embodiment of the invention, the above described central processor antitheft system and method thereof can monitor whether the central processor of the computer is removed or stolen. When the central processor is removed, the control circuit generates a status signal and provides an alert. The central processor anti-theft device of the central processor anti-theft system can wirelessly transmit status signals to the alarm device of the central processor anti-theft system to generate an alarm. In addition, the central processor anti-theft system can continue to function when the computer's power supply is powered down. In other words, the central processor anti-theft system can continuously monitor whether the central processor has been removed or stolen while the computer is powered off.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

100. . . Central processor anti-theft system

1. . . Central processor anti-theft device

10. . . Power Supplier

11. . . capacitance

12. . . Control circuit

13. . . Wireless transmission circuit

14. . . Detection circuit

15,16. . . CPU

17. . . Alarm device

171. . . Remote host

172. . . Alarm

173. . . Storage unit

R1, R2. . . resistance

S10~S30. . . Control state

S310～S350. . . Step flow

1 is a circuit block diagram of a central processor anti-theft system in accordance with an embodiment of the present invention.

2 is a control state diagram of a control circuit of the central processor theft prevention device according to the embodiment of the present invention.

3 is a flow chart of a method for preventing theft of a central processing unit according to an embodiment of the present invention.

4 is a schematic diagram of an algorithm of a central processor anti-theft method according to an embodiment of the present invention.

5A and FIG. 5B are schematic diagrams showing another algorithm of the anti-theft method of the central processing unit according to the embodiment of the present invention.

100. . . Central processor anti-theft system

1. . . Central processor anti-theft device

10. . . Power Supplier

11. . . capacitance

12. . . Control circuit

13. . . Wireless transmission circuit

14. . . Detection circuit

15,16. . . CPU

17. . . Alarm device

171. . . Remote host

172. . . Alarm

173. . . Storage unit

R1, R2. . . resistance

Claims (12)

A central processing unit anti-theft system for monitoring at least one central processing unit of a computer, the central processing unit anti-theft system comprising: a central processing unit anti-theft device comprising: a capacitor for electrically coupling to one of the computers a power supply device; the detection circuit has a first end and at least a second end, the first end of the detecting circuit is electrically coupled to the capacitor, and the second end of the detecting circuit The detection circuit generates a detection signal; the control circuit is electrically coupled to the second processor. The detection circuit generates a detection signal according to the second processor. Connecting the capacitor and the second end of the detecting circuit, the control circuit generates a state signal according to the detecting signal; and a transmitting circuit electrically coupled to the control circuit and the capacitor to receive the current from the control circuit a status signal and transmitting the status signal; and an alarm device receiving the status signal from the transmission circuit, wherein the alarm is installed when the central processor is electrically separated from the second end of the detection circuit Generating an alarm signal according to the state signal; wherein when the power supply of the computer is powered off, the capacitor for providing power to the control circuit, the detection circuit and the wireless transmission circuitry. The central processor anti-theft system of claim 1, wherein the transmission circuit is a wireless transmission circuit, and the alarm device wirelessly receives the status signal. The central processor anti-theft system of claim 1, wherein when the central processor is electrically coupled to the second end of the detecting circuit, the second end of the detecting circuit has a first a voltage level, when the central processor is electrically separated from the second end of the detecting circuit, the second end of the detecting circuit has a second voltage level. The central processor anti-theft system of claim 1, wherein the control circuit is further configured to receive a start signal generated by the computer, and the control circuit sets the detection signal according to the detection signal when the start signal is generated. An initial value of the status signal. The central processor anti-theft system of claim 1, wherein the alarm device further comprises a storage unit for recording the status signal. A central processor anti-theft method is implemented in a central processor anti-theft device, the central processor anti-theft device includes a capacitor, a detecting circuit and a control circuit, the capacitor respectively supplying power to the detecting circuit and the control circuit The detecting circuit is configured to be electrically coupled to at least one central processing unit of a computer, the method comprising: obtaining, by the detecting circuit, a first state value of the central processing unit when the computer is powered on; the detecting circuit Obtaining a second state value of the central processing unit after the computer is powered on; and the control circuit comparing the first state value with the second state value, and determining whether the central processing unit is electrically connected to the detecting circuit Separation. The central processor anti-theft method of claim 6, further comprising: setting the first state value of the central processor before the computer is powered on. The central processor anti-theft method of claim 6, further comprising: when the first state value is different from the second state value, the central processor anti-theft device generates a status signal. A central processing unit anti-theft device for mounting on a computer, the computer having at least one central processing unit, the central processing unit anti-theft device comprising: a capacitor for electrically coupling to a power supply of the computer; a detecting circuit having a first end and at least a second end, the first end of the detecting circuit is electrically coupled to the capacitor, and the second end of the detecting circuit is electrically coupled Connected to the central processing unit, when the central processing unit is electrically separated from the second end of the detecting circuit, the detecting circuit generates a detection signal accordingly; and a control circuit electrically coupled to the capacitor and The second end of the detecting circuit, the control circuit generates a status signal according to the detection signal; wherein when the power supply of the computer is powered off, the capacitor is used to provide power to the control circuit and the Detector Measuring circuit. The central processor anti-theft device of claim 9, wherein when the central processor is electrically coupled to the second end of the detecting circuit, the second end of the detecting circuit has a first a voltage level, when the central processor is electrically separated from the second end of the detecting circuit, the second end of the detecting circuit has a second voltage level. The central processor anti-theft device according to claim 9, further comprising: a transmission circuit electrically coupled to the control circuit and the capacitor, receiving the status signal from the control circuit, and transmitting the status signal to An alarm device. The central processor anti-theft device of claim 11, wherein the transmission circuit is a wireless transmission circuit, and the alarm device wirelessly receives the status signal from the transmission circuit, wherein the central processor and the Detector When the second end of the measuring circuit is electrically separated, the alarm device generates an alarm signal according to the status signal.