TWI448058B - Boost converter - Google Patents

Description

Step-up voltage converter

The present invention relates to a boost voltage converter.

A DC to DC voltage converter can be used to regulate an input voltage to a stable output voltage to supply the current required by the load, wherein the input voltage can be greater than, equal to, or less than the output voltage. In recent years, due to the increasing popularity of portable products, boost converters using batteries as input voltages are urgent for the market because they can convert a lower input voltage to a higher output voltage. demand.

FIG. 1 is a schematic diagram showing the architecture of a typical boost voltage converter 10. The boost voltage converter 10 includes an input capacitor 12, two switches SW _A and SW _B , an inductor 14 , an output capacitor 16 , and a control circuit 18 . As shown in FIG. 1, a load 19 is coupled to the output of the boost voltage converter 10. The control circuit 18 provides two drive signals V _A and V _{B for} individually controlling the switches SW _A and SW _B such that the switches SW _A and SW _B can be alternately turned on and off.

When the boost voltage converter 10 operates in a normal mode, its output voltage Vout is greater than its input voltage Vin. In this state, when the switch SW _{A is} turned on and the switch SW _{B is} turned off, the input voltage Vin charges the inductor 14 to generate a charging current i _L . Conversely, when the switch SW _{B is} turned on and the switch SW _{A is} turned off, the charging current i _{L in} turn charges the output capacitor 16 such that the output voltage Vout maintains a voltage greater than the input voltage Vin level.

In a conventional architecture, the switch SW _{B is} typically implemented as a P-type transistor. The P-type transistor is implemented with its source and body connected to the output and its drain connected to a node UP. One disadvantage of the conventional architecture is that when the boost voltage converter 10 is operating in a shutdown mode, the P-type transistor exhibits a relatively large leakage current, which increases power loss. When the boost voltage converter 10 operates in the sleep mode, its output voltage Vout is less than its input voltage Vin. In this state, a parasitic PNP bipolar transistor of the P-type transistor will be turned on, so that the leakage current will flow from the input end of the boosting voltage converter 10 to the output via the P-type transistor. . If the output is short-circuited, the P-type transistor will burn out.

Therefore, in order to avoid the above problems, it is necessary to provide an improved step-up voltage converter to reduce leakage current when the boost voltage converter operates in the sleep mode.

It is an object of the present invention to provide a step-up voltage converter for receiving an input voltage from an input to regulate the generation of an output voltage to an output.

To achieve the above objects, an embodiment of the boost voltage converter of the present invention includes first and second main transistors, first and second switches, and a comparison circuit. The first primary transistor is configured to selectively connect a switching node to a common node based on a first signal. The second main transistor is configured to selectively connect the switching node to the output according to a second signal, wherein the second main transistor has a source connected to the output and has a drain connection To the switching node, the first and second signals are complementary signals.

The comparison circuit is configured to compare the input voltage to the output voltage to generate a third signal and a fourth signal, wherein the third and fourth signals are complementary signals. The first switch is configured to selectively connect a body of the second primary transistor to the switching node based on the third signal. The second switch is configured to selectively connect the body of the second primary transistor to the output in accordance with the fourth signal. When the input voltage is greater than the output voltage, the body of the second main transistor is connected to the switching node by the first switch, and when the input voltage is less than the output voltage, the second main transistor The body is connected to the output by the second switch.

Another embodiment of the boost voltage converter of the present invention includes a first and second primary transistor, first and second switches, and a comparison circuit. The first primary transistor is configured to selectively connect a switching node to a common node based on a first signal. The second main transistor is configured to selectively connect the switching node to the output according to a second signal, wherein the second main transistor has a source connected to the output and has a drain connection To the switching node, the first and second signals are complementary signals.

The comparison circuit is configured to compare the input voltage to the output voltage to generate a third signal and a fourth signal, wherein the third and fourth signals are complementary signals. The first switch is configured to selectively connect the input to a power supply terminal in accordance with the third signal. The second switch is configured to selectively connect the output to the power supply terminal in accordance with the fourth signal. The power supply end is configured to supply a voltage of an internal circuit of the boost voltage converter. When the input voltage is greater than the output voltage, the voltage of the power supply terminal is the input voltage, and when the input voltage is greater than the output voltage, The voltage at the power supply terminal is the output voltage.

The direction of the invention discussed herein is a boost voltage converter. In order to fully understand the present invention, detailed steps and structures are set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the relevant art. On the other hand, well-known structures or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. .

2 shows a block diagram of a boost voltage converter 20 incorporating an embodiment of the present invention. The boost voltage converter 20 is configured to receive an input voltage Vin from an input terminal N ₁ and adjust to generate an output voltage Vout to an output terminal N2. Referring to FIG. 2, the voltage boost converter 20 comprises an input capacitor 22, an NMOS transistor MS _1, the MS ₂ a PMOS transistor, an inductor 24, a control circuit 27 and a comparator circuit 34. In addition, a load 28 and an output capacitor 26 are coupled to the output terminal N _{2 of} the boost voltage converter 20 .

The inductor 24 is connected between the input terminal N ₁ and a switching node SW. The NMOS transistor MS _{1 is} connected between the switching node SW and a ground node, and the PMOS transistor MS _{2 is} connected between the switching node SW and the output terminal N2. The control circuit 27 configured to generate the NMOS transistor is turned on signals S ₁ MS ₁ and the PMOS transistor turn-on signal S _{2 2} MS. When the NMOS transistor MS ₁ is turned on, the switch node SW is at a low voltage level _(L similar to the product of the inductor current i and the internal resistance of the NMOS transistor of the MS _1). When the PMOS transistor MS _{2 is} turned on, the switching node SW is at a high voltage level (approximating the output voltage Vout plus the product of the internal resistance of the PMOS transistor MS ₂ and the inductor current i _L ).

The PMOS transistor MS ₂ has a source connected to the output terminal N ₂ and a drain connected to the switching node SW. A body of the PMOS transistor MS ₂ is selectively coupled to the switching node SW or the output terminal N ₂ according to the magnitude of the input voltage Vin and the output voltage Vout. The boost voltage converter 20 can operate in a normal mode or a rest mode. When the boost voltage converter 20 operates in the normal mode, its output voltage Vout is greater than its input voltage Vin. Conversely, when the boost voltage converter 20 operates in the sleep mode, its output voltage Vout is less than its input voltage Vin.

Referring to Figure 2, the comparator circuit 34 is configured to compare the input voltage Vin and the voltage value of the output voltage Vout, thereby generating a signal _{S. 3} S and a signal complementary to the signal S _{4. 3.} A first switch 30 according to the signal S ₃ is selectively connected to the PMOS transistor MS of the body ₂ to the switching node SW, and a second switch 32 based on the signal S ₄ is selectively connected to the PMOS transistor ₂ MS The body to the output terminal N ₂ .

3 shows a circuit diagram of a comparison circuit 34 incorporating an embodiment of the present invention. In the embodiment, the comparison circuit 34 is a current comparator comprising a comparison unit 342 and an output unit 344. The comparison unit 342 for receiving the input voltage Vin and the output voltage Vout to generate an output signal cmp, and the output unit 344 for receiving the output signal cmp to produce signals S ₃ and S _4. Referring to Figure 3, the comparison unit 342 comprises a differential input stage 346, wherein the differential input stage 346 includes a P-type transistor M ₁ and M _2, N-type transistors M ₅ and M ₆ and a bias resistor R _B . The source of the P-type transistor M ₁ is connected to the input terminal N ₁ to receive the input voltage Vin, and the source of the P-type transistor M2 is connected to the output terminal N ₂ to receive the output voltage Vout. The gate of the P-type transistor M _{1 and} the gate of the P-type transistor M ₂ are connected to each other, and the gate of the P-type transistor M ₂ is short-circuited to its drain. The gate of the N-type transistor M _{5 and} the gate of the N-type transistor M ₆ are connected to each other, and the gate of the N-type transistor M ₅ is short-circuited to its drain. The drain of the N-type transistor M ₅ is connected to the drain of the P-type transistor M ₁ , and the drain of the N-type transistor M ₆ is connected to the drain of the P-type transistor M ₂ . Further, a bias resistor R _B is connected in series between the source of the N-type transistor M ₆ and the ground node. The operating current of the comparison unit 342 can be reduced to less than 1 μA by a sufficiently large value of the bias resistor R _B . The output unit 344 includes two inverters X ₁ and X ₂ connected in series, wherein the inverter X ₁ is biased with the output voltage Vout, and the inverter X ₂ is biased with the input voltage Vin. .

2 to 4, the working principle of the boosting voltage converter 20 of the present invention will be described below. When the boost voltage converter 20 operates in the normal mode, the voltage Vout at its output terminal N ₂ is greater than the voltage Vin at its input terminal N ₁ . Under this condition, referring to FIG. 4, the voltage of the node A varies with the output voltage Vout. When the voltage of the node A rises to Vout - Vgs (the source-to-gate voltage difference of the transistor M ₂ ), since the output voltage Vout is greater than the input voltage Vin, the transistor M ₁ is forced to be turned off. At this time, the voltage of the node B is Vgs (the gate-to-source voltage difference of the transistor M ₅ ), so the voltage of the node C is the output voltage Vout. When the voltage of the node A rises to a predetermined voltage, the transistor M ₈ pulls the voltage of the node C to a voltage level close to the output voltage Vout. Since the source of the transistor M ₁₂ is connected to the input voltage Vin and the source of the transistor M ₁₀ is connected to the output voltage Vout, the transistor M ₁₂ will be turned off. When the transistor M _{12 is} turned off, since the voltage of the node C rises, the transistor M ₁₃ generates a pulling force, so that the voltage level of the output signal cmp falls to a ground voltage. Therefore, the voltage level of the signal S ₃ is the output voltage Vout, and the voltage level of the signal S ₄ is the ground voltage. Referring to FIG. 2, the first switch 30 is turned off and the second switch 32 is turned on. The body of the PMOS transistor MS ₂ is connected to the output terminal N ₂ by the first switch 32.

On the other hand, when the boost voltage converter 20 is operating in the sleep mode, the control circuit 27 will turn off the transistors MS ₁ and MS ₂ , and the output voltage Vout will be discharged via the resistor 28, so that the voltage of the output terminal N ₂ is Vout It is smaller than the voltage Vin of its input terminal N ₁ . Under this condition, with reference to FIG. 5, the voltage of the node A is Vin-Vgs (the transistor M the source to gate voltage difference of _2). Since the voltage of the node B is Vgs (the gate-to-source voltage difference of the transistor M ₅ ), the voltage of the node C is the ground voltage. At this time, the transistor M _{13 is} turned off, so that the voltage level of the output signal cmp is the input voltage Vin. Therefore, the voltage level of the signal S ₃ is the ground voltage, and the voltage level of the signal S ₄ is the input voltage Vin. Referring to FIG. 2, the first switch 30 is turned on and the second switch 32 is turned off. The body of the PMOS transistor MS ₂ is connected to the switching node SW by the second switch 32.

In an embodiment of the invention, the first and second switches 30 and 32 are implemented by a PMOS transistor. Figure 6 shows a circuit diagram of the first and second switches 30 and 32 in connection with an embodiment of the present invention. The first switch 30 is replaced by a P-type transistor MS ₃ , wherein the source and the body of the P-type transistor MS ₃ are commonly connected to the body of the PMOS transistor MS ₂ , and the drain is connected to the switching node SW And the gate is used to receive the signal S ₃ . The second switch 32 is replaced by a P-type transistor MS ₄ , wherein the source and the body of the P-type transistor MS ₄ are commonly connected to the body of the PMOS transistor MS ₂ , and the drain is connected to the output terminal N ₂ , and the gate is used to receive the signal S ₄ .

In addition, as the boost voltage converter 20 operates in different modes, the supply voltage of the internal circuit of the boost voltage converter 20 also needs to be adjusted to improve the overall voltage of the boost voltage converter 20. Work efficiency. In an embodiment of the invention, the boost voltage converter 20 can include a power switching unit 70 that automatically outputs a supply voltage V _H to the boost mode according to an operation mode of the boost voltage converter 20 . The internal circuit of the voltage converter 20.

FIG. 7 shows a circuit diagram of a power switching unit 70 incorporating an embodiment of the present invention. Referring to FIG. 7, the power switching unit 70 mode includes a third switch 35 and a fourth switch 36. The third switch 35 is configured to selectively connect the input voltage Vin to the supply voltage V _H according to the third signal S ₃ , and the fourth switch 36 is configured to be selectively selected according to the fourth signal S ₄ The output voltage Vout is grounded to the supply voltage V _H .

The working principle of the power switching unit 70 is explained as follows. When the boost voltage converter 20 operates in the normal mode, the voltage Vout at its output terminal N ₂ is greater than the voltage Vin at its input terminal N ₁ . Referring to FIG 4, when the voltage signal S ₃ bits of the output voltage Vout of registration, and the voltage level of the signal S ₄ for the quasi-ground voltage. Therefore, the third switch 35 in FIG. 7 is turned off and the fourth switch 36 is turned on, so the output voltage Vout will be supplied to the supply voltage V _H . On the other hand, when the step-up voltage converter 20 operates in the sleep mode, the voltage Vout at its output terminal N ₂ is smaller than the voltage Vin at its input terminal N ₁ . Referring to FIG 5, when the voltage signal S ₃ bits for the quasi-ground voltage, the voltage level of signal S ₄ for the quasi-output voltage Vout. Therefore, the third switch 35 in FIG. 7 is turned on and the fourth switch 36 is turned off, so the input voltage Vin will be supplied to the supply voltage V _H .

In an embodiment of the invention, the third and fourth switches 35 and 36 are implemented by a PMOS transistor. Referring to FIG. 7, the third switch 35 is replaced by a P-type transistor MS ₅ , wherein the source and the body of the P-type transistor MS ₅ are commonly connected to the supply voltage V _H , and the drain is connected to the switching node. SW, and the gate is used to receive the signal S ₃ . The fourth switch 36 is replaced by a P-type transistor MS ₆ , wherein the source and the body of the P-type transistor MS ₆ are commonly connected to the supply voltage V _H , the drain is connected to the output terminal N ₂ , and the gate is connected The pole is used to receive the signal S ₄ . Therefore, the P-type transistor MS ₅ and the P-type transistor MS ₆ are selectively turned on according to the voltage levels of the signals S ₃ and S ₄ .

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

10‧‧‧Boost voltage converter

12‧‧‧ Capacitance

14‧‧‧Inductance

16‧‧‧ Capacitance

18‧‧‧Control circuit

19‧‧‧ load

20‧‧‧Boost voltage converter

22‧‧‧ Capacitance

24‧‧‧Inductance

26‧‧‧ Capacitance

27‧‧‧Control circuit

28‧‧‧ load

30‧‧‧ switch

32‧‧‧ switch

34‧‧‧Comparative circuit

35‧‧‧ switch

36‧‧‧Switch

70‧‧‧Power switching unit

MS ₁ ~ MS ₆ ‧‧‧O crystal

M ₁ ~M ₁₃ ‧‧‧O crystal

X ₁ ~X ₂ ‧‧‧Inverter

S ₁ ~S ₄ ‧‧‧ signal

N ₁ ‧‧‧ input

N ₂ ‧‧‧ output

SW‧‧‧Switching node

Vin‧‧‧Input voltage

Vout‧‧‧ input voltage

i _L ‧‧‧Charging current

1 is a schematic structural diagram of a typical boost voltage converter;

2 is a block diagram showing the structure of a boost voltage converter in accordance with an embodiment of the present invention;

3 is a circuit diagram showing a comparison circuit in accordance with an embodiment of the present invention;

4 shows an operational state of a comparison circuit incorporating an embodiment of the present invention;

Figure 5 shows the operational state of a comparison circuit incorporating an embodiment of the present invention;

6 shows a circuit diagram of the first and second switches in connection with an embodiment of the present invention;

FIG. 7 shows a circuit diagram of a power switching unit incorporating an embodiment of the present invention.

20‧‧‧Boost voltage converter

22‧‧‧ Capacitance

24‧‧‧Inductance

26‧‧‧ Capacitance

27‧‧‧Control circuit

28‧‧‧ load

30‧‧‧ switch

32‧‧‧ switch

34‧‧‧Comparative circuit

MS ₁ ~ MS ₂ ‧‧‧O crystal

M ₁ ~M ₁₃ ‧‧‧O crystal

S ₁ ~S ₄ ‧‧‧ signal

N ₁ ‧‧‧ input

N ₂ ‧‧‧ output

SW‧‧‧Switching node

Vin‧‧‧Input voltage

Vout‧‧‧ input voltage

i _L ‧‧‧Charging current

Claims (10)

A step-up voltage converter for receiving a DC input voltage from an input terminal to adjust a current output voltage to an output terminal, the boost voltage converter comprising: a first main transistor a state of selectively connecting a switching node to a common node according to a first signal; a second primary transistor configured to selectively connect the switching node to the output according to a second signal, wherein the a second main transistor having a source coupled to the output and having a drain connected to the switching node, the first and second signals being complementary signals; a comparison circuit configured to compare the DC Inputting a voltage and a DC output voltage to generate a third signal and a fourth signal, wherein the third and fourth signals are complementary signals; a first switch configured to select according to the third signal Connecting a body of the second main transistor to the switching node; and a second switch configured to selectively connect the body of the second main transistor to the fourth signal according to the fourth signal An output; wherein when the DC input voltage is greater than the DC output voltage, the body of the second main transistor is connected to the switching node by the first switch, and when the DC input voltage is less than the DC output voltage, The body of the second primary transistor is coupled to the output by the second switch. The step-up voltage converter of claim 1, wherein the first switch is a P-type transistor, the source and the body are commonly connected to the body of the second main transistor, and the drain is connected to the switching node And the gate is for receiving the third signal, the second switch is a P-type transistor, the source and the The body is commonly connected to the body of the second main transistor, the drain is connected to the output, and the gate is configured to receive the fourth signal. The step-up voltage converter of claim 1, wherein the step-up voltage converter further comprises: a third switch configured to selectively connect the input terminal to a power supply terminal according to the third signal; And a fourth switch configured to selectively connect the output terminal to the power supply terminal according to the fourth signal; wherein the power supply terminal is configured to supply a voltage of an internal circuit of the boost voltage converter, and When the DC input voltage is greater than the DC output voltage, the voltage of the power supply terminal is the DC input voltage, and when the DC input voltage is greater than the DC output voltage, the voltage of the power supply terminal is the DC output voltage. A boost voltage converter according to claim 1, wherein the comparison circuit comprises: a first P-type transistor having a source connected to the input terminal; and a second P-type transistor having a source connected to the output a terminal, wherein the drain and the gate are connected in common to the gate of the first P-type transistor; a first N-type transistor, the source of which is connected to the common node, and the gate and the drain thereof are connected in common to a drain of the first P-type transistor; a second N-type transistor having a gate connected to the gate of the first N-type transistor and a drain connected to the gate of the second P-type transistor And a bias resistor connected in series between the source of the second N-type transistor and the common node. According to the step-up voltage converter of claim 4, wherein the comparison circuit is further included The invention comprises: a third P-type transistor, the source of which is connected to a high supply power source, and the drain and the gate thereof are connected in common to the gate of the second P-type transistor; and a fourth P-type transistor, a source connected to the output terminal, a gate connected to the gate of the second P-type transistor; a fifth P-type transistor having a source connected to the output terminal and a drain shorted to the gate thereof a sixth P-type transistor having a source connected to the input terminal and a gate connected to the gate of the fifth P-type transistor; a seventh P-type transistor having a source connected to the output a gate connected to the gate of the second P-type transistor; an eighth P-type transistor having a source connected to the drain of the seventh P-type transistor, the gate being connected to the gate a drain of the six P-type transistor, the drain of which is connected to the gate of the first N-type transistor; a third N-type transistor whose source is connected to the common node, the gate of which is connected to the first a gate of an N-type transistor, the drain of which is connected to the drain of the fourth P-type transistor; a fourth N-type transistor whose source is connected to the common node and whose gate is connected to a gate of the third N-type transistor, the drain of which is connected to the drain of the fifth P-type transistor; and a fifth N-type transistor whose source is connected to the common node and whose gate is connected to The drain of the third N-type transistor is connected to the drain of the sixth P-type transistor. A step-up voltage converter for receiving a DC input voltage from an input terminal to regulate a DC output voltage to an output terminal, the boosting type The voltage converter comprises: a first main transistor configured to selectively connect a switching node to a common node according to a first signal; a second main transistor configured to be according to a second a signal selectively connecting the switching node to the output terminal, wherein the second main transistor has a source connected to the output end and having a drain connected to the switching node, the first and second signals being complementary a comparison circuit configured to compare the DC input voltage and the DC output voltage to generate a third signal and a fourth signal, wherein the third and fourth signals are complementary signals; a switch configured to selectively connect the input to a power supply terminal in accordance with the third signal; and a second switch configured to selectively connect the output to the fourth signal based on the fourth signal a power supply end; wherein the power supply end is configured to supply a voltage of an internal circuit of the boost voltage converter, and when the DC input voltage is greater than the DC output voltage, the voltage of the power supply terminal is the DC input voltage, When the DC input voltage is greater than the DC output voltage, the voltage of the power supply for the DC output voltage terminal. The step-up voltage converter of claim 6, wherein the first switch is a P-type transistor, the source and the body are commonly connected to the power supply terminal, the drain is connected to the input terminal, and the gate thereof is For receiving the third signal, the second switch is a P-type transistor, the source and the body are commonly connected to the power supply end, the drain is connected to the output end, and the gate is used to receive the third Four signals. The boost voltage converter of claim 6, wherein the boost voltage converter further comprises: a third switch configured to selectively connect one of the second main transistors according to the third signal a body to the switching node; and a fourth switch configured to selectively connect the body of the second main transistor to the output according to the fourth signal; wherein when the DC input voltage is greater than the DC output When the voltage is applied, the body of the second main transistor is connected to the switching node by the first switch, and when the DC input voltage is less than the DC output voltage, the body of the second main transistor is A second switch is connected to the output. A boost voltage converter according to claim 6, wherein the comparison circuit comprises: a first P-type transistor having a source connected to the input terminal; and a second P-type transistor having a source connected to the output a terminal, wherein the drain and the gate are connected in common to the gate of the first P-type transistor; a first N-type transistor, the source of which is connected to the common node, and the gate and the drain thereof are connected in common to a drain of the first P-type transistor; a second N-type transistor having a gate connected to the gate of the first N-type transistor and a drain connected to the gate of the second P-type transistor And a bias resistor connected in series between the source of the second N-type transistor and the common node. The step-up voltage converter of claim 9, wherein the comparison circuit further comprises: a third P-type transistor having a source connected to a high supply power source and a drain and a gate connected to the second The gate of the P-type transistor; a fourth P-type transistor having a source connected to the output terminal and a gate connected to the gate of the second P-type transistor; a fifth P-type transistor having a source connected to the output terminal And the drain is short-circuited to its gate; a sixth P-type transistor has a source connected to the input terminal and a gate connected to the gate of the fifth P-type transistor; a seventh P-type transistor a crystal whose source is connected to the output terminal and whose gate is connected to the gate of the second P-type transistor; an eighth P-type transistor whose source is connected to the P of the seventh P-type transistor a gate connected to the drain of the sixth P-type transistor and a drain connected to the gate of the first N-type transistor; a third N-type transistor having a source connected to the common a node whose gate is connected to the gate of the first N-type transistor and whose drain is connected to the drain of the fourth P-type transistor; a fourth N-type transistor whose source is connected to the common a node having a gate connected to the gate of the third N-type transistor and a drain connected to the drain of the fifth P-type transistor; and a fifth N-type transistor having a source connected thereto Node with which the drain is connected to the gate of the third N-type transistor of the electrode, and its drain connected to the drain of the sixth P-type transistor poles.