TWI447910B - A semiconductor structure with a stress region - Google Patents

Description

Semiconductor structure with stress region

The present invention relates to a metal-oxide-semiconductor (MOS) structure, and more particularly to a semiconductor structure having a stress region.

With the advancement of technology, the flash memory process technology has also entered the nano-era, in order to accelerate the operating rate of components, increase the accumulation of components, and reduce the operating voltage of components, etc., the channel of the component gate The shrinkage of the length and thickness of the oxide layer is an inevitable trend. The gate width of the device has been reduced from the previous micron (10 ^-6 meters) to the current nano (10 ^-9 meters), but with the shrinkage of components, it also brings many problems, such as: pressure leakage The stree-induced leakage current (SILC) and the shortening of the gate line width will make the Short Channel Effect more and more serious. To avoid the influence of the short channel effect on the component, the thickness of the oxide layer must be thinner. However, when the thickness of the oxide layer is 8 nm or even thinner, the physical limit of the material becomes an obstacle to the component process. The induced leakage current (SILC) is a gate leakage current that increases after a constant voltage or constant current is applied. After the thickness of the oxide layer is reduced, the induced leakage current (SILC) becomes an important factor. The problem is that the increase in leakage current will cause the electrons stored in the floating gate to be lost, greatly reducing the preservability of the data and increasing the power consumption of the MOS device. In addition, the memory disturb (Gate disturb, Drain disturb) also greatly limits the thickness of the oxide layer during the component shrinking process. Therefore, after the component size reaches the physical limit, in addition to the method of reducing the size of the component, how to improve the disadvantage caused by the size reduction becomes quite urgent.

In order to improve the performance of the component current, there are many ways to increase the mobility of the carrier. Among various methods for increasing the mobility of the carrier, a known strained Si channel method is to form a channel with stress. This stress can enhance the mobility of electrons or holes, and the characteristics of the MOS device can be improved by the channel with stress. And the application of stress can also benefit from the memory bit interference (Gate disturb, Drain disturb), that is, the lower bucker voltage can bring higher bungee current, so only a lower 汲 is needed. The pole voltage can reach the required bungee current, which in turn reduces the degree of interference.

One way to increase stress can be achieved by forming a stressor layer on the MOS device. A contact Etch Stop Layer (CESL) can be used as the stress layer. When the stress layer is deposited, coplanar stress is generated and band separation is achieved in order to align the crystal lattices of each other due to the difference in lattice spacing distance from the underlying material. Referring to the seventh figure, it is the relationship between the stress direction and the energy band in the MOS semiconductor, that is, the energy band (fourfold degenerate, Δ4) energy band corresponding to the k _x and k _y directions in the k space, and the k _z direction energy valley (twofold degenerate, △ 2) The energy band decreases, so most of the electrons are distributed in the lower energy band Δ2 energy valley (low effective mass), in addition to strain-induced band splitting, on the one hand, the energy is reduced. Inter-valley scattering rate (on-the-valley scattering rate), on the other hand, reduces the effective state density of the conductive strip, thereby reducing the intra-valley scattering rate (infratron scattering rate) Therefore, lower effective mass and scattering rate improve electron mobility. In the same manner as above, the light electric hole with degenerate energy on the valence band is separated from the heavy electric hole, and the scattering rate between the energy band and the energy band is reduced, and the mobility of the hole is also improved. However, if the stress layer is too thick, it will affect the difficulty of subsequent caulking. If it is too thin, the resulting stress effect will be limited.

Therefore, how to improve the stress layer and its associated configuration becomes important to enhance the characteristics of the component without increasing the complexity of the design.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor structure having a stress region to improve carrier mobility.

To achieve the above object, the present invention is a semiconductor structure having a stress region, comprising: a substrate having a first component region and a second component region; wherein the first component region and the second component region a gate is included, and a drain is included between the first component region and the second component region; wherein the upper ends of the gates are respectively provided with an automatic alignment metal salicide layer, and at the top of the gate An unstressed region is located in the first component region and the second component region; wherein the stress region includes a first portion and a second portion in each of the first and second component regions; The first and second portions generate different stresses, and the first portion has a pair of L-shaped barriers opposite to each other; a barrier plug that separates the first component region from the Second component area.

In order to achieve the above object, in an embodiment of the present invention, the first part is A pair of L-shaped barriers opposite each other; the second portion is a contact hole etch stop layer (CESL). The stress of the second portion is greater than the stress of the third portion, and the stress is a uniaxial tensile stress.

In order to achieve the above object, another embodiment of the present invention is that the substrate is a substrate and an N channel is formed along the <110> direction.

In order to achieve the above object, another embodiment of the present invention is that the substrate is a substrate and a channel is formed along the <100> direction.

Thereby, a semiconductor structure having a stress region of the present invention can generate appropriate stress and enhance carrier mobility.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying drawings. In the various figures and embodiments, the same elements will be given the same symbols.

Referring to the first drawing, there is shown a cross-sectional view of a wafer according to an embodiment of the present invention. The figure shows a first device region 112 and a second device region 114 formed on a semiconductor substrate 100. The first device region and the second device region are N-channel or P-channel or a mixture of the two, in this embodiment N channel. A source 104, a gate 106, a tunneling oxide layer 106a, a floating gate 106b, a dielectric layer 106c, a control gate 106d, and a control gate are formed on the semiconductor substrate 100. A first oxide layer 108 and a second oxide layer 110. The base material may be tantalum, SiGe, silicon on insulator (SOI), silicon on insulator (silicon) Germanium on insulator (SGOI), germanium on insulator (GOI); in this embodiment, the substrate 100 is a germanium substrate, and is in the (100) direction and the channel is made in the <110> direction. . The second oxide layer 110 may be SiN, oxynitride, oxide, or the like, and is SiN in this embodiment.

Referring to the second figure, a conventional deposition technique such as chemical vapor deposition (CVD) using a source gas containing NH ₃ and SiH ₄ , rapid thermal chemical vapor deposition (RTCVD), Atomic layer deposition (ALD), where an oxide layer 210 is deposited. The thickness of the oxide layer 210 is between 200 To 1500 In this embodiment, it is 750 . The oxide layers 110 and 210 located adjacent to 106b and 106d have a deposition thickness at least greater than one-half of the width d of the region 107 for enclosing the region 107. The oxide layer 210 is then etched into a plurality of Oxide spacers 310a-d (see FIG. 3), and the oxide layers 110 and 210 on 106d are completely etched away (see FIG. 3).

Referring to the fourth figure, the second oxide layer 110 forms a first, second, third, and fourth L-shaped spacers (L-shape) 402, 404, 406, 408 (wherein the first and third L-shaped gaps) The walls 402 and 406 are inverted L-shaped), the L-shaped spacers are in a pair and opposite to each other, that is, a pair of 402 and 404, a pair of 406 and 408, and at this time, the second and third L-shaped spacers 404 Connected to 406 to form a U shape. The L-shaped spacers produce the desired uniaxial tensile stress (first part). However, the stress can be adjusted by appropriate material selection and formation methods. Adjustable process parameters in the formed method The number has temperature, deposition speed, power, and the like. Those skilled in the art will be able to discover the relationship between these process parameters and a sedimentary layer stress.

Next, the oxide layer 210 located in the region 107 is completely etched away by dry or wet etching, and then a cobalt (Co), titanium (Ti), nickel (nickel, Ni) or molybdenum is formed on the surface. a metal telluride layer formed by molybdenum, Mo), and performing a rapid thermal annealing process to form an automatic pair of the gates of the first component region and the second component region with the surface of the drain The metalloid telluride layers 410a and 410b (salicide layer) are used to reduce the driving force of the parasitic resistance lifting element.

Referring to the fifth figure, following the above steps, a contact etch stop layer 502 (CESL) is deposited on the semiconductor substrate 100, which may be SiN, oxynitride, oxide, etc. In the present embodiment, it is SiN. The contact hole etch stop layer 502 is deposited to a thickness of 100 to 1500 . In the present embodiment, the contact hole etch stop layer 502 utilizes a deposition process to produce the desired uniaxial tensile stress (second portion). Wherein, the increase of the stress is related to the hydrogen atom content of the stop layer 502, and the lower the hydrogen atom content, the greater the increase of the tensile stress. However, the uniaxial tensile stress generated by the L-type spacers in this embodiment is smaller than the uniaxial tensile stress generated by the contact hole etch stop layer 502. Next, an inter-layer dielectric (ILD), such as cerium oxide SiO ₂ , is deposited over the contact hole etch stop layer 502.

Referring to the sixth figure, the above steps are followed to form a drain 102 by ion implantation, and a contact hole 602 is non-uniform from the interlayer dielectric layer 504 by a conventional photoresist mask process. Sexually etched into the contact etch Stop layer 502. Ion implantation of the drain and rapid thermal annealing for doping in the active element are then performed. A barrier plug 604 is deposited by chemical vapor deposition and directly contacts the drain 102. The second and third L-shaped spacers 404 and 406 are cut into an L shape from the U-shape originally connected (the L-shaped spacer 406 is inverted L-shaped). The contact hole etch stop layer 502 is also cut into 502a and 502b. The oxide layer spacers of the first device region 112 and the second device region 114 are asymmetric (ie, 310a and 310b; 310c and 310d).

In the foregoing embodiment, the stress region includes the L-type spacers 402, 404, 406, 408 (first portion); and the contact hole etch stop layers 502a and 502b (second portion); wherein the L-types The spacer and the contact hole etch stop layer undergo rapid thermal annealing treatment in different steps to generate an appropriate uniaxial tensile stress, thereby increasing the effective mass of the electron and thereby reducing the tunnel leakage current, and therefore, at the same pressure The leakage current (SILC) can reduce the thickness of the tunneling oxide layer and reduce the possibility of short channel effect (SCE).

In one embodiment, the L-type spacers generate less uniaxial tensile stress than the contact hole etch stop layers 502a and 502b, and since the substrate 100 is in the (100) direction and along the channel The <110> direction is produced, and the uniaxial tensile stress generated by the stress regions increases the electron mobility of the memory device. Therefore, a higher electron mobility can increase the read current, and a lower read voltage can be used to achieve the desired read current, thereby improving data retention.

In another embodiment, the substrate 100 is in the (100) direction and the channel Made along the <100> direction. Compared with the <110> direction, electrons have a higher piezoresistance coefficient on the <100> channel, so the uniaxial tensile stress generated by the stress region can further increase the mobility of electrons in the memory device. . Further, since the lattice direction is <100>, the hole mobility in the PMOS is not lowered.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100‧‧‧Base

102‧‧‧汲polar

104‧‧‧ source

106‧‧‧ gate

106a‧‧‧ Tunneling Oxidation Layer

106b‧‧‧Floating gate

106c‧‧‧ dielectric layer

106d‧‧‧Control gate

107‧‧‧Area

108‧‧‧First oxide layer

110‧‧‧Second oxide layer

112‧‧‧First component area

114‧‧‧Second component area

210‧‧‧Oxide layer

310a~310d‧‧‧Oxide spacer

402, 404, 406, 408‧‧‧ L-shaped spacer

410a‧‧‧First metal telluride

410b‧‧‧Second metal telluride

502, 502a, 502b‧‧‧ contact hole etch stop layer

504‧‧‧Interlayer dielectric layer

602‧‧‧Contact hole

604‧‧‧ Barrier plug

The first to sixth figures show wafer cross-sectional views of embodiments of the present invention at different process steps.

The seventh figure is a diagram of the relationship between the stress direction and the energy band in the MOS semiconductor.

100‧‧‧Base

102‧‧‧汲polar

104‧‧‧ source

106a‧‧‧ Tunneling Oxidation Layer

106b‧‧‧Floating gate

112‧‧‧First component area

114‧‧‧Second component area

310a‧‧‧Oxide spacer

310d‧‧‧Oxide spacer

402, 404, 406, 408‧‧‧ L-shaped spacer

502a, 502b‧‧‧ contact hole etch stop layer

504‧‧‧Interlayer dielectric layer

602‧‧‧Contact hole

604‧‧‧ Barrier plug

Claims (8)

A semiconductor structure having a stress region, comprising: a substrate having a first device region and a second device region; wherein the first device region and the second device region each comprise a gate, the first component a drain is included between the region and the second component region; wherein each of the gates is provided with an automatic alignment metal salicide layer, and the gate is not provided, and each gate is Located on the substrate and having sidewalls, each sidewall of the gate is in contact with a first oxide layer; a stress region is located in the first component region and the second component region; wherein the stress region is in the first And the second component region includes a first portion and a second portion; wherein the first and second portions generate different stresses, and the first portion has a pair of L-shaped spacers opposite each other ( L-shape), the second portion is a contact hole etch stop layer (CESL), the first portion contacting the first oxide layer and not covering the upper end of the gate in a direction outside the sidewall of the gate The second portion is in contact with the first portion; a barrier plug The first partition member-based region and the second element region, wherein the contact hole etch stop layer from the upper end to the outer wall of the cell walls of the gate line contact hole formed in the accommodating position of the barrier plug. The semiconductor structure of claim 1, wherein the substrate is a substrate and a channel is formed along the <110> direction. The semiconductor structure of claim 2, wherein the channel is an N channel. The metal oxide semiconductor structure according to claim 1, wherein the substrate is a germanium substrate, and a channel is formed along the <100> direction. The semiconductor structure of claim 1, wherein the L-shaped spacer may be SiN, oxynitride, or oxide. The semiconductor structure of claim 1, wherein the contact hole etch stop layer is SiN, oxynitride, or oxide. The semiconductor structure of claim 1, wherein the stress of the first portion is less than the stress of the second portion. The semiconductor structure of claim 7, wherein the stress is a uniaxial tensile stress.