TWI446449B - Semiconductor device and manufacturing method thereof - Google Patents

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a structure of a thin film transistor that can be applied to a liquid crystal display panel and a method of fabricating the same.

Since polycrystalline germanium thin film transistors have advantages of low power consumption and large electron mobility compared with amorphous germanium thin film transistors, low temperature polycrystalline germanium thin film transistors have been widely used in large-sized liquid crystal displays.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional low temperature polycrystalline germanium film transistor. As shown in FIG. 1 , a buffer layer 102 is formed on the substrate 100 , and a polysilicon layer 110 is formed on the buffer layer 102 , and the polysilicon layer 110 is formed by a doping process. The source region 112, the drain region 114, and the channel region 116, wherein the channel region 116 is located between the source region 112 and the drain region 114.

Referring to FIG. 1 again, the gate insulating layer 120 covers the polysilicon layer 110 and the buffer layer 102, and the gate 130 is disposed on the gate insulating layer 120 above the channel region 116. The dielectric layer 140 covers the gate 130 and the gate insulating layer 120, and the contact openings 112a, 114a are formed in the dielectric layer 140 and the gate insulating layer 120. In addition, the source metal layer 152 and the gate metal layer 154 are disposed on the dielectric layer 140, and the source metal layer 152 and the gate metal layer 154 are connected to the source region 112 by the contact opening 112a, 114a, respectively. And the bungee region 114 is electrically connected.

It is worth mentioning that in order to reduce the lateral electric field during the operation of the transistor to increase the reliability of the operation of the device and reduce the leakage current, a light doping is usually formed between the source region 112, the drain region 114 and the channel region 116. Lightly doped drain (LDD) zone 118. Conventionally, in the fabrication of a polycrystalline germanium thin film transistor having a lightly doped drain region 118, it is generally necessary to perform two or more doping processes by using two or more photomask processes to form sources having different doping concentrations. Zone 112/drain region 114 and lightly doped bungee region 118. However, the above-mentioned method of fabricating the lightly doped drain region is not only complicated in process, but also easy to cause difficulty in alignment of the mask pattern, which makes the electrical performance of the fabricated thin film transistor inconsistent, thereby affecting the reliability of the product. degree.

The present invention relates to a method of fabricating a semiconductor device which can reduce the number of masks in a process to reduce cost and improve process yield.

The invention further relates to a semiconductor component having high reliability which provides better electrical performance.

In order to specifically describe the contents of the present invention, a method of fabricating a semiconductor device is proposed herein. First, a substrate is provided, and a first semiconductor pattern and a second semiconductor pattern are formed on the substrate. Then, a gate insulating layer and a gate metal layer are sequentially formed on the substrate, and cover the first semiconductor pattern and the second semiconductor pattern. Then, a first mask pattern and a second mask pattern are formed on the gate metal layer, wherein the first mask pattern is located above the first semiconductor pattern and correspondingly exposes a first source of the first semiconductor pattern/ a drain region, and the second mask pattern is over the second semiconductor pattern and correspondingly exposes a second source/drain region of the second semiconductor pattern. Then, the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask to form a first gate pattern and a second gate pattern, respectively. Thereafter, the first source/drain region and the second source/drain region are first performed with the first mask pattern, the first gate pattern, the second mask pattern, and the second gate pattern as masks The type ion doping has a first source/drain region and a second source/drain region having a first conductivity type. Then, an etching process is performed on the first mask pattern and the second mask pattern to remove a portion of the outer surface of the first mask pattern and the second mask pattern, thereby exposing a portion of the first gate pattern and the second Gate pattern. Then, the first gate pattern and the second gate pattern are etched by the first mask pattern and the second mask pattern after removing the outer wall to form a first gate and a second gate. And correspondingly exposing a first lightly doped region inside the first source/drain region of the first semiconductor pattern and a second lightly doped region inside the second source/drain region of the second semiconductor pattern. Then, the first light-doped region and the second light-doped region are lightly doped with the first type of ions by the first gate and the second gate electrode, so that the first lightly doped region and the second lightly doped region The zone has a first conductivity type. Then, the first mask pattern and the second mask pattern are removed, and then a patterned mask layer is formed on the substrate, and the patterned mask layer correspondingly exposes a portion of the second semiconductor pattern. Then, the second source/drain region and the second lightly doped region are subjected to counter-doping of the second type ions via the patterned mask layer to make the second source/drain region The ion form of the second lightly doped region is changed from the first conductivity type to the second conductivity type. After that, the patterned mask layer is removed.

In an embodiment of the present invention, the method for fabricating the semiconductor device further includes forming a dielectric layer on the gate insulating layer to cover the first gate and the second gate after removing the patterned mask layer. . Then, a plurality of first contact windows are formed in the dielectric layer and the gate insulating layer, the first contact windows exposing the first source/drain regions of the first semiconductor pattern and the second source of the second semiconductor pattern/ Bungee area. Then, a first source/drain contact metal and a second source/drain contact metal are respectively formed in the first contact window, wherein the first source/drain contacts the metal and the second source/drain The contact metal is electrically connected to the corresponding first source/drain region and the second source/drain region, respectively.

After the above steps, the present invention further forms a flat layer on the dielectric layer to cover the first source/drain contact metal and the second source/drain contact metal. Next, a second contact window is formed in the planar layer, the second contact window exposing the first source/drain contact metal. Then, an electrode pattern is formed on the planar layer, wherein the electrode pattern is connected to the first source/drain contact metal via the second contact window.

After the above steps, the third mask pattern is simultaneously formed on the gate metal layer when the first mask pattern and the second mask pattern are formed. Thereafter, when the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask, the gate metal layer is patterned by using the third mask pattern as a mask to form a lower layer. pad. In addition, the present invention can further cover the underlying pads when forming the dielectric layer. Then, when the first contact window is formed, a third contact window is further formed in the dielectric layer to expose the underlying pad. Then, when the first source/drain contact metal and the second source/drain contact metal are formed, an upper pad is formed in the third contact window, wherein the upper pad is connected to the lower pad. Furthermore, the present invention can cover the upper layer pad even when the flat layer is formed. Thereafter, when the second contact window is formed, a fourth contact window is further formed in the flat layer, wherein the fourth contact window exposes the upper layer pad. Moreover, when the electrode pattern is formed on the flat layer, a pad pattern is further formed in the fourth contact window, and the pad pattern is connected to the upper layer pad.

The present invention further proposes a method of fabricating another semiconductor device. First, a substrate is provided, and a first semiconductor pattern and a second semiconductor pattern are formed on the substrate. Next, a second source/drain region of the second semiconductor pattern is doped with a second type of ion to have a second conductivity type. Then, a gate insulating layer is formed on the substrate to cover the first semiconductor pattern and the second semiconductor pattern. Then, a gate metal layer is formed on the gate insulating layer, and a first mask pattern and a second mask pattern are formed on the gate metal layer, wherein the first mask pattern is located above the first semiconductor pattern and corresponds to A first source/drain region of the first semiconductor pattern is exposed, and the second mask pattern is over the second semiconductor pattern and correspondingly exposes a second source/drain region of a portion of the second semiconductor pattern. Then, the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask to form a first gate pattern and a second gate pattern, respectively. Thereafter, the first source/drain region is doped with the first type by using the first mask pattern and the first gate pattern as a mask, so that the first source/drain region has the first conductivity type. And the second source/drain region maintains the second conductivity type. Then, an etching process is performed on the first mask pattern and the second mask pattern to remove the outer wall of the partial thickness of the first mask pattern and the second mask pattern, thereby exposing a portion of the first gate pattern and The second gate pattern. Then, the first gate pattern and the second gate pattern are etched by using the first mask pattern and the second mask pattern as a mask to form a first gate and a second gate, wherein the first gate Correspondingly exposing a lightly doped region inside the first source/drain region of the first semiconductor pattern, and the second gate covering a channel region of the second semiconductor pattern and a portion of the second source/drain region. Then, the light-doped region is lightly doped with the first type ion by the first gate electrode, so that the lightly doped region has the first conductivity type, and the second source/drain region still maintains the second conductivity. Type. Thereafter, the first mask pattern and the second mask pattern are removed.

In an embodiment of the invention, the method for fabricating the semiconductor device further includes forming a dielectric layer on the gate insulating layer to cover the first gate and the second gate. Next, a plurality of first contact windows are formed in the dielectric layer and the gate insulating layer, the first contact windows exposing the first source/drain regions and the second source/drain regions. Then, a first source/drain contact metal and a second source/drain contact metal are respectively formed in the first contact window, wherein the first source/drain contacts the metal and the second source/drain The contact metal is respectively connected to the corresponding first source/drain region and the second source/drain region.

After the above steps, the present invention can further form a flat layer on the dielectric layer to cover the source/drain contact metal. Next, a second contact window is formed in the planar layer, the second contact window exposing the first source/drain contact metal. Then, an electrode pattern is formed on the planar layer, wherein the electrode pattern is connected to the first source/drain contact metal via the second contact window.

In an embodiment of the present invention, the method for fabricating the semiconductor device described above further forms a third mask pattern on the gate metal layer while forming the first mask pattern and the second mask pattern. Moreover, when the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask, the gate metal layer is patterned by using the third mask pattern as a mask to form a lower layer. pad.

In addition, the present invention can further cover the underlying pads when forming the dielectric layer. Then, when the first contact window is formed, a third contact window is further formed in the dielectric layer to expose the underlying pad. Thereafter, an upper layer pad is formed in the third contact window while the first source/drain contact metal and the second source/drain contact metal are formed, so that the upper layer pad is connected to the lower layer pad.

Further, in the present invention, when the flat layer is formed, it is possible to cover the upper layer pad. Moreover, when the second contact window is formed, a fourth contact window is further formed in the flat layer, and the fourth contact window exposes the upper layer pad. Then, when the electrode pattern is formed on the flat layer, a pad pattern is further formed in the fourth contact window, and the pad pattern is connected to the upper layer pad.

In an embodiment of the invention, the step of performing first type ion doping on the first source/drain region further comprises performing first type ion doping on a portion of the second source/drain region, and The second source/drain region of this portion must still maintain the second conductivity type. In addition, when the first type ion is lightly doped in the lightly doped region, the second source/drain region of the portion may be lightly doped with the first type ion at the same time, and the second source of the portion is/ The bungee region must still maintain the second conductivity type.

In an embodiment of the invention, the method for fabricating the semiconductor device further includes simultaneously forming a third semiconductor pattern on the substrate when the first semiconductor pattern and the second semiconductor pattern are formed. Next, when performing the second type ion doping on the second source/drain region, the third semiconductor pattern is simultaneously doped with the second type ion so as to have the second conductivity type.

In addition, when the first mask pattern and the second mask pattern are formed, a fourth mask pattern may be simultaneously formed on the gate metal layer, wherein the fourth mask pattern passes over the third semiconductor pattern. Then, when the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask, the gate metal layer is patterned by using the fourth mask pattern as a mask to form a metal. An electrode, wherein the metal common electrode passes over the third semiconductor pattern. In addition, when the dielectric layer is formed, it further covers the metal common electrode, and when the first contact window is formed, a fifth contact window is further formed in the dielectric layer to expose a portion of the third semiconductor pattern. Then, when the first source/drain contact metal is formed, the first source/drain contact metal is further connected to the third semiconductor pattern via the fifth contact window.

The etching process employed in the above various embodiments is, for example, a dry etching process. In more detail, the etching process is, for example, etching the first mask pattern and the second mask pattern by oxygen plasma.

Further, the substrate used in the above embodiments is, for example, a glass substrate, and the material of the first semiconductor pattern or the second semiconductor pattern is, for example, polycrystalline germanium. Further, the above-described first type ions are, for example, N-type ions, and the second type ions are, for example, P-type ions. In addition, the material of the first mask pattern, the second mask pattern or the patterned mask layer is, for example, a photoresist.

The invention further provides a semiconductor device, which mainly comprises a substrate, a first semiconductor pattern, a second semiconductor pattern, a gate insulating layer, a first gate and a second gate. The first semiconductor pattern is disposed on the substrate and has a first channel region, a first source/drain region on both sides of the first channel region, and the first channel region and the first source/drain region A lightly doped region that is symmetric with each other, wherein the first source/drain region and the lightly doped region have a first conductivity type. In addition, the second semiconductor pattern is disposed on the substrate, and the second semiconductor pattern has a second channel region and a second source/drain region on both sides of the second channel region, wherein the second source/drain region Has a second conductivity type. The gate insulating layer is disposed on the substrate and covers the first semiconductor pattern and the second semiconductor pattern. In addition, the first gate is disposed on the gate insulating layer, and the first gate is located above the first semiconductor pattern and correspondingly exposes the first source/drain region and the lightly doped region. The second gate is disposed on the gate insulating layer, and the second gate is located above the second semiconductor pattern and covers the second channel region and a portion of the second source/drain regions.

In an embodiment of the invention, the semiconductor device further includes a dielectric layer, a first source/drain contact metal, and a second source/drain contact metal. The dielectric layer is disposed on the gate insulating layer and covers the first gate and the second gate, and the dielectric layer has a plurality of portions exposing the first source/drain region and the second source/drain region A contact window. In addition, the first source/drain contact metal and the second source/drain contact metal are disposed in the first contact window, and are electrically connected to the corresponding first source/drain region and the second source, respectively. Polar/bungee area.

The above semiconductor device may further include a flat layer and an electrode pattern. The flat layer is disposed on the dielectric layer and covers the first source/drain contact metal and the second source/drain contact metal, and the second layer has a second contact window to expose the first source/汲Extremely contact with metal. Further, the electrode pattern is disposed on the planar layer and coupled to the first source/drain contact metal via the second contact window.

In an embodiment of the invention, the semiconductor device further includes a lower layer pad disposed on the gate insulating layer. In addition, the dielectric layer may further have a third contact window for exposing the lower layer pad.

In an embodiment of the invention, the semiconductor device further includes an upper layer pad disposed in the third contact window and connected to the lower layer pad. In addition, the flat layer may further have a fourth contact window for exposing the upper layer pad. A pad pattern may be formed in the fourth contact window to connect the upper layer pads.

In an embodiment of the invention, the semiconductor device further includes a third semiconductor pattern disposed on the substrate and covered by the gate insulating layer, and the third semiconductor pattern has a second conductivity type. Furthermore, the third semiconductor pattern is, for example, coupled to the first source/drain region.

In addition, the semiconductor device of the present invention may further include a metal common electrode disposed on the gate insulating layer and passing over the third semiconductor pattern.

The substrate described above is, for example, a glass substrate, and the material of the first semiconductor pattern or the second semiconductor pattern is, for example, polycrystalline germanium. Further, the first conductivity type is, for example, an N type, and the second conductivity type is, for example, a P type.

Based on the above, the lightly doped region in the thin film transistor structure formed by the present invention has a symmetrical length, thereby contributing to improvement in reliability and electrical performance when the device is operated. In addition, since the present invention adopts the same mask process to form gate patterns of different thin film transistors and elements such as metal common electrodes and lower pads, it is possible to effectively avoid the light that may be generated when the above components are fabricated by different mask processes. Cover alignment error helps improve process yield and reduces manufacturing costs.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The method for fabricating the semiconductor device of the present invention can be used in a liquid crystal display panel for fabricating a polycrystalline germanium film transistor as an active component in a pixel, and based on the process characteristics thereof, the related components of the periphery of the panel and the external pads can be simultaneously integrated. Production. The following embodiments will be described by simultaneously fabricating at least a P-type thin film transistor (PTFT), an N-type thin film transistor (NTFT), and an external pad or even a storage capacitor on a panel. However, it is for illustrative purposes only and is not intended to limit the scope of application of the present invention. For the similar component structures and processes in the field of semiconductors, the techniques proposed by the present invention can be employed to achieve better process results and product quality.

2A to 2O, a method of fabricating a semiconductor device according to an embodiment of the present invention is shown.

First, as shown in FIG. 2A, a substrate 202 is provided, and a first semiconductor pattern 212 and a second semiconductor pattern 214 are formed on the substrate 202. In this embodiment, the substrate 202 can be a glass substrate, a quartz substrate, a plastic substrate or other suitable transparent substrate, and the first semiconductor pattern 212 and the second semiconductor pattern 214 formed thereon are formed on the substrate 202, for example. A layer of amorphous germanium is subjected to a laser annealing process to form an amorphous germanium layer into a polycrystalline germanium layer, and then patterned by the polycrystalline germanium layer. The laser source used in the laser annealing process herein may be an excimer laser, a solid-state laser or a diode pumped solid state laser (DPSS). )and many more.

It is worth mentioning that the present invention can form a buffer layer on the substrate 202 as in the conventional polycrystalline germanium film transistor process to enhance the adhesion of the substrate 202 to the subsequently formed polysilicon layer, and to avoid the substrate 200. Metal ions (such as sodium) diffuse and contaminate the polycrystalline layer. In addition, before the laser annealing process, the amorphous germanium layer may be subjected to dehydrogenation to avoid hydrogen explosion in the amorphous germanium layer during the laser annealing process (hydrogen). Exploration) phenomenon. Those skilled in the art should be able to understand the above contents according to the existing technical standards, and this embodiment will not be disclosed in detail.

Next, as shown in FIG. 2B, a gate insulating layer 220 and a gate metal layer 230 are sequentially formed on the substrate 202, so that the gate insulating layer 220 and the gate metal layer 230 cover the first semiconductor pattern 212 and the second semiconductor pattern. 214. The method for forming the gate insulating layer 220 is, for example, chemical vapor deposition (CVD), and the material of the gate insulating layer 220 is, for example, silicon nitride (SiN) or silicon oxide (SiO). . In addition, the material of the gate metal layer 230 is, for example, chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-impedance metal, which is formed, for example, by sputtering or other thin film deposition processes. .

Then, as shown in FIG. 2C, a first mask pattern 242 and a second mask pattern 244 are formed on the gate metal layer 230, wherein the first mask pattern 242 is located above the first semiconductor pattern 212 and correspondingly exposed. a first source/drain region 212a on both sides of the first semiconductor pattern 212, and the second mask pattern 244 is located above the second semiconductor pattern 214 and correspondingly exposes a second source on both sides of the second semiconductor pattern 214 /Bungee area 214a. The method of forming the first mask pattern 242 and the second mask pattern 244 is, for example, performing photoresist coating on the gate metal layer 230 and a yellow light process such as exposure and development. It should be noted that the disclosed embodiment is a double gate thin film transistor structure, so as to avoid problems such as entanglement effect and leakage current, the first mask pattern 242 formed may have two parts. Both are located above the first semiconductor pattern 212. In addition, if an external pad is to be formed over the substrate 202, the third mask pattern 246 may be simultaneously formed on the gate metal layer 230 in this step.

Next, as shown in FIG. 2D, the gate metal layer 230 is patterned with the first mask pattern 242, the second mask pattern 244, and the third mask pattern 246 as masks to form on the gate insulating layer 220, respectively. A first gate pattern 232, a second gate pattern 234, and a lower layer pad 236. The patterning action here is achieved, for example, by performing a dry or wet etching process.

Then, as shown in FIG. 2E, the first gate pattern 232 corresponding to the first mask pattern 242, the second mask pattern 244 and the second gate pattern 234 corresponding thereto are the mask source to the first source/汲The polar region 212a and the second source/drain region 214a are doped with a first type of ions such that the first source/drain region 212a and the second source/drain region 214a have a first conductivity type. The first type of ion doping performed herein is, for example, N-type ion doping to implant an N-type dopant, such as a phosphorus ion, in the first source/drain region 212a and the second source/drain region 214a. . At the same time, the first channel region 212c and the second channel region 214c may be respectively defined in the first semiconductor pattern 212 and the second semiconductor pattern 214 under the first gate pattern 232 and the second gate pattern 234.

Then, as shown in FIG. 2F, an etching process is performed on the first mask pattern 242 and the second mask pattern 244 to remove portions of the outer walls of the first mask pattern 242 and the second mask pattern 244, thereby exposing a portion of the first gate pattern 232 and the second gate pattern 234. Further, if the third mask pattern 246 is simultaneously formed in the foregoing steps, the third mask pattern 246 is also etched together. The etching process performed in this step is, for example, a dry etching process. More specifically, the first mask pattern 242, the second mask pattern 244, and the third layer may be etched by, for example, a plasma such as an oxygen plasma. The mask pattern 246, also known as the photoresist ashing process, is characterized in that the first mask pattern 242, the second mask pattern 244, and the third mask pattern 246 are isotropically etched. For example, after the first mask pattern 242 is etched, in addition to the thickness reduction, the equal length L1 is also reduced on both sides.

Next, as shown in FIG. 2G, the first gate pattern 232 and the second gate pattern 234 are etched by the first mask pattern 242 and the second mask pattern 244 to form a first gate 232a and a The second gate 234a correspondingly exposes a first lightly doped region 212b inside the first source/drain region 212a of the first semiconductor pattern 212 and a second source/drain region of the second semiconductor pattern 214 A second lightly doped region 214b on the inside of 214a. Furthermore, if the third mask pattern 246 is simultaneously formed and etched in the foregoing steps, this step further includes etching a portion of the lower layer pad 236 with the third mask pattern 246 as a mask. It should be noted that since the first mask pattern 242, the second mask pattern 244 and the third mask pattern 246 are etched in the same direction, the left and right sides are reduced inward by the symmetrical distance, so the first exposed The lightly doped region 212b and the second lightly doped region 214b will also have a symmetrical length.

Then, as shown in FIG. 2H, the first light-doped region 212b and the second light-doped region 214b are lightly doped with the first type of ions by using the first gate 232a and the second gate 234a as masks. A lightly doped region 212b and a second lightly doped region 214b have a first conductivity type. Corresponding to the above-mentioned first type ion doping is N-type ion doping, the first type ion light doping performed here is, for example, also N-type ion doping, except that a lower concentration N-type dopant is used. For example, phosphorus ions.

In this embodiment, the first lightly doped region 212b having a symmetrical length is formed by the steps of FIGS. 2F to 2H, thereby effectively avoiding the mask alignment error when the lightly doped drain region is fabricated, thereby improving the thin film transistor. Electrical performance.

Next, as shown in FIG. 2I, the first mask pattern and the second mask pattern are removed, and another patterned mask layer 250 is formed on the substrate 202. The patterned mask layer 250 correspondingly exposes the second semiconductor pattern 214. The method of forming the patterned mask layer 250 is, for example, performing photoresist coating on the gate insulating layer 220 and a yellow light process such as exposure and development.

And, as shown in FIG. 2J, the second source/drain region 214a and the second lightly doped region 214b in the second semiconductor pattern 214 are subjected to opposite doping of the second type ions via the patterned mask layer 250 ( Counter-doping), so that the ion form of the second source/drain region 214a and the second lightly doped region 214b is changed from the first conductivity type to the second conductivity type. The first conductivity type is N-type with respect to the above, and the second conductivity type here is P-type, so the second type ion doping performed is, for example, P-type ion doping to be at the second source P-type dopants, such as boron ions, are implanted in the /drain region 214a and the second lightly doped region 214b. It is worth mentioning that, according to experimental results, in order to obtain a better opposite doping effect, the second source/drain region 214a and the second lightly doped region 214b can be successfully converted into the second conductivity type, The type II ion doping should have a similar ion implantation depth as the first type ion doping described above.

Thereafter, the patterned mask layer 250 is removed to obtain the structure of the semiconductor device as shown in FIG. 2K. The first source/drain region 212a, the first lightly doped region 212b, the first channel region 212c and the first gate 232a may constitute an NTFT structure, and the second source/drain region 214a and the second lightly doped The impurity region 214b, the second channel region 214c and the second gate 234a may constitute a PTFT structure. Wherein, the first lightly doped region 212b has a symmetrical length, thereby helping to improve the reliability and electrical performance of the component during operation.

On the other hand, the present invention uses the same mask process to form the first gate pattern 232, the second gate pattern 234, and the lower pad 236, and then combines opposite doping techniques to form different types of thin film transistors, such as PTFT. Compared with NTFT, it has the advantages of simple process, low cost and high yield compared with the prior art. In more detail, please refer to the peripheral circuit layout of the conventional liquid crystal display panel illustrated in FIG. 3A. The present invention is, for example, a CMOS-structured inverter 300. Since the inverter 300 is conventionally fabricated using two different mask processes to separately form the PTFT 310 and the NTFT 320, the front and rear light are respectively The gate metal patterns 330a and 330b defined in the mask process may not be connected due to the alignment error of the mask, affecting the process yield and increasing the complexity of the process. Furthermore, considering the alignment error of the reticle, it is necessary to sacrifice a part of the layout area in order to provide a reasonable process margin when designing the component layout of the front end. On the other hand, referring to a peripheral circuit layout of the present invention shown in FIG. 3B, if the fabrication method of the above embodiment of the present invention is adopted, the gate metal patterns 332 of the PTFT 310 and the NTFT 320 can be simultaneously defined by the same mask process. The above problems can be overcome, which helps to reduce the number of masks required for the process, reduce costs, and improve process yield.

Following the steps illustrated in FIG. 2K, the present embodiment can further perform subsequent steps to form a source/drain contact metal, a pixel electrode, an upper pad, and the like.

Referring to FIG. 2L, after the patterned mask layer 250 is removed, a dielectric layer 260 may be further formed on the gate insulating layer 220 to cover the first gate 232a, the second gate 234a, and the foregoing optional formation. Lower layer pad 236. Also, a plurality of first contact windows 262 and third contact windows 264 are formed in the dielectric layer 260 and the gate insulating layer 220. The first contact window 262 exposes the first source/drain region 212a of the first semiconductor pattern 212 and the second source/drain region 214a of the second semiconductor pattern 214, and the third contact window 264 exposes the lower layer pad 236. The method of forming the first contact window 262 and the third contact window 264 is, for example, performing a yellow light process on the dielectric layer 260 and a subsequent etching process.

Then, as shown in FIG. 2M, a first source/drain contact metal 272 and a second source/drain contact metal 274 are formed in the first contact window 262 to make the first source/drain contact The metal 272 and the second source/drain contact metal 274 are electrically connected to the corresponding first source/drain region 212a and the second source/drain region 214a, respectively. Moreover, an upper bonding pad 276 can be simultaneously formed in the third contact window 264 corresponding to the lower bonding pad 236, so that the upper bonding pad 276 and the lower bonding pad 236 are connected to each other. The method of forming the first source/drain contact metal 272, the second source/drain contact metal 274, and the upper pad 276 is, for example, first forming a source/drain metal layer on the dielectric layer 260 (not Illustrated), and then the source/dip metal layer is formed by a yellow light and an etching process. In addition, the source/drain metal layer may be made of chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-impedance metal, for example, by sputtering or Other thin film deposition processes are formed.

Next, as shown in FIG. 2N, a flat layer 280 is formed on the dielectric layer 260 to cover the first source/drain contact metal 272, the second source/drain contact metal 274, and the optional upper layer. Pad 276. Moreover, a second contact window 282 and a fourth contact window 284 are formed in the planar layer 280, wherein the second contact window 282 exposes the first source/drain contact metal 272, and the fourth contact window 284 exposes the upper layer Pad 276. The method of forming the second contact window 282 and the fourth contact window 284 is, for example, performing a yellow light process on the dielectric layer 280 and a subsequent etching process.

Thereafter, as shown in FIG. 2O, an electrode pattern 290 and a pad pattern 292 are formed on the flat layer 280, wherein the electrode pattern 290 is connected to the first source/drain contact metal 272 via the second contact window 282 as A pixel electrode is connected to the upper pad 276 via the fourth contact window 284 as an external pad. The method of forming the electrode pattern 290 and the pad pattern 292 here is, for example, forming a conductive material layer (not shown) on the flat layer 280, and then forming an etching process on the conductive material layer. The conductive material layer may be made of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), for example, by sputtering or other thin film deposition process. form.

The present invention has been substantially completed for use in a semiconductor element structure including a pixel region and a peripheral wiring region of a liquid crystal display panel, and the contents of the present invention will be described below by way of other embodiments. Please refer to FIG. 4A to FIG. 4J, which illustrate a method of fabricating a semiconductor device according to another embodiment of the present invention. It is to be noted that the detailed implementation of the partial process in the following embodiments is similar to that disclosed in the foregoing embodiments. Therefore, the related embodiments are referred to the foregoing embodiments, and the detailed description thereof will not be repeated below.

First, as shown in FIG. 4A, a substrate 402 is formed to form a first semiconductor pattern 412 and a second semiconductor pattern 414 on the substrate 402, and a second source/drain region 414a of the second semiconductor pattern 414 is formed. The second type of ion doping is performed to have a second conductivity type. In this embodiment, the substrate 402 can also be a glass substrate, a quartz substrate, a plastic substrate or other suitable transparent substrate, and the first semiconductor pattern 412 and the second semiconductor pattern 414 are formed, for example, by a laser annealing process to form a polysilicon layer. The patterning step is further carried out. In addition, the step of performing the second type ion doping on the second source/drain region 414a is achieved, for example, by using a photoresist layer 404 as a mask. In addition, the manufacturing method can selectively form a storage capacitor and an external pad over the substrate 402. Therefore, a third semiconductor pattern 418 can be additionally formed on the substrate 402 in this step, and the third semiconductor pattern 418 can be simultaneously applied. The second type of ion doping is performed to have a second conductivity type. The second type of ion doping performed herein is, for example, P-type ion doping to implant a P-type dopant, such as boron ions, in the second source/drain region 414a and the third semiconductor pattern 418. At the same time, a second channel region 414c can be defined in the second semiconductor pattern 414.

Next, as shown in FIG. 4B, a gate insulating layer 420 is formed on the substrate 402 to cover the first semiconductor pattern 412, the second semiconductor pattern 414, and the third semiconductor pattern 418. Also, a gate metal layer 430 is formed on the gate insulating layer 420. The method for forming the gate insulating layer 420 is, for example, chemical vapor deposition (CVD), and the material of the gate insulating layer 420 is, for example, silicon nitride (SiN) or silicon oxide (SiO). . In addition, the material of the gate metal layer 430 is, for example, chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-impedance metal, which is formed, for example, by sputtering or other thin film deposition processes. .

Then, as shown in FIG. 4C, a first mask pattern 442 and a second mask pattern 444 are formed on the gate metal layer 430, wherein the first mask pattern 442 is over the first semiconductor pattern 412 and correspondingly exposed. A first source/drain region 412a of the first semiconductor pattern 412 is formed, and the second mask pattern 444 is located above the second semiconductor pattern 414 and correspondingly exposes a second source/汲 of the portion of the second semiconductor pattern 414 Polar zone 414a. In addition, if the storage capacitor and the external pad are selectively formed as described above, a third mask pattern 446 and a fourth mask pattern 448 may be additionally formed on the gate metal layer 430 in the step, wherein the fourth mask Pattern 448 passes over third semiconductor pattern 418. The method of forming the first mask pattern 442 and the second mask pattern 444 is, for example, performing photoresist coating on the gate metal layer 430 and a yellow light process such as exposure and development.

Next, as shown in FIG. 4D, the gate metal layer 430 is patterned by using the first mask pattern 442, the second mask pattern 444, the third mask pattern 446, and the fourth mask pattern 448 as masks, respectively. A first gate pattern 432, a second gate pattern 434, a lower layer pad 436, and a metal common electrode 438 over the third semiconductor pattern 418 are formed. Thereafter, the first source/drain region 412a is first doped with the first mask pattern 442 and the first gate pattern 432 as a mask, so that the first source/drain region 412a has The first conductivity type while the second source/drain region 414a maintains the second conductivity type. The patterning action here is achieved, for example, by performing a dry or wet etching process, and the first type of ion doping performed is, for example, N-type ion doping to be in the first source/drain region 412a. An N-type dopant such as a phosphorus ion is implanted therein. It is worth noting that since the second source/drain region 414a has to maintain the original second conductivity pattern after this step, the P-type dopant concentration of the second type ion doping performed in the foregoing should be It is larger than the N-type dopant concentration of the first type ion doping here. Meanwhile, a first channel region 412c may be defined in the first semiconductor pattern 412 under the first gate pattern 432.

Then, as shown in FIG. 4E, an etching process is performed on the first mask pattern 442 and the second mask pattern 444 to remove the outer wall of the partial thickness of the first mask pattern 442 and the second mask pattern 444. A portion of the first gate pattern 432 and the second gate pattern 434 are exposed. Then, the first gate pattern 432 and the second gate pattern 434 are etched by using the first mask pattern 442 and the second mask pattern 444 after the partial outer wall is removed to form a first gate 432a. And a second gate 434a, wherein the first gate 432a correspondingly exposes a lightly doped region 412b inside the first source/drain region 412a of the first semiconductor pattern 412, and the second gate 434a covers the second portion A channel region 414c of the semiconductor pattern 414 and a portion of the second source/drain region 414a. In addition, if the third mask pattern 446 and the fourth mask pattern 448 are simultaneously formed in the foregoing steps, the third mask pattern 446 and the fourth mask pattern 448 are also etched together. The etching process performed in this step is, for example, a dry etching process. In more detail, for example, the first mask pattern 442, the second mask pattern 444, and the third layer may be etched by a plasma such as an oxygen plasma. The mask pattern 446 and the fourth mask pattern 448, which is generally referred to as a photoresist ashing process, are characterized in that the first mask pattern 442, the second mask pattern 444, and the third mask can be applied. The pattern 446 and the fourth mask pattern 448 are isotropically etched. For example, after the first mask pattern 442 is etched, in addition to the thickness reduction, the equal length L2 is also reduced on both sides. In addition, the etching step also includes etching a portion of the lower pad 436 and a portion of the metal common electrode 438 with the third mask pattern 446 and the fourth mask pattern 448 as masks, respectively. It should be noted that since the first mask pattern 442 is etched in an isotropic manner so that the left and right sides thereof are reduced inward by a symmetric distance, the exposed lightly doped region 412b also has a symmetrical length.

Next, as shown in FIG. 4F, the light-doped region 412b is lightly doped with the first type ion by using the first mask pattern 442 and the corresponding first gate 432a as a mask, so that the lightly doped region 412b has The first conductivity type. The first type of ion light doping performed herein is, for example, also N-type ion doping, except that a lower concentration of N-type dopants, such as phosphorus ions, is used. As before, the second source/drain region 414a must maintain the second conductivity pattern after this step. It is worth mentioning that since the second mask pattern 444 and the second gate pattern 434 under it are formed (as shown in FIG. 4C), it is still necessary to pass through. Subsequent etching processes (as shown in Figure 4E) are etched away from the thickness of the portion and the lateral length. Therefore, in order to ensure that the second channel region 434c under the second gate pattern 434 is not doped with the first type ions in this step, the second mask pattern 444 and the second gate are required in the design of the film layer pattern. The pole pattern 434 and the subsequently formed second gate 434a maintain a state of covering the second channel region 434c in the foregoing process.

Thus, the first source/drain region 412a, the lightly doped region 412b, the first channel region 412c and the first gate 432a can form an NTFT structure, and the second source/drain region 414a and the second channel The region 414c and the second gate 434a may constitute a PTFT structure.

Then, as shown in FIG. 4G, the first mask pattern 442 and the second mask pattern 444, the third mask pattern 446 and the fourth mask pattern 448 are removed to form a dielectric layer 460 on the gate insulating layer 420. The first gate 432a, the second gate 434b, and the optional underlying pad 436 and the metal common electrode 438 are covered. Moreover, a plurality of first contact windows 462, a third contact window 464, and a fifth contact window 466 are formed in the dielectric layer 460 and the gate insulating layer 420. The first contact window 462 exposes the first source/drain region 412a of the first semiconductor pattern 412, the second source/drain region 414a of the second semiconductor pattern 414, and the third contact window 464 exposes the lower layer pad 436 And the fifth contact window 466 exposes a portion of the third semiconductor pattern 418. The method of forming the first contact window 462, the third contact window 464, and the fifth contact window 466 is, for example, performing a yellow light process on the dielectric layer 460 and a subsequent etching process.

Then, as shown in FIG. 4H, a first source/drain contact metal 472, a second source/drain contact metal 474 are formed in the first contact window 462, and an upper pad 476 is formed. In the three contact window 464, the first source/drain contact metal 472 and the second source/drain contact metal 474 are electrically connected to the corresponding first source/drain region 412a and the second source, respectively. / drain region 414a, and upper pad 476 is connected to lower pad 436 via third contact window 464. In addition, the first source/drain contact metal 472 is also connected to the third semiconductor pattern 418 via the fifth contact window 466 at the same time, so that the first source/drain region 412a and the third semiconductor pattern 418 are electrically connected to each other. As such, when the display signal is introduced into the third semiconductor pattern 418 by the first source/drain region 412a, a storage capacitor is formed between the third semiconductor pattern 418 and the metal common electrode 438 above it. The method of forming the first source/drain contact metal 472, the second source/drain contact metal 474, and the upper pad 476 is, for example, first forming a source/drain metal layer on the dielectric layer 460 (not Illustrated), and then the source/dip metal layer is formed by a yellow light and an etching process. In addition, the source/drain metal layer may be made of chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-impedance metal, for example, by sputtering or Other thin film deposition processes are formed.

Next, as shown in FIG. 4I, a flat layer 480 is formed on the dielectric layer 460 to cover the first source/drain contact metal 472, the second source/drain contact metal 474, and the optional upper layer. Pad 476. Moreover, a second contact window 482 and a fourth contact window 484 are formed in the flat layer 480, wherein the second contact window 482 exposes the first source/drain contact metal 472, and the fourth contact window 484 exposes the upper layer. Pad 476. The method of forming the second contact window 482 and the fourth contact window 484 is, for example, performing a yellow light process on the dielectric layer 480.

Thereafter, as shown in FIG. 4J, an electrode pattern 490 and a pad pattern 492 are formed on the flat layer 480, wherein the electrode pattern 490 is connected to the first source/drain contact metal 472 via the second contact window 482 as A pixel electrode is connected to the upper pad 476 via the fourth contact window 484 as an external pad. The method of forming the electrode pattern 490 and the pad pattern 492 here is, for example, forming a conductive material layer (not shown) on the flat layer 480, and then forming an etching process on the conductive material layer. The conductive material layer may be made of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), for example, by sputtering or other thin film deposition process. form.

The lightly doped regions in the thin film transistor structure formed by the above embodiments also have a symmetrical length, thereby contributing to improved reliability and electrical performance during operation of the device. In addition, since the above embodiment also uses the same mask process to form the gate patterns of the different thin film transistors and the metal common electrode, the lower layer pads and the like, it can effectively avoid the possibility that the above components can be produced by different mask processes. The reticle alignment error helps to improve the process yield, and can save the layout area of the substrate that must be sacrificed in the front-end component layout design, thereby reducing the manufacturing cost.

On the other hand, in the above embodiment, the storage capacitor can be integrated. When the first semiconductor pattern and the second semiconductor pattern are formed, a third semiconductor pattern that can serve as an electrode under the storage capacitor is formed together, and the third semiconductor pattern is formed. The ions are doped to make them electrically conductive. Therefore, the semiconductor device formed in this embodiment can be matched with a good storage capacitor, and when applied to a liquid crystal display panel, it will help to improve the display quality of the liquid crystal display panel.

While the invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and it is possible to make a few changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Substrate

102. . . The buffer layer

110. . . Polycrystalline layer

112. . . Source area

112a. . . Contact window opening

114. . . Bungee area

114a. . . Contact window opening

116. . . Channel area

118. . . Lightly doped bungee zone

120. . . Brake insulation

130. . . Gate

140. . . Dielectric layer

152. . . Source metal layer

154. . . Bungee metal layer

202. . . Substrate

212. . . First semiconductor pattern

212a. . . First source/drain region

212b. . . First lightly doped region

212c. . . First passage area

214. . . Second semiconductor pattern

214a. . . Second source/drain region

214b. . . Second lightly doped region

214c. . . Second passage zone

220. . . Brake insulation

230. . . Gate metal layer

232. . . First gate pattern

232a. . . First gate

234. . . Second gate pattern

234a. . . Second gate

236. . . Underlying pad

242. . . First mask pattern

244. . . Second mask pattern

246. . . Third mask pattern

250. . . Patterned mask layer

260. . . Dielectric layer

262. . . First contact window

264. . . Third contact window

272. . . First source/drain contact metal

274. . . Second source/drain contact metal

276. . . Upper pad

280. . . Flat layer

282. . . Second contact window

284. . . Fourth contact window

290. . . Electrode pattern

292. . . Mat pattern

L1. . . length

300. . . Inverter

310. . . PTFT

320. . . NTFT

330a, 330b, 332. . . Gate metal pattern

402. . . Substrate

404. . . Photoresist layer

412. . . First semiconductor pattern

412a. . . First source/drain region

412b. . . Lightly doped area

412c. . . First passage area

414. . . Second semiconductor pattern

414a. . . Second source/drain region

414c. . . Second passage zone

418. . . Third semiconductor pattern

420. . . Brake insulation

430. . . Gate metal layer

432. . . First gate pattern

432a. . . First gate

434. . . Second gate pattern

434a. . . Second gate

436. . . Underlying pad

438. . . Metal common electrode

442. . . First mask pattern

444. . . Second mask pattern

446. . . Third mask pattern

448. . . Fourth mask pattern

460. . . Dielectric layer

462. . . First contact window

464. . . Third contact window

466. . . Fifth contact window

472. . . First source/drain contact metal

474. . . Second source/drain contact metal

476. . . Upper pad

480‧‧‧flat layer

482‧‧‧Second contact window

484‧‧‧4th contact window

490‧‧‧electrode pattern

492‧‧‧push pattern

L2‧‧‧ length

1 is a schematic cross-sectional view of a conventional low temperature polycrystalline germanium film transistor.

2A to 2O illustrate a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

FIG. 3A illustrates a peripheral circuit layout of a conventional liquid crystal display panel.

Figure 3B illustrates a peripheral line layout of the present invention.

4A-4J illustrate a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.

402. . . Substrate

412. . . First semiconductor pattern

412a. . . First source/drain region

412b. . . Lightly doped area

412c. . . First passage area

414. . . Second semiconductor pattern

414a. . . Second source/drain region

414c. . . Second passage zone

418. . . Third semiconductor pattern

420. . . Brake insulation

432. . . First gate pattern

432a. . . First gate

434. . . Second gate pattern

434a. . . Second gate

436. . . Underlying pad

438. . . Metal common electrode

460. . . Dielectric layer

472. . . First source/drain contact metal

474. . . Second source/drain contact metal

476. . . Upper pad

480. . . Flat layer

490. . . Electrode pattern

492. . . Mat pattern

Claims (13)

A semiconductor device includes: a substrate; a first semiconductor pattern disposed on the substrate, and the first semiconductor pattern has a first channel region, and a first source/汲 on both sides of the first channel region a polar region and a lightly doped region between the first channel region and the first source/drain region and symmetrical with each other, wherein the first source/drain region and the lightly doped region have a first a second semiconductor pattern disposed on the substrate, the second semiconductor pattern having a second channel region and a second source/drain region on both sides of the second channel region, wherein the second semiconductor pattern The second source/drain region has a second conductivity type; a third semiconductor pattern is disposed on the substrate, the third semiconductor pattern is entirely in the second conductivity type; and a gate insulating layer is disposed on the substrate And covering the first semiconductor pattern, the second semiconductor pattern and the third semiconductor pattern; a first gate is disposed on the gate insulating layer, wherein the first gate is located above the first semiconductor pattern Correspondingly exposing the first source/drain region and a lightly doped region; and a second gate disposed on the gate insulating layer, wherein the second gate is over the second semiconductor pattern and covers the second channel region and a portion of the second source/汲Polar zone. The semiconductor device of claim 1, further comprising: a dielectric layer disposed on the gate insulating layer and covering the first gate And the second gate, and the dielectric layer has a plurality of first contact windows exposing the first source/drain region and the second source/drain region; and a first source/ a gate contact metal and a second source/drain contact metal disposed in the first contact windows and electrically connected to the corresponding first source/drain region and the second source Polar/bungee area. The semiconductor device of claim 2, further comprising: a planar layer disposed on the dielectric layer and covering the first source/drain contact metal to be in contact with the second source/drain a metal having a second contact window in the planar layer to expose the first source/drain contact metal; and an electrode pattern disposed on the planar layer and coupled via the second contact window The first source/drain contacts the metal. The semiconductor device of claim 3, further comprising a lower layer pad disposed on the gate insulating layer. The semiconductor device of claim 4, wherein the dielectric layer further has a third contact window for exposing the underlying pad. The semiconductor device of claim 5, further comprising an upper layer pad disposed in the third contact window and connected to the lower layer pad. The semiconductor device of claim 6, wherein the flat layer further has a fourth contact window for exposing the upper layer pad. The semiconductor device of claim 7, further comprising a pad pattern disposed in the fourth contact window and connected to the upper layer pad. The semiconductor device of claim 1, wherein the third semiconductor pattern is coupled to the first source/drain region. The semiconductor device of claim 9, further comprising a metal common electrode disposed on the gate insulating layer and passing over the third semiconductor pattern between the metal common electrode and the third semiconductor pattern A storage capacitor is formed. The semiconductor component of claim 1, wherein the substrate comprises a glass substrate. The semiconductor device of claim 1, wherein the material of the first semiconductor pattern or the second semiconductor pattern comprises polysilicon. The semiconductor device of claim 1, wherein the first conductivity type comprises an N type and the second conductivity type comprises a P type.