TWI445305B - Spike voltage reducing circuit for power transistor and power semiconductor chip with the same - Google Patents

Description

Surge voltage eliminating circuit for power transistor and power semiconductor chip having the same

The present invention relates to a surge voltage cancellation circuit, and more particularly to a surge voltage cancellation circuit for a power transistor.

Power MOSFETs are commonly used in AC-DC power converters. Too fast switching rates tend to suffer from electromagnetic interference (EMI) problems caused by excessive spikes. To reduce the surge voltage, as shown in Fig. 1, the usual way is to add a resistor R0 between the gate terminal G of the power transistor Q0 and the driving circuit 100 to slow down the switching speed of the transistor Q0, but The price paid is the power consumption when the transistor Q0 switches. Especially for high voltage power transistors, the switching loss has a very serious effect on energy utilization efficiency. However, too high a surge voltage can also damage the component. Therefore, how to reduce the surge voltage, but maintain a certain energy conversion efficiency, is very important for high-voltage power transistors.

Second, there are many snubber circuit designs on the market today that can reduce the surge voltage generated by transient switching. However, these vibration-damping circuits require additional capacitors, inductors, and resistor components, which increases the manufacturing cost.

Accordingly, the present invention provides a surge voltage cancellation circuit that can be coupled to a power transistor to reduce the adverse effects of the surge voltage on the power transistor.

The main object of the present invention is to provide a surge voltage canceling circuit which can effectively reduce the surge voltage while avoiding an excessive increase in the switching loss of the power transistor.

Another object of the present invention is to provide a surge voltage canceling circuit that can be integrated into a power transistor wafer to reduce the overall manufacturing cost.

One embodiment of the present invention provides a surge voltage cancellation circuit. The surge voltage cancellation circuit includes an input terminal, a first current path, a second current path, a first resistor, a second resistor, and a first Zener diode. The first current path is between the input terminal and one of the gate terminals of a power transistor structure. The second current path is also between the input terminal and the aforementioned gate terminal. The first resistance is located on the first current path. The second resistor is located on the second current path, and the resistance of the second resistor is greater than the resistance of the first resistor. The first Zener diode system is located on the first current path and is connected in the forward direction between the input terminal and the gate terminal. Wherein, when the voltage difference between the input terminal and the gate terminal is greater than the breakdown voltage of the first Zener diode, the voltage drop rate of the gate terminal is substantially determined by the current on the first current path, when the input terminal and the gate terminal are When the voltage difference is less than the breakdown voltage of the first Zener diode, the voltage drop rate of the gate terminal is substantially determined by the current on the second current path.

According to an embodiment of the invention, the surge voltage canceling circuit has a second Zener diode located on the first current path and connected in reverse between the input terminal and the gate terminal. When the voltage difference between the input terminal and the gate terminal is less than the voltage of the first Zener diode and the breakdown voltage of the second Zener diode, the voltage rise rate of the gate terminal is substantially from the second current path. The current determines that when the voltage difference between the input terminal and the gate terminal is greater than the voltage of the first Zener diode and the breakdown voltage of the second Zener diode, the voltage rise rate of the gate terminal is substantially The current on the first current path is determined.

One embodiment of the present invention provides a power semiconductor wafer having a surge voltage cancellation circuit. The wafer includes a power transistor structure and a gate contact structure. The gate contact structure has an input terminal, a first current path, a second current path, a first resistor, a second resistor and a first Zener diode. The first current path is between the input terminal and the gate terminal of the power transistor structure. The second current path is also between the input terminal and the gate terminal of the power transistor structure. The first resistance is located on the first current path. The second resistor is located on the second current path, and the resistance of the second resistor is greater than the resistance of the first resistor. The first Zener diode system is located on the first current path and is electrically connected between the input terminal and the gate terminal of the power transistor structure. When the voltage difference between the input terminal and the gate terminal is greater than the breakdown voltage of the first Zener diode, the voltage drop rate of the gate terminal of the power transistor structure is substantially determined by the current on the first current path, when the input terminal is When the voltage difference between the gate terminals is less than the breakdown voltage of the first Zener diode, the voltage drop rate of the gate terminal of the power transistor structure is substantially determined by the current on the second current path.

According to an embodiment of the invention, the input terminal is located in a gate metal contact pad, and the gate terminal is located in a gate polysilicon structure. The first current path is formed by the gate metal contact pad via a first polysilicon structure of the first conductivity type and a second polysilicon structure of the second conductivity type, directly to the gate polysilicon structure. The second current path is connected to the gate polysilicon structure via the gate metal contact pad via the second polysilicon structure. Wherein, a first Zener diode is formed between the first polysilicon structure and the second polysilicon structure, and the second polysilicon structure between the first polysilicon structure and the gate polysilicon structure is used as the first resistor The second polysilicon structure between the gate metal contact pad and the gate polysilicon structure is used as the second resistor.

According to an embodiment of the invention, the gate contact structure of the wafer has a second Zener diode located in the first current path and connected in reverse between the input terminal and the gate terminal. When the voltage difference between the input terminal and the gate terminal is less than the voltage of the first Zener diode and the breakdown voltage of the second Zener diode, the voltage rise rate of the gate terminal is substantially from the second current path. The current determines that when the voltage difference between the input terminal and the gate terminal is greater than the voltage of the first Zener diode and the breakdown voltage of the second Zener diode, the voltage rise rate of the gate terminal is substantially The current on the first current path is determined.

In the foregoing embodiment, the input terminal is located in a gate metal contact pad, and the gate terminal is located in a gate polysilicon structure. The first current path is formed by a gate metal contact pad, a first polysilicon structure of a first conductivity type, a third polysilicon structure of a second conductivity type, and a second polysilicon of a first conductivity type Structure, straight to the gate polysilicon structure. The second current path is connected to the gate polysilicon structure via the gate metal contact pad via the second polysilicon structure. Wherein, a first Zener diode is formed between the first polycrystalline germanium structure and the third polycrystalline germanium structure, and a second Zener diode is formed between the third polycrystalline germanium structure and the second polycrystalline germanium structure, The second polysilicon structure between the third polysilicon structure and the gate polysilicon structure serves as a first resistor, and the second polysilicon structure between the gate metal contact pad and the gate polysilicon structure serves as a second resistor.

The surge voltage cancellation circuit provided by one embodiment of the present invention helps to increase efficiency and reduce surge voltage. In addition, an embodiment of the present invention integrates the surge voltage cancellation circuit into the power semiconductor wafer, which further reduces the cost of the external drive circuit.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

Fig. 3 is a circuit diagram showing a preferred embodiment of the surge voltage canceling circuit of the present invention. As shown in the figure, the surge voltage eliminating circuit 200 has an input terminal IN, a first resistor R1, a second resistor R2, a first Zener diode ZD1 and a second Zener. Diode ZD2. The input terminal IN is connected to a driving circuit 100, such as a pulse modulation control circuit, to receive a square wave driving signal. Between the input terminal IN and the gate terminal G of the power transistor structure Q1, there is a first current path and a second current path. The first resistor R1, the first Zener diode ZD1 and the second Zener diode ZD2 are located on the first current path. The second resistor R2 is located on the second current path, and the resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1.

As shown in the figure, the first Zener diode ZD1 is connected in the forward direction between the input terminal IN and the gate terminal G, and the second Zener diode ZD2 is connected in the reverse direction to the input terminal IN and the gate terminal G. between. In the process of rising the square wave drive signal VIN, please also refer to FIG. 4, when the voltage difference between the square wave drive signal VIN and the gate voltage signal VGS (VIN-VGS) is smaller than the conduction of the first Zener diode ZD1. The voltage and the voltage of the breakdown voltage of the second Zener diode ZD2 and v1, the first current path has not been turned on. At this time, the rate of rise of the gate voltage signal VGS is mainly determined by the magnitude of the current on the second current path, that is, by the second resistor R2. Since the resistance value of the second resistor R2 is large, the gate voltage signal VGS is in a slowly rising state.

As the voltage of the square wave drive signal VIN rises, the voltage difference (VIN-VGS) between the square wave drive signal VIN and the gate voltage signal VGS also gradually increases. At time t1, when the voltage difference between the square wave drive signal VIN and the gate voltage signal VGS (VIN-VGS) is greater than the voltage of the turn-on voltage of the first Zener diode ZD1 and the breakdown voltage of the second Zener diode ZD2 And v1, the first current path begins to conduct. Since the resistance value of the first resistor R1 is significantly smaller than the resistance value of the second resistor R2, at this time, the rising rate of the gate voltage signal VGS is mainly determined by the magnitude of the current on the first current path, that is, by the first resistor R1. Therefore, therefore, the rate of rise of the gate voltage signal VGS will increase. Moreover, the lower the resistance value of the first resistor R1, the faster the rising rate of the gate voltage signal VGS.

At time t2, the capacitance CGS between the gate and the source of the power transistor structure Q1 is fully charged, at which point the current begins to charge the Miller capacitor. During this charging process, the gate voltage signal VGS will remain substantially constant. After the charging of the Miller capacitor is completed, the gate voltage signal VGS will continue to rise until the gate voltage signal VGS is equal to the input terminal voltage VIN.

Referring to Fig. 2, since the square wave drive signal VIN is switched from a low potential to a high potential at a relatively fast speed, in this process, an induced current is inevitably generated, resulting in switching loss. In contrast, referring to FIG. 4, this embodiment reduces the rate at which the gate voltage signal VGS rises. Since the magnitude of the induced current is proportional to the rising speed of the gate voltage signal VGS, the present invention can reduce the induced current generated and contribute to reducing the switching loss (energy loss equals the product of voltage and current).

Next, in the falling portion of the square wave drive signal VIN, initially, the voltage difference (VGS-VIN) between the square wave drive signal VIN and the gate voltage signal VGS is smaller than the turn-on voltage of the first Zener diode ZD1 and the second The voltage of the breakdown voltage of the Zener diode ZD2 and v2, the first current path has not been turned on. As the potential of the square wave drive signal VIN decreases, the voltage difference (VGS-VIN) between the square wave drive signal VIN and the gate voltage signal VGS gradually increases. When the voltage difference between the square wave drive signal VIN and the gate voltage signal VGS (VGS-VIN) is greater than the turn-on voltage of the first Zener diode ZD1 and the voltage of the breakdown voltage of the second Zener diode ZD2 and v2, A current path begins to conduct. At this time, the falling rate of the gate voltage signal VGS mainly depends on the magnitude of the current on the first current path, that is, determined by the first resistor R1, and therefore, the gate voltage signal VGS drops rapidly.

Subsequently, at time t3, the voltage difference (VGS-VIN) between the square wave drive signal VIN and the gate voltage signal VGS is smaller than the turn-on voltage of the first Zener diode ZD1 and the breakdown voltage of the second Zener diode ZD2. When the voltage and v2, the first current path stops conducting. At this time, the rising rate of the gate voltage signal VGS is determined by the second resistor R2 on the second current path, and therefore, the falling speed of the gate voltage signal VGS is slowed down.

Referring to Fig. 2, during the fast switching process of the transistor element, the spike voltage Vsp is too high at the moment when the transistor element is turned off. Although reducing the switching speed of the transistor element can alleviate the problem that the surge voltage Vsp is too high, it causes an increase in switching loss. In contrast, referring to Fig. 4, in the present embodiment, the transistor element substantially maintains its switching speed. When the gate voltage signal VGS is lowered to near zero, the speed at which the potential drops is slowed down. Therefore, the problem that the surge voltage Vsp is excessively high can be avoided, and the switching loss can be prevented from being excessively increased.

As shown in FIG. 4, in terms of the voltage difference between the square wave drive signal VIN and the gate voltage signal VGS, a rising edge transition voltage v1 is used as a demarcation point in the rising edge of the gate voltage signal. It can be roughly divided into a portion where the voltage rise rate is slower and a portion where the voltage rise rate is faster. Similarly, in the falling edge of the gate voltage signal VGS, a falling point transition voltage v2 is used as a demarcation point, which can be roughly divided into a portion where the voltage drop rate is faster and a portion where the voltage drop rate is slower. . The aforementioned breakover voltages v1 and v2 can be adjusted by changing the parameters of the first Zener diode ZD1 and the second Zener diode ZD2 as needed.

Fig. 5 is a circuit diagram showing another preferred embodiment of the surge voltage canceling circuit of the present invention. Compared with the surge voltage eliminating circuit 200 of FIG. 3, the first voltage path of the surge voltage eliminating circuit 300 of the present embodiment has only a first resistor R1 and a first Zener diode ZD3. The first Zener diode ZD3 is also connected in the forward direction between the input terminal IN and the gate terminal G of the power transistor structure.

In the process of rising the square wave drive signal, please refer to FIG. 6 again, since the resistance value of the first resistor R1 is significantly smaller than the resistance value of the second resistor R2, the rising rate of the gate voltage signal VGS is mainly determined by the first The magnitude of the current in the current path, which is determined by the first resistor R1. Therefore, the gate voltage signal VGS will rise rapidly.

Next, in the falling portion of the square wave driving signal VIN, initially, the voltage difference (VGS-VIN) between the square wave driving signal VIN and the gate voltage signal VGS is smaller than the breakdown voltage v3 of the first Zener diode ZD3, A current path has not been turned on. As the potential of the square wave drive signal VIN decreases, the voltage difference (VGS-VIN) between the square wave drive signal VIN and the gate voltage signal VGS gradually increases. When the voltage difference (VIN-VGS) between the square wave drive signal VIN and the gate voltage signal VGS is greater than the breakdown voltage v3 of the first Zener diode ZD3, the first current path remains in an on state. At this time, the falling rate of the gate voltage signal VGS is mainly determined by the magnitude of the current of the first current path, that is, by the first resistor R1, and therefore, the gate voltage signal VGS is rapidly decreased. Subsequently, at time t4, when the voltage difference (VIN-VGS) of the square wave drive signal VIN and the gate voltage signal VGS falls below the collapse voltage v3 of the first Zener diode ZD3, the first current path stops conducting. . At this time, the rising rate of the gate voltage signal VGS is determined by the second resistor R2 on the second current path, and therefore, the falling speed of the gate voltage signal VGS is slowed down.

7a and 7b are top and cross-sectional views of a preferred embodiment of the power semiconductor chip integrated with the surge voltage cancellation circuit of FIG. Here, the sectional view shown in Fig. 7b corresponds to the A-A' cross section in Fig. 7a. The figure shows a gate contact structure of a power semiconductor wafer. This gate contact structure is connected to the gate terminal of the power transistor structure. The gate and the left and right sides of the gate contact structure in the figure can be extended to connect the gate polysilicon structure of the power transistor structure to pass the gate voltage signal.

The gate contact structure has a first polysilicon structure 423 of a first conductivity type and a second polysilicon structure 425 of a second conductivity type formed on a substrate 410. In the present embodiment, the first conductivity type is a P type, the second conductivity type is an N type, and the second polysilicon structure 425 surrounds the first polysilicon structure 423. Moreover, in a preferred embodiment, the first polysilicon structure and the second polysilicon structure may be formed in the same polysilicon layer.

An interlayer dielectric layer 430 is overlying the first polysilicon structure 423 and the second polysilicon structure 425. The gate metal contact pad 445 is coupled to the first polysilicon structure 423 through at least one first plug 433 while being coupled to the second polysilicon structure 425 via at least one second plug 435. The second polysilicon structure 425 is extended to connect a gate polysilicon structure 421 which is also a second conductivity type. In addition, a gate metal layer 440 is overlaid on the gate polysilicon structure 421 to reduce the gate resistance. The gate metal layer 440 and the gate metal contact pad 445 may be formed on the same metal layer.

At the same time, as shown in FIG. 5, the gate metal contact pad 445 corresponds to the input terminal IN in FIG. 5, and the gate polysilicon structure 421 corresponds to the gate terminal G in FIG. The first current path is directly connected to the gate polysilicon structure 421 by the gate metal contact pad 445 via the first polysilicon structure 423 and the second polysilicon structure 425. The second current path is directed to the gate polysilicon structure 421 by the gate metal contact pad 445 via the second polysilicon structure 425. Wherein, a first Zener diode ZD3 is formed between the first polysilicon structure 423 and the second polysilicon structure 425, and a second polysilicon structure between the first polysilicon structure 423 and the gate polysilicon structure 421 is formed. 425 is the first resistor R1, and the second polysilicon structure 425 between the gate metal contact pad 445 and the gate polysilicon structure 421 is used as the second resistor R2.

8a and 8b are top and cross-sectional views of a preferred embodiment of the power semiconductor chip integrated with the surge voltage cancellation circuit of FIG. Here, the cross-sectional view shown in Fig. 8b corresponds to the B-B' cross section in Fig. 8a. The figure shows a gate contact structure of a power semiconductor wafer. This gate contact structure is connected to the gate terminal of the power transistor structure. The gate and the left and right sides of the gate contact structure in the figure can be extended to connect the gate polysilicon structure of the power transistor structure to pass the gate voltage signal.

Compared to the embodiments of FIGS. 7a and 7b, the present embodiment forms a third polysilicon between the first polysilicon structure 523 and the second polysilicon structure 525 connected to the gate metal contact pad 545. Structure 527. The first polysilicon structure 523 is a first conductivity type, the second polysilicon structure 525 is also a first conductivity type, and the third polysilicon structure 527 is a second conductivity type. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. The gate metal contact pad 545 is connected to the first polysilicon structure 523 through at least one first plug 533 and to the second polysilicon structure 525 through at least one second plug 535. The second polysilicon structure 525 is extended to connect the gate polysilicon structure 521 which is also of the first conductivity type. In addition, a gate metal layer 540 is overlaid on the gate polysilicon structure 521.

At the same time, as shown in FIG. 3, the gate metal contact pad 545 corresponds to the input terminal IN in FIG. 3, and the gate polysilicon structure 521 corresponds to the gate terminal G in FIG. The first current path is directly connected to the gate polysilicon structure 521 by the gate metal contact pad 545 via the first polysilicon structure 523, the third polysilicon structure 527, and the second polysilicon structure 525. The second current path is directed to the gate polysilicon structure 521 by the gate metal contact pad 545 via the second polysilicon structure 525. Wherein, the first Zener diode ZD1 is formed between the first polysilicon structure 523 and the third polysilicon structure 527, and is connected between the input terminal IN and the gate terminal G, and the third polysilicon structure 527 is A second Zener diode ZD2 is formed between the second polysilicon structure 525 and is connected between the input terminal IN and the gate terminal G, and the second polysilicon structure 527 and the gate polysilicon structure 521 are the second largest. The germanium structure 525 is used as the first resistor R1, and the second polysilicon structure 525 between the gate metal contact pad 545 and the gate polysilicon structure 521 is used as the second resistor R2.

The surge voltage eliminating circuit provided by the invention not only helps to increase the efficiency and reduce the surge voltage, but also is easily integrated into the gate contact structure in the power semiconductor wafer to simplify the external driving circuit and reduce the external driving circuit. cost.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100. . . Drive circuit

Q0. . . Power transistor

R0. . . resistance

200. . . Surge voltage cancellation circuit

IN. . . Input

R1. . . First resistance

R2. . . Second resistance

ZD1, ZD3. . . First Zener diode

ZD2. . . Second Zener diode

G. . . Gate extreme

VIN. . . Square wave drive signal

VGS. . . Gate voltage signal

Q1. . . Power transistor structure

410,510. . . Substrate

421,521. . . Gate polysilicon structure

423,523. . . First polycrystalline structure

425,525. . . Second polycrystalline structure

527. . . Third polycrystalline germanium structure

430,530. . . Interlayer dielectric layer

433,533. . . First plug

435,535. . . Second plug

445,545. . . Gate metal contact pad

440,540. . . Gate metal layer

Figure 1 shows a typical power transistor drive circuit.

Fig. 2 is a waveform diagram showing the square wave drive signal VIN, the gate voltage signal VGS, the source drain voltage VDS, and the drain current ID in the surge voltage cancel circuit of Fig. 1.

Fig. 3 is a circuit diagram showing a preferred embodiment of the surge voltage canceling circuit of the present invention.

Fig. 4 is a view showing a waveform diagram of a square wave drive signal VIN, a gate voltage signal VGS, a source drain voltage VDS, and a drain current ID in the surge voltage eliminating circuit of Fig. 3.

Fig. 5 is a circuit diagram showing another preferred embodiment of the surge voltage canceling circuit of the present invention.

Fig. 6 is a view showing a waveform diagram of a square wave drive signal VIN, a gate voltage signal VGS, a source drain voltage VDS, and a drain current ID in the surge voltage eliminating circuit of Fig. 5.

7a and 7b are top and cross-sectional views of a preferred embodiment of the power semiconductor chip integrated with the surge voltage cancellation circuit of FIG.

8a and 8b are top and cross-sectional views of a preferred embodiment of the power semiconductor chip integrated with the surge voltage cancellation circuit of FIG.

100‧‧‧ drive circuit

200‧‧‧ Surge voltage elimination circuit

IN‧‧‧ input

R1‧‧‧first resistance

R2‧‧‧second resistance

ZD1‧‧‧First Zener diode

ZD2‧‧‧Second Zener diode

G‧‧‧ gate extreme

Q1‧‧‧Power transistor structure

Claims (4)

A power semiconductor wafer having a surge voltage cancellation circuit, comprising: a power transistor structure having a gate terminal; and a gate contact structure comprising: an input terminal; a first current path located at Between the input terminal and the gate terminal; a second current path between the input terminal and the gate terminal; a first resistor located on the first current path; and a second resistor located at the second a resistance of the second resistor is greater than a resistance of the first resistor; and a first Zener diode is located on the first current path and is coupled in the input terminal to the gate terminal The input end is located in a gate metal contact pad, and the gate electrode is located in a gate polysilicon structure, and the gate metal contact pad is located in one of the first first conductivity type adjacent to the first polycrystal. The first Zener diode system is located between the first polycrystalline germanium structure and the second polycrystalline germanium structure, and the second polycrystalline structure is over the second polycrystalline germanium structure.矽 structure is extended to connect An extremely polycrystalline germanium structure, the gate metal contact pad is electrically connected to the first polysilicon structure through at least one first plug, and electrically connected to the second polysilicon structure through at least one second plug The second polysilicon structure between the first polysilicon structure and the gate polysilicon structure serves as the first resistor, and the second polysilicon structure between the second plug and the gate polysilicon structure Used as the second resistor. A power semiconductor wafer having a surge voltage canceling circuit according to the first aspect of the invention, wherein the first polysilicon structure, the second polysilicon structure and the gate polysilicon structure are in the same polysilicon layer And, the second polysilicon structure surrounds the first polysilicon structure. A power semiconductor wafer having a surge voltage canceling circuit according to the first aspect of the invention, wherein the gate polysilicon structure is covered with a gate metal layer, and the gate metal layer and the gate metal contact pad are located; The same metal layer. A power semiconductor wafer having a surge voltage canceling circuit as claimed in claim 1, wherein the power transistor structure is a metal oxide half field effect transistor (MOSFET) structure.