TWI444739B - Pixel array substrate and manufacturing method thereof, and display device and manufacturing method thereof - Google Patents

Description

Pixel array substrate, manufacturing method thereof, display and manufacturing method thereof

The present invention relates to a pixel array substrate, a method of manufacturing the same, a display and a method of fabricating the same, and more particularly to a pixel array substrate having bumps, a method of fabricating the same, a display, and a method of fabricating the same.

The conventional pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of capacitor structures. The scan lines and the data lines define a plurality of pixel regions. Each active component is located in a corresponding pixel area and is connected to a corresponding scan line and a corresponding data line. Each capacitor structure is located in a corresponding pixel region.

As the pixel becomes smaller and smaller, in order to maintain a certain aperture ratio, the scan line, the data line, the active component, and the capacitor structure also need to be reduced in size, but the smaller the line size, the higher the resistance value of the line. As a result, the signal attenuation is too fast, which in turn affects the overall power consumption. However, if the dimensions of the scan lines, data lines, active components, and capacitor structures are maintained, the aperture ratio of the pixel array substrate may be lowered, and the industrial competitiveness may be lost.

The invention relates to a pixel array substrate, a manufacturing method thereof and a display and a manufacturing method thereof. In an embodiment, a certain aperture ratio can be obtained under the pixel area of the pixel array substrate to improve the display quality. In another embodiment, the aperture ratio can be increased to improve the display quality without changing the area of the pixel area of the pixel array substrate.

According to an embodiment of the present invention, a pixel array substrate is proposed. The pixel array substrate comprises a light transmissive substrate and a pixel structure layer. The light transmissive substrate includes a bump layer. The pixel structure layer is formed on the light transmissive substrate. The pixel structure layer includes a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of capacitor structures. The scan lines and the data lines define a plurality of pixel regions. Each active component is connected to a corresponding scan line and a corresponding data line, and each active component is located in a corresponding pixel area. Each capacitor structure is located in a corresponding pixel region. The scan lines, the data lines, the active components, and at least one of the capacitor structures are formed on the bump layer.

According to an embodiment of the invention, a display is presented. The display includes a display panel and a housing. The display panel includes the above pixel array substrate. The outer casing surrounds the display panel.

According to an embodiment of the present invention, a method of fabricating a pixel array substrate is provided. The manufacturing method includes the following steps. Providing a transparent substrate; forming a bump layer on the transparent substrate; and forming a pixel structure layer on the transparent substrate, wherein the pixel structure layer comprises a plurality of scan lines, a plurality of data lines, and a plurality of active The component and the plurality of capacitor structures, the scan lines and the data lines define a plurality of pixel regions, and each active component is connected to the corresponding scan line and the corresponding data line and is located in the corresponding pixel region, and each capacitor structure And being located in the corresponding pixel region, wherein at least one of the scan lines, the data lines, the active components, and the capacitor structures are formed on the bump layer.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Please refer to FIG. 1 , which is a partial top view of a pixel array substrate according to an embodiment of the invention. The pixel array substrate 100 includes a light transmissive substrate 110 and a pixel structure layer 120. The pixel structure layer 120 is formed on the transparent substrate 110, for example, on the upper surface 110u of the transparent substrate 110 (shown in FIG. 2A).

The pixel structure layer 120 includes a plurality of data lines 121, a plurality of scan lines 122, a plurality of active elements 123, a plurality of capacitor structures 124, and a plurality of pixel electrodes 125. The data lines 121 and the scan lines 122 define a plurality of pixel areas PA. Each active component 123 is connected to the corresponding data line 121 and the corresponding scan line 122, and is located in the corresponding pixel area PA.

Referring to Figs. 2A and 2B, Fig. 2A is a cross-sectional view taken along line 2A-2A' in Fig. 1, and Fig. 2B is a cross-sectional view taken along line 2B-2B' in Fig. 1. The transparent substrate 110 includes a bump layer 111, wherein the bump layer 111 may be formed by a photolithography etching, a sandblasting process, or a method of coating a glass paste (Frit). The bump layer 111 is a structure in which one of the transparent substrates 110 is formed. In one embodiment, the material of the transparent substrate 110 is the same as the material of the bump layer 111.

The bump layer 111 has opposite two bump sidewalls 111s1 and 111s2. The bump layer 111 protrudes from the upper surface 110u of the transparent substrate 110. The bump sidewalls 111s1 and 111s2 of the bump layer 111 are, for example, planar walls, and the planar walls may be planar inclined walls that are inclined with respect to the upper surface 110u. In another embodiment, the bump sidewalls 111s1 and 111s2 may also be curved walls (described in FIG. 7); or one of the bump sidewalls 111s1 and 111s2 is a planar wall, and the bump sidewalls 111s1 and 111s2 are another one. The surface is a curved wall.

As shown in FIG. 2A, the angle A1 between the bump sidewalls 111s1 of the bump layer 111 and the upper surface 110u of the transparent substrate 110 is at least greater than 90 degrees. The angle A2 between the bump sidewall 111s2 of the bump layer 111 and the upper surface 110u of the transparent substrate 110 is at least greater than 90 degrees. The bump sidewall 111s1 is opposite to the bump sidewall 111s2. The angle A1 and the angle A2 may be equal or different. In one embodiment, the included angle A1 is preferably, but not limited to, between 130 and 150 degrees, and the included angle A2 is preferably, but not limited to, between 130 and 150 degrees. The above-mentioned included angles A1 and A2 refer to an angle between the bump side wall 111s1 and the light-transmitting substrate 110 which is not covered by the upper surface 110u of the bump layer 111.

As shown in FIG. 2A, since the bump layer 111 extends in a direction perpendicular to the upper surface 110u of the transparent substrate 110, the structure formed on the bump layer 111 may be perpendicular to the upper surface 110u of the transparent substrate 110. The extension (for example, extending in the vertical direction) can increase the extension area of the structure formed on the bump layer 111 without occupying a space along the extending direction of the upper surface 110u (for example, in the horizontal direction).

As shown in FIG. 2A, the bump layer 111 has an upper surface 111u, and the distance H1 between the upper surface 111u of the bump layer 111 and the upper surface 110u of the transparent substrate 110 is greater than 0, and the embodiment of the present invention has a pitch H1. There are no restrictions on the limits.

At least one of the data lines 121, the scan lines 122, the active elements 123, and the capacitor structures 124 are formed on the bump layer 111, for example, at least on the bump sidewalls 111s1 and/or 111s2. . In one embodiment, all of the data lines 121, all of the scan lines 122, all of the active elements 123, and all of the capacitor structures 124 are formed on the bump layer 111; or, the groups of the data lines 121, A group of scan lines 122, a group of the active elements 123, and at least one group of the plurality of capacitor structures 124 are formed on the bump layer 111; or one of the data lines 121, the One of the scan lines 122, one of the active elements 123, and one of the capacitor structures 124 are formed on the bump layer 111. The following is further explained.

As shown in FIG. 2A, since the active device 123 is formed on the bump layer 111, even if the size of the active device 123 projected on the upper surface 110u of the transparent substrate 110 is reduced, the original can be conformed (the bump-free layer 111 is not provided). Design) The area design value of the active component 123. When the size of the active element 123 is reduced, the light-transmitting area is increased, thereby increasing the aperture ratio of the pixel area PA; or, in the case of reducing the size of the active element 123, the overall area of the pixel area PA is reduced, and further The size of the pixel array substrate 100 is reduced.

As shown in FIG. 2A, the active element 123 includes a semiconductor layer 123a, and a semiconductor layer 123a is formed on the bump layer 111.

The semiconductor layer 123a includes a first sub-semiconductor layer 123a1, a second sub-semiconductor layer 123a2, a third sub-semiconductor layer 123a3, a fourth sub-semiconductor layer 123a4, and a fifth sub-semiconductor layer 123a5. The first sub-semiconductor layer 123a1 is formed on the upper surface 111u of the bump layer 111 of the bump layer 111, and the second sub-semiconductor layer 123a2 and the third sub-semiconductor layer 123a3 are respectively formed on the bump sidewalls 111s1 and 111s2 of the bump layer 111. The fourth sub-semiconductor layer 123a4 and the fifth sub-semiconductor layer 123a5 are formed on the upper surface 110u of the transparent substrate 110. In one embodiment, the semiconductor layer 123a may also omit at least one of the fourth sub-semiconductor layer 123a4 and the fifth sub-semiconductor layer 123a5.

In this embodiment, the semiconductor layer 123a is formed on the bump sidewalls 111s1 and 111s2 of the bump layer 111, thus increasing the extension area of the semiconductor layer 123a. In detail, if the bump layer 111 is absent, the area of the second sub-semiconductor layer 123a2 is limited to the range of the projection width W12 of FIG. 2A, and the area of the third sub-semiconductor layer 123a3 is limited to the projection width W13 of FIG. 2A. The scope. In contrast, in the present embodiment, since the extending areas of the bump side walls 111s1 and 111s2 of the bump layer 111 are larger than the area of the projection width W12 and the projection width W13, the extended area of the semiconductor layer 123a can be increased.

The width W1 of the channel region 168 is defined as the width of the overlapping region of the semiconductor layer 123a and the gate 123g projected on the upper surface 110u of the transparent substrate 110, which includes the projection width W11 of the first sub-semiconductor layer 123a1 and the second sub-semiconductor layer 123a2. The projection width W12, the projection width W13 of the third sub-semiconductor layer 123a3, the projection width W14 of the fourth sub-semiconductor layer 123a4, and the projection width W15 of the fifth sub-semiconductor layer 123a5 are summed. The actual length L1 of the channel region 168 extending along the surface of the light-transmitting substrate 110 is as follows (1).

Wherein, the width W12 and the width W13 may be equal or different, and the width W14 and the width W15 may be equal or different. In an embodiment, W14 or W15 may also be omitted, that is, the width of W14 or W15 may be zero.

The angle A1 is an angle between the bump sidewall 111s1 of the bump layer 111 and the upper surface 110u of the transparent substrate 110, which is at least greater than 90 degrees. The angle A2 is an angle between the bump sidewall 111s2 of the bump layer 111 and the upper surface 110u of the transparent substrate 110, which is at least greater than 90 degrees. The angle A1 and the angle A2 may be equal or different. In one embodiment, the included angle A1 is preferably, but not limited to, between 130 and 150 degrees, and the included angle A2 is preferably, but not limited to, between 130 and 150 degrees.

As shown in FIG. 2A, the active device 123 further includes a gate 123g, a first insulating layer 123p1, a dielectric layer 123p2, a protective layer 123p3, a drain 123d, and a source 123s. The first insulating layer 123p1 covers the semiconductor layer 123a, the gate 123g is formed on the first insulating layer 123p1, the dielectric layer 123p2 covers the gate 123g, and the drain 123d and the source 123s pass through the via of the first insulating layer 123p1 and the dielectric The via hole of the layer 123p2 is connected to the semiconductor layer 123a. The protective layer 123p3 covers the drain 123d and the source 123s. The pixel electrode 125 is connected to the drain electrode 123d through a through hole of the protective layer 123p3.

As shown in FIG. 2A, since the semiconductor layer 123a is formed on the bump layer 111 to form a protruding structure, the first insulating layer 123p1, the dielectric layer 123p2, the protective layer 123p3, and the pixel electrode 125 formed on the semiconductor layer 123a are formed. A protruding structure corresponding to the contour of the semiconductor layer 123a is also formed.

As shown in FIG. 2B, since the semiconductor layer 123a is formed on the bump layer 111 to form a protruding structure, the gate 123g formed on the semiconductor layer 123a also constitutes a protruding structure corresponding to the outline of the semiconductor layer 123a. In detail, the gate 123g may be formed on the first insulating layer 123p1 along the extending direction of the bump sidewalls 111s1 and 111s2 along the bump layer 111, thereby increasing the extended area of the gate 123g, thereby raising the gate 123g. Electrical quality. In this way, even if the size of the active element 123 projected on the upper surface 110u of the bump layer 111 is reduced, the area design value of the original (no bump layer 111 design) gate 123g can be maintained. When the size of the active element 123 is reduced, the light transmitting area is increased, and the aperture ratio of the pixel area PA can be increased.

Please refer to FIG. 2C, which is a cross-sectional view taken along line 2C-2C' in FIG. 1, and FIG. 2C shows only scanning line 122 and transparent substrate 110. A scan line 122 may be formed on the bump layer 111. In addition, the geometry of the scan line 122 can be similar to the geometry of the semiconductor layer 123a, and will not be described again.

In another embodiment (not shown), the data line 121 may also be formed on the bump layer 111. In addition, the geometry of the data line 121 can be similar to the geometry of the semiconductor layer 123a or the scan line 122, and will not be described again.

Referring to Fig. 2D, a cross-sectional view taken along the direction 2D-2D' in Fig. 1 is shown. Each capacitor structure 124 is located in the corresponding pixel area PA and is formed on the bump layer 111.

Each of the capacitor structures 124 includes a capacitor lower electrode 124b, a capacitor upper electrode, and a dielectric layer 123p2. The dielectric layer 123p2 may be formed between the capacitor lower electrode 124b and the capacitor upper electrode (for example, the pixel electrode 125). The upper electrode of the capacitor is, for example, a light transmissive pixel electrode 125 or another opaque metal electrode. The capacitor lower electrode 124b is formed on the bump sidewalls 111s1 and 111s2 of the bump layer 111. In one embodiment, the capacitor lower electrode 124b can be formed in the same process as the gate 123g, but the invention is not limited thereto.

The capacitor lower electrode 124b is formed on the bump layer 111 to form a protruding structure, so that the extended area of the capacitor structure 124 can be increased to occupy the dielectric value without occupying the space in the extending direction of the upper surface 110u of the transparent substrate 110. . In addition, since the capacitor lower electrode 124b is formed on the bump layer 111 to form a protruding structure, the dielectric layer 123p2 formed on the capacitor lower electrode 124b and the capacitor upper electrode (for example, the pixel electrode 125) also form a corresponding protruding structure. .

As shown in Fig. 2D, in the present embodiment, the dielectric layer 123p2 covers the gate 123g. In another embodiment, the first insulating layer 123p1 may cover the capacitor lower electrode 124b, and the dielectric layer 123p2 covers the first insulating layer 123p1, such that between the capacitor lower electrode 124b and the capacitor upper electrode (for example, the pixel electrode 125) The first insulating layer 123p1 and the dielectric layer 123p2 may be sandwiched.

Although the bump layer 111 of the above embodiment is exemplified by having two opposite bump sidewalls 111s1 and 111s2 at the same time, in one embodiment, the bump layer 111 may omit one of the bump sidewalls 111s1 and 111s2. As a result, at least one of the data lines 121, the scan lines 122, the active elements 123, and the capacitor structures 124 are formed on one of the bump sidewalls 111s1 and 111s2 of the bump layer 111. The following is an example.

Referring to FIG. 3, a partial cross-sectional view of a pixel array substrate in accordance with another embodiment of the present invention is shown. In the pixel structure layer 220 of the pixel array substrate 200, the bump layer 111 of the light-transmitting substrate 110 may omit the sidewall 111s2. As a result, the semiconductor layer 123a can omit the corresponding third sub-semiconductor layer 123a3 and fifth sub-semiconductor layer 123a5 (123a3 and 123a5 are shown in FIG. 2A). In this embodiment, the semiconductor layer 123a may also omit a portion of the first sub-semiconductor layer 123a1, but may also retain the complete first sub-semiconductor layer 123a1. In one embodiment, the fourth sub-semiconductor layer 123a4 of FIG. 3 may be omitted and only the first sub-semiconductor layer 123a1 and the second sub-semiconductor layer 123a2 may be left. In another embodiment, the bump layer 111 may also omit the bump sidewall 111s1, and the semiconductor layer 123a correspondingly omits the second sub-semiconductor layer 123a2 and the fourth sub-semiconductor layer 123a4 and at least retains the first sub-semiconductor layer 123a1 and the third layer. Sub-semiconductor layer 123a3.

Referring to FIG. 4, a partial top view of a pixel array substrate in accordance with still another embodiment of the present invention is shown. The pixel array substrate 300 includes a light transmissive substrate 110 and a pixel structure layer 320. The pixel structure layer 320 is formed on the transparent substrate 110, for example, on the upper surface 110u of the transparent substrate 110 (shown in FIG. 6).

The pixel structure layer 320 includes a plurality of data lines 121, a plurality of scan lines 122, a plurality of active elements 323, a plurality of capacitor structures 324, and a plurality of pixel electrodes 325. The data lines 121 and the scan lines 122 define a plurality of pixel areas PA. Each active component 323 is connected to the corresponding data line 121 and the corresponding scan line 122, and each active component 323 is located in the corresponding pixel area PA.

Please refer to Fig. 5, which is a cross-sectional view taken along line 5-5' in Fig. 4. In the pixel array substrate 300, the active element 323 includes a gate 323g formed on the bump layer 111. Since the active element 323 is formed on the bump layer 111, even if the size of the active surface 323 projected on the upper surface 110u of the bump layer 111 is reduced, the area design of the gate 323g (the design of the bumpless layer 111) can be met. value. When the size of the active element 323 is reduced, the light transmitting area is increased, and the aperture ratio of the pixel area PA can be increased.

In this embodiment, the width W2 of the channel region 368 of the active device 323 and the actual length extending along the surface of the transparent substrate 110 are calculated similarly to the width W1 of the channel region 168 of the above embodiment and along the transparent substrate 110. The calculation method of the actual length L1 of the surface extension (refer to the above formula (1)).

As shown in FIG. 5, the active device 323 further includes a drain 323d, a source 323s, a semiconductor layer 323a, an insulating layer 323p1, a protective layer 323p2, a pixel electrode 325, and a capacitor structure 324 (the capacitor structure 324 is shown in FIG. 4). ).

As shown in Fig. 5, the insulating layer 323p1 is formed on the gate 323g to constitute a protruding structure corresponding to the outline of the gate 323g, and the semiconductor layer 323a is formed on the insulating layer 323p1 to constitute a protruding structure corresponding to the outline of the insulating layer 323p1. The drain 323d and the source 323s are formed on the semiconductor layer 323a to constitute a protruding structure corresponding to the outline of the semiconductor layer 323a. The protective layer 323p2 covers the drain 323d, the source 323s, and the semiconductor layer 323a, and constitutes a protruding structure corresponding to the outline of the drain 323d and the source 323s. The pixel electrode 325 is formed on the protective layer 323p2 to constitute a protruding structure corresponding to the outline of the protective layer 323p2.

In one embodiment, the capacitor structure 324 can also be formed on the bump layer 111, which is similar to the structure of the 2D diagram, and will not be described again.

Although the bump sidewalls 111s1 and 111s2 of the bump layer 111 of the above embodiment are exemplified by a planar wall, in one embodiment, the bump sidewalls 111s1 and 111s2 of the bump layer 111 may be curved walls, as explained below.

Please refer to FIG. 6 , which is a cross-sectional view showing a bump layer of another embodiment. The profile of the bump sidewall 411s of the bump layer 411 is at least a portion of a cylindrical profile or an elliptical profile.

The at least one of the data lines 121, the scan lines 122, the active elements 123, and the capacitor structures 124 may be extended in a direction perpendicular to the upper surface 410u of the transparent substrate 410. Extending in a direction away from the upper surface 410u of the transparent substrate 410 (i.e., extending in the vertical direction), the extended area can be increased without occupying a space along the extending direction of the upper surface 110u.

Taking the active component formed on the bump layer 411 as an example, the width W3 of the channel region 468 of the active device is defined as the width of the overlapping region of the semiconductor layer 423a and the gate (not shown) projected on the upper surface 410u of the transparent substrate 410. Such as the sum of the projection widths W31, W32 and W33. The actual length L3 of the channel region 468 extending along the surface of the light-transmitting substrate 110 is as follows (2).

Here, the section length L3 is calculated in the case where the cross-sectional profile of the bump layer 411 is exemplified by a semicircle. The projection widths W31, W32, and W33 are projected widths of the bump layer 411 projected on the upper surface 410u of the transparent substrate 410. When the profile of the bump layer 411 is other shapes, those skilled in the art can calculate the length of the profile according to the geometric principle. In an embodiment, the projection width W32 or W33 may be omitted, that is, the value of the projection width W32 or W33 may be zero.

Please refer to FIG. 7 , which shows an external view of a display according to an embodiment of the invention. The display 500 includes a display panel 510 and a housing 520. The outer casing 520 surrounds the display panel 510 to protect the display panel 510. The display panel 510 may include a color filter, a liquid crystal layer, and the above pixel array substrate 100, 200 or 300, and the liquid crystal layer may be located between the color filter and the pixel array substrate.

In one embodiment, the display panel 510 can be an active matrix organic light emitting diode (AMOLED) panel, which can include a glass cover, an organic light emitting layer, and the above pixel array substrate 100, 200 or 300, wherein the organic light emitting layer can be located Between the glass cover and the pixel array substrate.

Hereinafter, a method of manufacturing a pixel array substrate according to an embodiment of the present invention will be described. The method of manufacturing the pixel array substrate of Fig. 1 will be described as an example.

Please refer to FIGS. 8A to 8C for a manufacturing process diagram of the pixel array substrate of FIG. 1.

As shown in FIG. 8A, a light-transmitting substrate 110 is provided.

Then, a bump layer 111 is formed on the light-transmitting substrate 110. This step can be completed by a lithography process, as explained below.

As shown in FIG. 8B, a patterned photoresist layer 130 is formed on the light-transmissive substrate 110. The method of patterning the photoresist layer 130 includes the following steps. First, a photoresist material is coated on the transparent substrate 110; then, the photoresist material is exposed using a photomask process; then, the exposed photoresist material is developed to form a patterned photoresist layer 130.

As shown in Fig. 8C, a bump layer 111 is formed. The method of forming the bump layer 111 is, for example, etching. After the bump layer 111 is formed, the patterned photoresist layer 130 is removed. Since the bump layer 111 is formed in the light-transmitting substrate 110 by an etching method, the bump layer 111 is a structure integrally formed in the light-transmitting substrate 110. Further, the overlap C1 of the bump layer 111 and the transparent substrate 110 may have no significant boundary.

Then, the pixel structure layer 120 is formed on the light-transmitting substrate 110 to form the pixel array substrate 100. In other embodiments, the pixel structure layer 220 or 320 may also be formed on the transparent substrate 110.

In one embodiment, after the pixel array substrate 100 is formed, a color filter (not shown) may be disposed corresponding to the pixel array substrate 100; then, the corresponding pixel array substrate 100 and the color filter form a liquid crystal layer (not The pixel array substrate 100, the color filter, and the liquid crystal layer are formed into the display panel 510 of FIG. In one embodiment, a liquid crystal layer may be formed between the pixel array substrate 100 and the color filter, which is not intended to limit the embodiment of the present invention; then, the display panel 510 is fixed by the outer casing 520 to form the seventh figure. Display 500.

In another embodiment, after the pixel array substrate 100 is formed, it can correspond to The pixel array substrate 100 is provided with a glass cover (not shown); then, the corresponding pixel array substrate 100 and the glass cover form an organic light-emitting layer (not shown), so that the pixel array substrate 100, the glass cover, and the organic light-emitting layer The layer forms the display panel 510 of FIG. 7; then, the display panel 510 is fixed with the outer casing 520 to form the display 500 of FIG. In another embodiment, the organic light-emitting layer may also be formed between the pixel array substrate 100 and the glass cover, which is not intended to limit the embodiments of the present invention.

The following is a description of another manufacturing method for forming a bump layer.

Please refer to FIGS. 9A to 9B, which illustrate a manufacturing process diagram of the bump layer of FIG. 6.

As shown in Fig. 9A, a colloid 411' is formed on the light-transmitting substrate 410. The method of forming the colloid 411' is, for example, a coating or dropping method. The colloid 411' is the same material as the transparent substrate 410. In one embodiment, the transparent substrate 410 is a glass substrate, and the colloid 411' is a glass paste.

As shown in Fig. 9B, the colloid 411' is baked at about 450 degrees Celsius to shape the outer shape of the bump layer 411.

Then, the bump layer 411 is sintered by laser to cure the bump layer 411. Among them, the temperature of laser sintering can be higher than 600 degrees Celsius. In this step, the bump layer 411 is completely combined with the transparent substrate 410, and is formed in the same shape as the transparent substrate 410. Further, the overlap C1 of the bump layer 411 and the transparent substrate 410 may have no significant boundary.

The pixel array substrate of the above embodiment of the present invention, the manufacturing method thereof, the display and the manufacturing method thereof can increase the extension area of the structure formed on the bump layer by the design of the bump layer. In this way, a certain aperture ratio can be maintained to reduce the display quality under the pixel area of the pixel array substrate, or the aperture ratio can be increased without changing the pixel area of the pixel array substrate. Display quality.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300. . . Pixel array substrate

110, 410. . . Light transmissive substrate

111, 411. . . Bump layer

111s1, 111s2, 411s. . . Bump side wall

110u, 111u, 410u. . . Upper surface

120, 220, 320. . . Pixel structure layer

121. . . Data line

122. . . Scanning line

123, 323. . . Active component

123a, 323a, 423a. . . Semiconductor layer

123a1. . . First sub-semiconductor

123a2. . . Second sub-semiconductor

123a3. . . Third sub-semiconductor

123a4. . . Fourth sub-semiconductor

123a5. . . Fifth sub-semiconductor layer

123d, 323d. . . Bungee

123g, 323g. . . Gate

123s, 323s. . . Source

123p1. . . First insulating layer

123p2. . . Dielectric layer

123p3, 323p2. . . The protective layer

124, 324. . . Capacitor structure

124b. . . Capacitor lower electrode

125, 325. . . Pixel electrode

130. . . Patterned photoresist layer

168, 368, 468. . . Channel area

323p1. . . Insulation

411'. . . colloid

500. . . monitor

510. . . Display panel

520. . . shell

A1, A2. . . Angle

H1. . . spacing

PA. . . Graphic area

W1, W11, W12, W13, W14, W15, W2, W3, W31, W32, W33. . . width

1 is a partial plan view of a pixel array substrate in accordance with an embodiment of the present invention.

Fig. 2A is a cross-sectional view taken along line 2A-2A' in Fig. 1.

Fig. 2B is a cross-sectional view taken along line 2B-2B' in Fig. 1.

Fig. 2C is a cross-sectional view taken along line 2C-2C' in Fig. 1.

Fig. 2D is a cross-sectional view taken along line 2D-2D' in Fig. 1.

3 is a partial cross-sectional view of a pixel array substrate in accordance with another embodiment of the present invention.

4 is a partial plan view of a pixel array substrate in accordance with still another embodiment of the present invention.

Fig. 5 is a cross-sectional view taken along line 5-5' in Fig. 4.

FIG. 6 is a cross-sectional view showing a bump layer of another embodiment.

FIG. 7 is a perspective view of a display according to an embodiment of the invention.

8A to 8C are views showing a manufacturing process of the pixel array substrate of Fig. 1.

9A to 9B are views showing a manufacturing process of the bump layer of Fig. 6.

110. . . Light transmissive substrate

111. . . Bump layer

111s1, 111s2. . . Bump side wall

110u, 111u. . . Upper surface

123. . . Active component

123a. . . Semiconductor layer

123a1. . . First sub-semiconductor

123a2. . . Second sub-semiconductor

123a3. . . Third sub-semiconductor

123a4. . . Fourth sub-semiconductor

123a5. . . Fifth sub-semiconductor layer

123d. . . Bungee

123g. . . Gate

123s. . . Source

123p1. . . First insulating layer

123p2. . . Dielectric layer

123p3. . . The protective layer

125. . . Pixel electrode

168. . . Channel area

A1, A2. . . Angle

H1. . . spacing

W1, W11, W12, W13, W14, W15. . . width

Claims (18)

A pixel array substrate comprising: a light transmissive substrate comprising a bump layer; and a pixel structure layer formed on the light transmissive substrate, the pixel structure layer comprising: a plurality of scan lines; a plurality of data lines The scan lines and the data lines define a plurality of pixel regions, a plurality of active components, each of the active components being connected to the corresponding scan line and the corresponding data line, wherein each active component is located in the corresponding pixel And a plurality of capacitor structures, each of the capacitor structures being located in the corresponding pixel region; wherein at least one of the scan lines, the data lines, the active elements, and the capacitor structures are formed The light-transmissive substrate has an upper surface, the bump layer protrudes from the upper surface of the transparent substrate and has a bump sidewall, and the bump sidewall of the bump layer and the light-transmitting layer An obtuse angle is formed between the upper surfaces of the substrate. The pixel array substrate of claim 1, wherein the bump layer has a bump sidewall, and the bump sidewall of the bump layer is a planar wall or a curved wall. The pixel array substrate of claim 2, wherein the curved wall has a contour that is at least a portion of a cylindrical contour or an elliptical contour. The pixel array substrate according to claim 1, wherein Each of the active components includes a gate formed on the bump layer. The pixel array substrate of claim 1, wherein each of the active elements comprises: a semiconductor layer formed on the bump layer. The pixel array substrate of claim 1, wherein each of the capacitor structures comprises: a capacitor lower electrode formed on the bump layer; a capacitor upper electrode; and a dielectric layer formed on the capacitor Between the lower electrode and the upper electrode of the capacitor. A display comprising: a display panel comprising a pixel array substrate as claimed in claim 1; and a housing for fixing the display panel. The display of claim 7, wherein the bump layer has a bump sidewall, and the bump sidewall of the bump layer is a planar wall or a curved wall. The display of claim 8, wherein the curved wall has a contour that is at least a portion of a cylindrical contour or an elliptical contour. The display of claim 7, wherein each of the active components comprises: a gate formed on the bump layer. The display of claim 7, wherein each of the active components comprises: A semiconductor layer is formed on the bump layer. The display device of claim 7, wherein each of the capacitor structures comprises: a capacitor lower electrode formed on the bump layer; a capacitor upper electrode; and a dielectric layer formed on the capacitor lower electrode The capacitor is between the electrodes. A method for manufacturing a pixel array substrate, comprising: providing a transparent substrate; forming a bump layer on the transparent substrate; and forming a pixel structure layer on the transparent substrate, wherein the pixel structure layer comprises a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of capacitor structures, wherein the scan lines and the data lines define a plurality of pixel regions, each of the active elements being connected to the corresponding scan line and corresponding The data line is located in the corresponding pixel area, and each of the capacitor structures is located in the corresponding pixel area, wherein the scan lines, the data lines, the active elements, and at least one of the capacitor structures Formed on the bump layer. The manufacturing method of claim 13, wherein the step of forming the bump layer is performed by a lithography process. The manufacturing method of claim 13, wherein the step of forming the bump layer comprises: forming a colloid on the transparent substrate, wherein the colloid is made of the same material as the transparent substrate; baking the colloid And sintering the colloid with a laser. The manufacturing method according to claim 15, wherein the light transmissive substrate is a glass substrate, and the glue system is a glass paste. A method for manufacturing a display, comprising: providing a transparent substrate; forming a bump layer on the transparent substrate; forming a pixel structure layer on the transparent substrate to form a pixel array substrate, wherein the drawing The element structure layer includes a plurality of scan lines, a plurality of data lines, a plurality of active elements, and a plurality of capacitor structures, wherein the scan lines and the data lines define a plurality of pixel regions, and each of the active elements is connected to the corresponding pixel The scan line and the corresponding data line are located in the corresponding pixel area, and the capacitor structures are located in the corresponding pixel area, wherein the scan lines, the data lines, the active components, and the capacitors Forming at least one of the structure on the bump layer, forming the pixel structure layer and the transparent substrate to form a pixel array substrate; setting a color filter corresponding to the pixel array substrate; corresponding to the pixel array substrate And the color filter forms a liquid crystal layer, the pixel array substrate, the color filter and the liquid crystal layer form a display panel; and the display panel is fixed by a casing. A method for manufacturing a display, comprising: providing a transparent substrate; forming a bump layer on the transparent substrate; forming a pixel structure layer on the transparent substrate to form a pixel array substrate, wherein the drawing The prime structure layer includes a plurality of scan lines, a plurality of data lines, a plurality of active components, and a plurality of capacitor structures, and the scan lines and The data lines define a plurality of pixel regions, each active component is connected to the corresponding scan line and the corresponding data line and is located in the corresponding pixel region, and each of the capacitor structures is located in the corresponding pixel region. The at least one of the scan lines, the data lines, the active elements, and the capacitor structures are formed on the bump layer, so that the pixel structure layer and the transparent substrate form a pixel array. a substrate; a glass cover is disposed on the pixel array substrate; an organic light emitting layer is formed on the pixel array substrate and the glass cover, so that the pixel array substrate, the glass cover and the organic light emitting layer form a display a panel; and fixing the display panel with a casing.