TWI443838B - Vertical diode device and diode array - Google Patents

Description

Vertical diode component and diode array

This invention relates to a semiconductor component, and more particularly to a vertical diode component and a diode array.

The development trend of memory components is to develop in small size. Some memory components can be clearly separated into memory itself and selectors, while some memory components combine the two. In general, if the two are separated, it is easier to optimize the memory components. When the two are combined, it is easy to reduce the component size.

A diode element can be utilized as a selector for the memory element. To achieve the minimum area, the diode elements must be a common base structure, but the biggest disadvantage of the common base structure is the large base series resistance. When the memory array is too large, the base series resistance will cause a large voltage drop, which may cause the memory components at the tail end of the array to be inoperable due to the low voltage. To overcome this problem, the size of the memory array can be reduced, but as a result, the size of the entire memory chip can be greatly increased.

In view of the above, the present invention provides a vertical diode element and a diode array composed of such a diode element, which can reduce the base series resistance, which can achieve a small memory element size on the one hand, and another Aspects can hold large memory arrays.

The present invention provides a vertical diode element comprising a substrate having a first conductivity type, a buried metal line, an insulating layer, a contact, a first doped region having a second conductivity type, and having a first conductivity type Second doped region. The buried metal wire is disposed in the substrate. The insulating layer is disposed between the substrate and the buried metal line and exposes a portion of the sidewall of the buried metal line. The contacts are disposed in the substrate and are located on portions of the buried metal lines that are exposed through the insulating layer. The first doped region is disposed in the substrate and is located on one side of the buried metal line, wherein the first doped region is in contact with the contact, and the resistance of the contact is lower than the resistance of the first doped region. The second doped region is disposed in the first doped region, wherein the second doped region is not in contact with the contact.

The invention further provides a diode array comprising a substrate, a plurality of buried metal lines, a plurality of strip-shaped first doped regions, a plurality of insulating layers, a plurality of contacts, and a plurality of block-shaped second doping Miscellaneous area. The buried metal wire is disposed in the substrate. The first doped regions are respectively disposed in the substrate between the buried metal lines. The insulating layer is respectively disposed between the first doped region and the buried metal line, wherein each insulating layer exposes a plurality of portions of one sidewall of the corresponding buried metal line, and the bottom of the first doped region is high At the bottom of the insulation layer. The contacts are disposed in the substrate, wherein each of the buried metal wires is provided with a contact on each portion of the sidewall of the corresponding insulating layer exposed. The second doped regions are respectively disposed in the first doped region corresponding to the contacts, and the second doped regions are not in contact with the contacts. In addition, the conductivity type of the first doping region is different from the conductivity type of the second doping region, and the resistance of the junction is lower than the resistance of the first doping region.

Based on the above, in the diode array composed of the vertical diode element of the present invention, since the buried metal line is connected in parallel with the strip-shaped first doped region, and the low-resistance contact is used to achieve the drainage effect, thereby The problem of excessive series resistance of the first doped region of the diode array can be reduced, and the component performance can be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a top plan view of a diode array according to an embodiment of the invention. Figure 2 is a cross-sectional view taken along line II' of Figure 1. For clarity of illustration, the top view of the present invention does not illustrate the top cladding layer above the buried metal lines.

Referring to FIG. 1 and FIG. 2, the diode array 100 of the present invention includes a substrate 102, a plurality of buried metal lines 104, a plurality of top cladding layers 105, a plurality of strip-shaped first doping regions 106, and a plurality of The insulating layer 108, the plurality of contacts 110, and the plurality of block-shaped second doping regions 112.

The substrate 102 is, for example, a P-type germanium substrate. The buried metal wires 104 are arranged in parallel in the substrate 102. In this embodiment, each of the buried metal lines 104 includes a lower metal line 114 and an upper metal line 116. The lower metal line 114 includes a first metal layer 114a and a first barrier layer 114b at the sidewalls and bottom of the first metal layer. The upper metal line 116 is located on the lower metal line 114. The upper metal line 116 includes a second metal layer 116a and a second barrier layer 116b at the sidewalls and bottom of the second metal layer 116a. In addition, the material of the first metal layer 114a and the second metal layer 116a is, for example, tungsten (W), and the material of the first barrier layer 114b and the second barrier layer 116b is, for example, titanium/titanium nitride (Ti/TiN). .

The top cladding layers 105 are disposed in the substrate 102 and on the upper metal lines 116, respectively. The material of the top cladding layer 105 is, for example, yttrium oxide or a high density plasma oxide (HDP oxide).

The first doping region 106 is, for example, an N-type heavily doped region. The first doped regions 106 are respectively disposed in the substrate 102 between the buried metal lines 104. Further, the bottom surface of the first doping region 106 is higher than the bottom surface of the buried metal wire 104.

The insulating layers 108 are respectively disposed between the substrate 102 and the buried metal lines 104, wherein the insulating layers 108 expose portions of the sidewalls of one of the corresponding buried metal lines 104. The material of the insulating layer 108 is, for example, cerium oxide. Further, the bottom of the first doping region 106 is higher than the bottom of the insulating layer 108.

A contact 110 is disposed on each portion of each of the sidewalls of each of the buried metal lines 104 exposed through the corresponding insulating layer 108. In one embodiment, the contacts 110 on portions of the same sidewall of each of the buried metal lines 104 exposed by the corresponding insulating layer 108 are separated from one another, as shown in the top view of FIG. In another embodiment, the contacts 110 on portions of the same sidewall of each of the buried metal lines 104 exposed by the corresponding insulating layer 108 are connected to each other, as shown in the top view of FIG.

It is particularly noted that the resistance of the contact 110 is lower than the resistance of the first doped region 106. In one embodiment, the material of the contact 110 is, for example, a metal telluride such as titanium silicide (TiSi _x ), nickel telluride (NiSi _x ) or cobalt telluride (CoSi _x ). Further, the upper end of the contact 110 is lower than the surface of the substrate 102, and the lower end of the contact 110 is higher than the bottom surface of the first doped region 106. In an embodiment, the contact 110 is located between the second barrier layer 116b and the first doped region 106, as shown in FIG. In another embodiment (not shown), the lower end of the contact 110 may extend further between the first barrier layer 114b and the first doped region 106.

The second doping region 112 is, for example, a P-type heavily doped region. The second doping regions 112 are respectively disposed in the first doping region 106 corresponding to the contacts 110. In addition, the first doped region 106 is in contact with the contact 110, but the second doped region 112 is not in contact with the contact 110.

The diode array 100 of the present invention is composed of a plurality of vertical diode elements 100'. Each of the vertical diode elements 100' includes a P-type substrate 102, a buried metal line 104, an insulating layer 108, A contact 110, an N-type first doped region 106 as a base, and a P-type second doped region 112 as an emitter. The buried metal wire 104 is disposed in the substrate 102. The insulating layer 108 is disposed between the first doped region 106 and the buried metal line 104 and exposes a portion of the sidewall of the buried metal line 104. The contact 110 is disposed in the substrate 102 and is located on a portion of the buried metal line 104 that is exposed through the insulating layer 108. The first doped region 106 is disposed in the substrate 102 and is located on one side of the buried metal line 104. The first doped region 106 is in contact with the contact 110, and the resistance of the contact 110 is lower than the first doped region. The resistance of 106. The second doping region 112 is disposed in the first doping region 106 , wherein the second doping region 112 is not in contact with the contact 110 .

It is particularly noted that the buried metal line 104 is connected in parallel with the strip-shaped first doping region 106, and the low-resistance contact 110 is used to achieve the drainage effect, thereby reducing the first doping of the diode array 100. The problem of excessive series resistance of the miscellaneous region 106 is excessive.

In the above embodiment, the center 112' of each of the second doping regions 112 is located on the center line 106' of the corresponding first doping region 106, as shown in FIGS. However, the invention is not limited thereto. In another embodiment, the center 112' of each of the second doping regions 112 may also be located on the side of the center line 106' of the corresponding first doping region 106 away from the contact 110, as shown in FIGS. 4-6. . Specifically, in order to avoid contact between the second doping region 112 and the contact 110 due to poor alignment in the process of forming the second doping region 112, the center 112' of each of the second doping regions 112 is located. The side of the centerline 106' of the corresponding first doped region 106 that is remote from the junction 110 is advantageous.

In the above embodiments, the P-type substrate, the N-type base (ie, the first doped region) and the P-type emitter (ie, the second doped region) are taken as an example, but the present invention does not This is limited. Those of ordinary skill in the art will appreciate that configurations can be made to form N-type substrates, P-type bases, and N-type emitters.

Hereinafter, a method of forming the diode array of the present invention will be described by taking the structure of FIG. 2 as an example. 2A to 2E are schematic cross-sectional views showing a method of forming a diode array according to an embodiment of the invention.

Referring to FIG. 2A, a doped region is formed in the substrate 102. Next, a patterned mask layer 202 is formed on the substrate 102. The material of the patterned mask layer 202 is, for example, tantalum nitride, and its formation method is, for example, chemical vapor deposition. Then, a plurality of trenches 204 are formed in the substrate 102 by patterning the mask layer 202 as an etch mask. The trench 204 divides the doped region into a plurality of first doped regions 106.

Thereafter, an insulating layer 206 is formed on the surface of the patterned mask layer 202 and the trench 204. The material of the insulating layer 206 is, for example, cerium oxide, and the forming method thereof is, for example, a chemical vapor deposition method. Next, a lower metal line 114 is formed in the trench 204. The lower metal line 114 includes a first metal layer 114a and a first barrier layer 114b at the sidewalls and bottom of the first metal layer. The material of the first metal layer 114a is, for example, tungsten (W), and the material of the first barrier layer 114b is, for example, titanium/titanium nitride (Ti/TiN). The method of forming the first metal layer 114a and the first barrier layer 114b is, for example, performing a chemical vapor deposition process and then performing an etch back process. Further, the surface of the lower metal line 114 is lower than the surface of the substrate 102. Next, a polysilicon layer 208 is conformally formed on the insulating layer 206 and the lower metal line 114.

Then, referring to FIG. 2B, the substrate 102 is subjected to a tilt ion implantation process 210 such that one side of the trench 204 (as shown on the right side of FIG. 2B) is ion doped, but the other side (as shown on the left side of FIG. 2B). Not doped by ions. The dopant is, for example, boron or boron fluoride ion (BF ₂ ⁺ ), and the implantation angle is, for example, 10 to 30 degrees. Since the etching selectivity ratio of the doped polysilicon layer 208 to the undoped polysilicon layer 208 is different, an etching process can be performed to remove the undoped polysilicon layer 208 (as shown by the broken line in FIG. 2B). ).

Thereafter, referring to FIG. 2C, the insulating layer 206 that is not covered by the polysilicon layer 208 is removed. Following, the polysilicon layer 208 is removed. The above removal step is, for example, an etching process.

Next, referring to FIG. 2D, an upper metal line 116 is formed on the lower metal line 114 in the trench 204. The upper metal line 116 includes a second metal layer 116a and a second barrier layer 116b at the sidewalls and bottom of the second metal layer 116a. The material of the second metal layer 116a is, for example, tungsten (W), and the material of the second barrier layer 116b is, for example, titanium/titanium nitride (Ti/TiN). The method of forming the second metal layer 116a and the second barrier layer 116b is, for example, performing a chemical vapor deposition process and then performing an etch back process. Further, the surface of the upper metal line 116 is lower than the surface of the substrate 102. In this embodiment, the lower metal line 114 and the upper metal line 116 form the buried metal layer 104.

Then, an annealing process is performed on the substrate 102. Since one side of the second barrier layer 116b (such as the left side of FIG. 2C) is in direct contact with the substrate 102, the junction between the second barrier layer 116b and the substrate 102 forms a contact of the metal telluride due to the annealing process. 110. In this embodiment, the material of the substrate 102 is tantalum, and the material of the second barrier layer 116b is titanium/titanium nitride (Ti/TiN), so the material of the contact 110 formed is titanium telluride (TiSi _x ). However, the material of the contact 110 of the present invention is not limited thereto, and the material may be determined according to the buried metal wire, as long as a low resistance gold half junction is formed at the joint.

Next, referring to FIG. 2E, the trench 204 is filled with a dielectric layer 212. The method of forming the dielectric layer 212 is, for example, a chemical vapor deposition process followed by a chemical mechanical polishing process. Then, the patterned mask layer 202 is removed, and a spacer 214 is formed on the double side walls of the dielectric layer 212. Thereafter, a plurality of photoresist layers perpendicular to the buried metal lines 104 are formed on the substrate 102 (not shown in this cross section). The gap between the spacer 214 and the photoresist layer defines the region where the second doped region 112 is to be formed. Then, the spacer 214 and the photoresist layer are used as an etch mask to perform an ion implantation process to form the second doping region 112 in the first doping region 106. In this embodiment, since the spacers 214 are formed on the double side walls of the dielectric layer 212, the center of each of the second doping regions 112 is located on the center line of the corresponding first doping region 106.

In particular, the spacers 214 may also be formed only on one side sidewalls (eg, left sidewalls) of the dielectric layer 212 such that the center of the formed second doped region 112 is located in the corresponding first doped region 106. The center line is far from the side of the contact 110.

Next, referring to FIG. 2F, the spacer 214 on the surface of the substrate 102, a portion of the dielectric layer 212 and a portion of the insulating layer 206 are removed to leave the top cladding layer 105 over the upper metal line 116 and left. An insulating layer 108 between the buried metal line 104 and the substrate 102 (or the first doped region 106). So far, the fabrication of the diode array 100 of the present invention has been completed.

In the above embodiment, as shown in FIG. 2D, the upper metal line 116 is formed first, and then an annealing process is performed to form the contact 110 between the second barrier layer 116b and the substrate 102 as an example. However, the invention is not limited thereto. In another embodiment, the contacts 110' may also be formed first to form the upper metal lines 116. 2A' to 2D' are schematic cross-sectional views showing a method of forming a low resistance contact according to another embodiment of the present invention.

First, the intermediate structure of Figure 2C is provided. Next, referring to FIG. 2A', a metal layer 120 is formed on the lower metal line 114 in the trench 204. The top of the metal layer 120 is lower than the surface of the substrate 102. The metal layer 120 is, for example, a nickel layer or a cobalt layer. Then, referring to FIG. 2B', the metal layer 120 is subjected to an annealing process to form a contact 110' between the junction between the metal layer 120 and the substrate 102. In this embodiment, the material of the substrate 102 is germanium, and the material of the metal layer 120 is nickel or cobalt, so the material of the contact 110' formed is nickel neodymium (NiSi _x ) or cobalt telluride (CoSi _x ). Thereafter, referring to FIG. 2C', an etching process is performed to remove the unreacted metal layer 120. Next, an upper metal line 116 is formed on the lower metal line 114 in the trench 204. The upper metal line 116 includes a second metal layer 116a and a second barrier layer 116b at the sidewalls and bottom of the second metal layer 116a. Then, the fabrication of the diode array of the present invention can be accomplished with reference to Figures 2E and 2F.

In summary, in the diode array of the present invention, since the buried metal line is connected in parallel with the strip-shaped first doped region, and the low-resistance contact is used to achieve the drainage effect, the diode array can be reduced. The problem of excessive series resistance of the first doped region is to effectively improve the performance of the device.

In addition, the vertical diode component of the present invention can be used as a selector for a double-ended memory (such as a resistive memory or a phase change memory), which can reduce the size of the memory component to a minimum possible area of 4F ² (wherein the process The feature size is F), and the memory component characteristics can be optimized at the same time.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Diode array

100'. . . Vertical diode component

102. . . Base

104. . . Buried metal wire

105. . . Top coating

106. . . First doped region

108. . . Insulation

110, 110'. . . contact

112. . . Second doped region

114. . . Lower metal wire

114a. . . First metal layer

114b. . . First barrier layer

116. . . Upper metal wire

116a. . . Second metal layer

116b. . . Second barrier layer

120‧‧‧metal layer

202‧‧‧ patterned mask layer

204‧‧‧ Ditch

206‧‧‧Insulation

208‧‧‧Polysilicon layer

210‧‧‧ oblique ion implantation process

212‧‧‧ dielectric layer

214‧‧‧ spacer

FIG. 1 is a top plan view of a diode array according to an embodiment of the invention.

Figure 2 is a cross-sectional view taken along line II' of Figure 1.

2A to 2F are cross-sectional views showing a method of forming a diode array according to an embodiment of the invention.

2A' to 2D' are schematic cross-sectional views showing a method of forming a low resistance contact according to another embodiment of the present invention.

3 is a top plan view of a diode array according to another embodiment of the invention.

4 is a top plan view of a diode array according to another embodiment of the invention.

Figure 5 is a cross-sectional view taken along line II' of Figure 4;

FIG. 6 is a top plan view of a diode array according to still another embodiment of the present invention.

100. . . Diode array

100'. . . Vertical diode component

102. . . Base

104. . . Buried metal wire

105. . . Top coating

106. . . First doped region

108. . . Insulation

110. . . contact

112. . . Second doped region

114. . . Lower metal wire

114a. . . First metal layer

114b. . . First barrier layer

116. . . Upper metal wire

116a. . . Second metal layer

116b. . . Second barrier layer

Claims (19)

A vertical diode component comprising: a substrate having a first conductivity type; a buried metal wire disposed in the substrate; an insulating layer disposed on the substrate and the buried metal wire And exposing a portion of a sidewall of the buried metal wire; a contact disposed in the substrate and located on the portion of the sidewall of the buried metal wire exposed through the insulating layer; a first doped region of the second conductivity type is disposed in the substrate and located on one side of the buried metal line, wherein the first doped region is in contact with the contact, and the resistance of the contact is low a resistance of the first doped region; and a second doped region having the first conductivity type disposed in the first doped region, wherein the second doped region is not in contact with the contact. The vertical diode element of claim 1, wherein a center of the second doped region is located on a center line of the first doped region. The vertical diode component of claim 1, wherein a center of the second doped region is located on a side of the center line of the first doped region that is away from the contact. The vertical diode component of claim 1, wherein the material of the joint comprises a metal halide. The vertical diode component of claim 1, wherein an upper end of the contact is lower than a surface of the substrate, and a lower end of the contact is higher than a bottom surface of the first doped region. The vertical diode element as described in claim 1 The buried metal wire includes: a lower metal wire including a first metal layer and a first barrier layer at a sidewall and a bottom of the first metal layer; and an upper metal wire located at the lower portion The metal line includes a second metal layer and a second barrier layer on sidewalls and a bottom of the second metal layer, wherein the contact is between the second barrier layer and the first doped region. The vertical diode component of claim 6, further comprising a top cladding disposed in the substrate and located on the upper metal line. The vertical diode component of claim 6, wherein the material of the first metal layer and the second metal layer comprises tungsten, and the material of the first barrier layer and the second barrier layer Includes titanium/titanium nitride. The vertical diode component of claim 1, wherein the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, the second conductive The type is N type. A diode array includes: a substrate; a plurality of buried metal wires disposed in the substrate; and a plurality of strip-shaped first doped regions respectively disposed between the buried metal wires a plurality of insulating layers disposed between the first doped regions and the buried metal wires, wherein each of the insulating layers exposes portions of sidewalls of one of the corresponding buried metal wires, And the bottom of the first doped regions is higher than the bottom of the insulating layers; a plurality of contacts are disposed in the substrate, wherein each of the sidewalls of the buried metal line exposed through the corresponding insulating layer is provided with a contact; a plurality of block-shaped second doped regions Disposed in the first doped regions corresponding to the contacts, and the second doped regions are not in contact with the contacts, wherein the conductive patterns of the first doped regions are different from the The conductivity of the second doped region, and the resistance of the contacts is lower than the resistance of the first doped regions, and wherein the first doped regions are respectively in contact with the contacts. The diode array of claim 10, wherein the center of each of the second doped regions is located on a center line of the corresponding first doped region. The diode array of claim 10, wherein the center of each of the second doped regions is located on a side of the center line of the corresponding first doped region away from the contact. The diode array of claim 10, wherein the material of the contacts comprises a metal halide. The diode array of claim 10, wherein the contacts on the portions of the sidewalls of the buried metal lines exposed by the corresponding insulating layer are separated from each other. The diode array of claim 10, wherein the contacts on the portions of the sidewalls of the buried metal lines exposed by the corresponding insulating layer are connected to each other. A diode array as described in claim 10, wherein The upper ends of the contacts are lower than the surface of the substrate, and the lower ends of the contacts are higher than the bottom surfaces of the first doped regions. The diode array of claim 10, wherein each of the buried metal wires comprises: a lower metal wire, comprising a first metal layer and a first layer located at a sidewall and a bottom of the first metal layer a barrier layer; and an upper metal line on the lower metal line and including a second metal layer and a second barrier layer on the sidewalls and the bottom of the second metal layer, wherein the contact is located in the second resistor Between the barrier layer and the first doped region. The diode array according to claim 17 further includes a plurality of top cladding layers respectively disposed in the substrate and located on the upper metal wires. The diode array of claim 17, wherein the materials of the first metal layer and the second metal layer comprise tungsten, and the first barrier layer and the second barrier layer Materials include titanium/titanium nitride.