TWI441156B - Gate driving apparatus and method for removing residual image - Google Patents

Description

Gate driving device and image sticking elimination method

The present invention is related to the field of display technology, and in particular to a gate driving device and an afterimage removing method.

Liquid crystal display (LCD) is a kind of flat display device, which has the advantages of lightness, thinness, power saving, low radiation, etc., and thus is widely used in various electronic devices.

However, when the liquid crystal display is turned off, the charge stored in the equivalent capacitance of the pixel cannot be quickly discharged, and the charge can be gradually released only by the leakage characteristics of the thin film transistor (TFT) in the pixel. , thus causing a residual image when shutting down.

The invention provides a gate driving device which can eliminate the residual image of the display device when it is turned off.

The present invention further provides an image sticking elimination method which is suitable for use in the aforementioned gate driving device.

The present invention provides a gate driving device that is suitable for use in a display device. The gate driving device includes a first power rail, a second power rail, a first voltage generator, a second voltage generator, a voltage level converter, a gate driver and a switching circuit. The first voltage generator is electrically connected to the first power rail to output the first voltage to the first power rail. The second voltage generator is electrically connected to the second power rail to output the second voltage to the second power rail. The voltage level converter is electrically connected to the first power rail and the second power rail, and is configured to convert the high and low levels of the first clock signal to the levels of the first voltage and the second voltage, respectively, to form A third clock signal. The voltage level converter is further configured to convert the high and low levels of a second clock signal to the levels of the first voltage and the second voltage, respectively, to form a fourth clock signal. The gate driver is electrically connected to the second power rail and the voltage level converter to receive the second voltage, the third clock signal and the fourth clock signal, and accordingly generate at least one gate pulse signal. The switch circuit is electrically connected between the first power rail and the second power rail, and is configured to determine whether to electrically connect the first power rail to the second according to one of the display devices Power rail.

The present invention further provides an image sticking elimination method suitable for use in a display device. The display device has a gate driving device, and the gate driving device has a first power rail, a second power rail, a first voltage generator, a second voltage generator, and a voltage level. Converter with a gate driver. The first voltage generator is electrically connected to the first power rail to output the first voltage to the first power rail. The second voltage generator is electrically connected to the second power rail to output the second voltage to the second power rail. The voltage level converter is electrically connected to the first power rail and the second power rail, and is configured to convert the high and low levels of the first clock signal to the levels of the first voltage and the second voltage, respectively, to form A third clock signal. The voltage level converter is further configured to convert the high and low levels of a second clock signal to the levels of the first voltage and the second voltage, respectively, to form a fourth clock signal. The gate driver is electrically connected to the second power rail and the voltage level converter to receive the second voltage, the third clock signal and the fourth clock signal, and accordingly generate at least one gate pulse signal. The image sticking elimination method comprises the steps of: obtaining a shutdown detection signal of the display device; and electrically connecting the first power rail to the second power source when the shutdown detection signal indicates that the display device is in a shutdown state. Track.

The invention solves the foregoing problems by adding a switch circuit to a conventional gate driving device composed of two power rail lines, two voltage generators, a voltage level converter and a gate driver. The switch circuit is electrically connected between the two power rails, and is used to determine whether to electrically connect the two power rails according to one of the display devices. As long as the shutdown detection signal indicates that the display device is in the off state, the switch circuit electrically connects the two power rails together, so that the two power rails can share residual charge to turn the voltage level converter The operating power supply is maintained for a period of time such that the voltage levels of the output signals of the buffers in the voltage level converter (ie, the third clock signal and the fourth clock signal) are maintained at a high level for the period of time. In this way, when the display device is turned off, all input signals of the gate driver are maintained at a high level during the period of time, so that the gate driver can output a high-level gate signal to be turned on during this period of time. The thin film transistor in each pixel allows the residual charge in each pixel to be quickly discharged by the thin film transistor to eliminate the residual image of the display device during shutdown.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

First embodiment:

1 is a schematic diagram of a gate driving device in accordance with an embodiment of the present invention. The gate driving device is suitable for a display device such as a liquid crystal display device. Referring to FIG. 1, the gate driving device includes a voltage generator 110, a voltage generator 120, a voltage level converter 130, a gate driver 140, a switching circuit 150, a power rail 170, and a power rail 180. The voltage generator 110 is electrically connected to the power rail 170 to output a voltage VGH to the power rail 170. The voltage generator 120 is electrically connected to the power rail 180 to output a voltage VGL to the power rail 180.

The voltage level converter 130 is electrically connected to the power rails 170 and 180, and is used to convert the high and low levels of the clock signal CLK1 outputted by the timing controller 160 to the levels of the voltages VGH and VGL, respectively. Clock signal CK1. The voltage level converter 130 is further configured to convert the high and low levels of the clock signal CLK2 output by the timing controller 160 to the levels of the voltages VGH and VGL, respectively, to form the clock signal CK2. The clock signal CK1 and the clock signal CK2 are mutually inverted. The gate driver 140 is electrically connected to the power rail 180 and the voltage level converter 130 to receive the voltage VGL and the clock signals CK1 and CK2, and accordingly generate at least one gate pulse signal GS. The switching circuit 150 is electrically connected between the power rails 170 and 180, and is configured to determine whether to electrically connect the power rail 170 to the power rail according to one of the display devices (not shown). Line 180.

The voltage level converter 130 includes buffers 132 and 134. The buffer 132 is electrically connected to the power rails 170 and 180 to treat the voltages VGH and VGL as their operating power sources. The buffer 132 is configured to convert the high and low levels of the clock signal CLK1 to the levels of the voltages VGH and VGL, respectively, to form the clock signal CK1. The buffer 134 is also electrically connected to the power rails 170 and 180 to treat the voltages VGH and VGL as their operating power sources. The buffer 134 is configured to convert the high and low levels of the clock signal CLK2 to the levels of the voltages VGH and VGL, respectively, to form the clock signal CK2.

In this example, the switch circuit 150 includes switches 151 and 152. The switch 151 has a first end 151-1, a second end 151-2 and a control end 151-3, and the first end 151-1 is electrically connected to the power rail 170, and the control end 151-3 is used for receiving the shutdown. The detection signal XON is used to determine whether or not to turn on. The switch 152 has a first end 152-1, a second end 152-2 and a control end 152-3, and the first end 152-1 is electrically connected to the second end 151-2 of the switch 151, and the second end 152- 2 is electrically connected to the power rail 180, and the control terminal 152-3 is configured to receive the shutdown detection signal XON to determine whether to conduct.

Since the shutdown detection signal XON has two levels, when the display device is turned off, the shutdown detection signal XON is switched from one of the terminals to the other, and the switches 151 and 152 must be turned on. Since the shutdown detection signal XON is generally at a high level when the display device is in normal operation, and the shutdown detection signal XON is generally at a low level when the display device is turned off, the switches 151 and 152 can all be implemented by using a P-type transistor. . In addition, in a preferred design, the switch circuit 150 can further include an impedance 153 electrically coupled between the second end 151-2 of the switch 151 and the first end 152-1 of the switch 152. This impedance 153 is realized, for example, by a resistor.

In this way, when the display device is turned off, the shutdown detection signal XON is switched from the high level to the low level, the switch circuit 150 electrically connects the power rails 170 and 180, so that the two power rails can be remnant. The charge is shared to maintain the operating power of the voltage level converter 130 for a period of time such that the voltage levels of the output signals (instant pulse signals CK1 and CK2) of the buffers in the voltage level converter 130 are at that time. Maintained at a high level. In other words, when the display device is turned off, all input signals of the gate driver 140 are maintained at a high level during the period of time, so that the gate driver 140 can output a high-level gate signal during the period of time. The GS turns on the thin film transistor in each pixel, so that the residual charge in each pixel can be quickly discharged by the thin film transistor to eliminate the residual image of the display device during shutdown.

It is worth mentioning that the gate driver used in the present invention may be implemented by an NMOS based GOA based on an N-type metal oxide semiconductor transistor, or a P-type metal oxide. Semiconductor transistor-based gate drive circuit substrate technology (PMOS based GOA) is implemented.

Second embodiment:

2 is a schematic diagram of a gate driving device in accordance with another embodiment of the present invention. Please refer to FIG. 2 and FIG. 1 at the same time. After comparing the two, it can be found that the difference between the two is the design of the switching circuit. As shown in FIG. 2, the voltage generators 110 and 120 are electrically connected to the power rails 170 and 180 through the switch circuit 250, and the switch circuit 250 is further configured to determine whether to or not the voltage generator 110 according to the shutdown detection signal XON. Cut off the power rails 170 and 180 with 120.

In this example, switch circuit 250 includes four switches, labeled 251, 252, 254, and 255, respectively. The switch 251 has a first end 251-1, a second end 251-2 and a control end 251-3, and the first end 251-1 is electrically connected to the power rail 170, and the control end 251-3 is used for receiving The shutdown detection signal XON is used to determine whether to turn on. The switch 252 has a first end 252-1, a second end 252-2 and a control end 252-3, and the first end 252-1 is electrically connected to the second end 251-2 of the switch 251, and the second end 252- 2 is electrically connected to the power rail 180, and the control terminal 252-3 is configured to receive the shutdown detection signal XON to determine whether to conduct.

The switch 254 has a first end 254-1, a second end 254-2 and a control end 254-3, and the first end 254-1 is electrically connected to the voltage generator 110, and the second end 254-2 is electrically connected to the switch. The first end 251-1 of the 251 is used, and the control end 254-3 is configured to receive the shutdown detection signal XON to determine whether to turn on. As for the switch 255, the first end 255-1, the second end 255-2 and the control end 255-3, and the first end 255-1 is electrically connected to the voltage generator 120, and the second end 255-2 is electrically The second end 252-2 of the switch 252 is connected, and the control end 255-3 is used to receive the shutdown detection signal XON, thereby determining whether to turn on. In addition, in a preferred design, the switch circuit 250 can further include an impedance 253 electrically coupled between the second end 251-2 of the switch 251 and the first end 252-1 of the switch 252. This impedance 253 is realized, for example, by a resistor.

Since the shutdown detection signal XON has two levels, when the display device is turned off, so that the shutdown detection signal XON is switched from one of the terminals to the other, the switches 251 and 252 must be turned on for charge sharing. Both switches 254 and 255 must be turned off to switch voltage generators 110 and 120 away from power rails 170 and 180 to prevent current from flowing back to voltage generators 110 and 120. Because the display device is in normal operation, the shutdown detection signal XON is generally at a high level, and when the display device is turned off, the shutdown detection signal XON is generally at a low level, so the switches 251 and 252 can be implemented by using a P-type transistor. Both switches 254 and 255 are implemented using N-type transistors.

With the teachings of the above embodiments, there are some basic operational steps in the art that can be summarized by the general knowledge, as shown in FIG. FIG. 3 is a flow chart of a method for removing an afterimage according to an embodiment of the invention. The image sticking elimination method is applicable to a display device. The display device has a gate driving device, and the gate driving device has a first power rail, a second power rail, a first voltage generator, a second voltage generator, and a voltage level. Converter with a gate driver. The first voltage generator is electrically connected to the first power rail to output the first voltage to the first power rail. The second voltage generator is electrically connected to the second power rail to output the second voltage to the second power rail. The voltage level converter is electrically connected to the first power rail and the second power rail, and is configured to convert the high and low levels of the first clock signal to the levels of the first voltage and the second voltage, respectively, to form A third clock signal. The voltage level converter is further configured to convert the high and low levels of a second clock signal to the levels of the first voltage and the second voltage, respectively, to form a fourth clock signal. The gate driver is electrically connected to the second power rail and the voltage level converter to receive the second voltage, the third clock signal and the fourth clock signal, and accordingly generate at least one gate pulse signal. As shown in FIG. 3, the steps of the image sticking elimination method include: obtaining a shutdown detection signal of the display device (as shown in step S302); and when the shutdown detection signal indicates that the display device is in a shutdown state, The first power rail is electrically connected to the second power rail (as shown in step S304).

Of course, the image sticking elimination method may further include the following steps: when the power-off detection signal indicates that the display device is in a shutdown state, the first voltage generator and the second voltage generator are separated from the first power rail and the first Two power rails.

In summary, the present invention solves the aforementioned problems by adding a conventional gate driving device composed of two power rails, two voltage generators, a voltage level converter and a gate driver. And a switching circuit electrically connected between the two power rails, and configured to determine whether to electrically connect the two power rails according to one of the display devices to turn off the detection signal. As long as the shutdown detection signal indicates that the display device is in the off state, the switch circuit electrically connects the two power rails together, so that the two power rails can share residual charge to turn the voltage level converter The operating power supply is maintained for a period of time such that the voltage levels of the output signals of the buffers in the voltage level converter (ie, the third clock signal and the fourth clock signal) are maintained at a high level for the period of time. In this way, when the display device is turned off, all input signals of the gate driver are maintained at a high level during the period of time, so that the gate driver can output a high-level gate signal to be turned on during this period of time. The thin film transistor in each pixel allows the residual charge in each pixel to be quickly discharged by the thin film transistor to eliminate the residual image of the display device during shutdown.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

110, 120. . . Voltage generator

130. . . Voltage level converter

140. . . Gate driver

150, 250. . . Switch circuit

151, 152. . . switch

151-1, 152-1, 251-1, 252-1, 254-1, 255-1. . . First end

151-2, 152-2, 251-2, 252-2, 254-2, 255-2. . . Second end

151-3, 152-3, 251-3, 252-3, 254-3, 255-3. . . Control terminal

153, 253. . . impedance

160. . . Timing control circuit

170, 180. . . Power rail

CLK1, CLK2, CK1, CK2. . . Clock signal

GS‧‧‧gate pulse signal

VGH, VGL‧‧‧ voltage

S302, S304‧‧‧ steps

XON‧‧‧Shutdown detection signal

1 is a schematic diagram of a gate driving device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a gate driving device in accordance with another embodiment of the present invention.

FIG. 3 is a flow chart of a method for removing an afterimage according to an embodiment of the invention.

110, 120. . . Voltage generator

130. . . Voltage level converter

140. . . Gate driver

150. . . Switch circuit

151, 152. . . switch

151-1, 152-1. . . First end

151-2, 152-2. . . Second end

151-3, 152-3. . . Control terminal

153. . . impedance

160. . . Timing control circuit

170, 180. . . Power rail

CLK1, CLK2, CK1, CK2. . . Clock signal

GS. . . Gate pulse signal

VGH, VGL. . . Voltage

XON. . . Shutdown detection signal

Claims (16)

A gate driving device is applicable to a display device, the gate driving device includes: a first power rail line; a second power rail line; a first voltage generator electrically connected to the first power rail line, The first voltage is output to the first power rail; a second voltage generator is electrically connected to the second power rail to output a second voltage to the second power rail; a voltage level conversion The device is electrically connected to the first power rail and the second power rail, and is configured to convert the high and low levels of a first clock signal to the first voltage and the second voltage, respectively. Forming a third clock signal, and converting the high and low levels of a second clock signal to the levels of the first voltage and the second voltage, respectively, to form a fourth clock signal; a gate driver The second power rail and the voltage level converter are electrically connected to receive the second voltage, the third clock signal and the fourth clock signal, and generate at least one gate pulse signal accordingly; And a switching circuit electrically connected to the first power rail and Between the second power rails, and determining whether to electrically connect the first power rail to the second power rail according to one of the display device shutdown detection signals, wherein the switch circuit includes: a first The switch has a first end, a second end and a first control end, the first end is electrically connected to the first power rail, and the first control end is configured to receive the shutdown detection signal, Determining whether to conduct; and a second switch having a third end, a fourth end, and a second control end, The third end is electrically connected to the second end of the first switch, the fourth end is electrically connected to the second power rail, and the second control end is configured to receive the shutdown detection signal, thereby determining whether Turn on. The gate driving device of claim 1, wherein the switching circuit further comprises: an impedance electrically connected between the second end of the first switch and the third end of the second switch . The gate driving device of claim 1, wherein the shutdown detection signal has a first level and a second level, and when the shutdown detection signal is converted from the first level to the When the second position is on time, the first switch and the second switch are both turned on. The gate driving device of claim 3, wherein the first level is a high level, the second level is a low level, and the first switch and the second switch are both a P type Crystal. The gate driving device of claim 1, wherein the voltage level converter comprises: a first buffer electrically connected to the first power rail and the second power rail, and used to The high and low levels of the first clock signal are respectively converted to the levels of the first voltage and the second voltage to form the third clock signal; and a second buffer electrically connected to the first power source The trajectory and the second power rail are used to convert the high and low levels of the second clock signal to the levels of the first voltage and the second voltage, respectively, to form the fourth clock signal. The gate driving device of claim 1, wherein the first voltage generator and the second voltage generator are electrically connected to the first power rail and the second power source respectively through the switch circuit. a trajectory, and the switch circuit is further configured to determine whether to cut the first voltage generator and the second voltage generator from the first power trajectory and the second power trajectory according to the shutdown detection signal. The gate driving device of claim 6, wherein the switch circuit comprises: a first switch having a first end, a second end and a first control end, wherein the first end is electrically connected The first power control line is configured to receive the shutdown detection signal to determine whether to conduct; and the second switch has a third end, a fourth end, and a second control end. The third end is electrically connected to the second end of the first switch, the fourth end is electrically connected to the second power rail, and the second control end is configured to receive the shutdown detection signal, thereby determining whether The third switch has a fifth end, a sixth end, and a third control end. The fifth end is electrically connected to the first voltage generator, and the sixth end is electrically connected to the first switch. The first end, the third control end is configured to receive the shutdown detection signal to determine whether to conduct; and the fourth switch has a seventh end, an eighth end, and a fourth control end, The seventh end is electrically connected to the second voltage generator, and the eighth end is electrically connected to the second switch The fourth terminal is configured to receive the shutdown detection signal to determine whether to turn on. The gate driving device of claim 7, wherein the gate driving device The switching circuit further includes: an impedance electrically connected between the second end of the first switch and the third end of the second switch. The gate driving device of claim 7, wherein the shutdown detection signal has a first level and a second level, and when the shutdown detection signal is converted from the first level to the When the second position is on time, the first switch and the second switch are both turned on, and the third switch and the fourth switch are both turned off. The gate driving device of claim 7, wherein the first level is a high level, the second level is a low level, and the first switch and the second switch are both a P type a crystal, and the third switch and the fourth switch are both an N-type transistor. The gate driving device of claim 7, wherein the voltage level converter comprises: a first buffer electrically connected to the first power rail and the second power rail, and used to The high and low levels of the first clock signal are respectively converted to the levels of the first voltage and the second voltage to form the third clock signal; and a second buffer electrically connected to the first power source The trajectory and the second power rail are used to convert the high and low levels of the second clock signal to the levels of the first voltage and the second voltage, respectively, to form the fourth clock signal. The gate driving device of claim 1, wherein the gate driver comprises a gate driving circuit substrate technology based on an N-type metal oxide semiconductor transistor, or is oxidized by a P-type metal. Semi-guide The body transistor is based on the gate drive circuit substrate technology. The gate driving device of claim 1, wherein the first clock signal and the second clock signal are opposite to each other. The gate driving device of claim 1, wherein the first clock signal and the second clock signal are output by a timing controller. An image sticking elimination method is applicable to a display device having a gate driving device, and the gate driving device further has a first power rail line, a second power rail line, and a first voltage generator a second voltage generator, a voltage level converter and a gate driver, the first voltage generator is electrically connected to the first power rail to output a first voltage to the first power rail, The second voltage generator is electrically connected to the second power rail to output a second voltage to the second power rail, and the voltage level converter is electrically connected to the first power rail and the second power a trajectory for converting a high and a low level of a first clock signal to a level of the first voltage and the second voltage, respectively, to form a third clock signal, and a second clock signal The high and low levels are respectively converted to the levels of the first voltage and the second voltage to form a fourth clock signal, and the gate driver is electrically connected to the second power rail and the voltage level conversion To receive the second voltage, the third clock And the fourth clock signal, and accordingly generating at least one gate pulse signal, the image removal method comprising: obtaining a shutdown detection signal of the display device; and displaying the display device when the shutdown detection signal is displayed When the power is turned off, the first power rail is electrically connected to the second power rail. The method of removing the afterimage according to claim 15 , wherein the method of removing the image further comprises: when the shutdown detection signal indicates that the display device is in a shutdown state, the first voltage generator is The second voltage generator cuts away from the first power rail and the second power rail.