TWI440307B - Output pad system and pad driving circuit thereof - Google Patents

Description

Output pad system and pad driving circuit

The present invention relates to a pad drive circuit, and more particularly to a pad drive circuit for an input/output system.

The time it takes to output the signal transition process is related to the Slew rate, which can be expressed as the voltage change (dv/dt) per unit time. Ideally, the rate of rotation should be infinite, allowing the output signal to transition from one logic state to another in an instant. However, the law of inertia in nature tends to maintain the status quo, and the output pad circuit components of the integrated circuit also store energy, causing the logic state to not change instantaneously, and the output signal takes a long time to switch from a logic state to Another logic state, thus reducing the transition speed of the integrated circuit.

Today's electronic systems require an integrated circuit that can switch at high speed. For example, integrated circuit signals applied to communication systems must comply with applicable communication specifications and protocols, such as Small Computer Standard Interface Protocol (SCSI), Peripheral Component Interconnect (PCI) bus protocol, and the like. These protocols specify the strength of the drive signal, the delay time of the signal from input to output, and the rate of rotation of the output signal. However, when the load area connected to the output pad of the integrated circuit changes, it is not easy to immediately conform to the aforementioned specifications.

Therefore, a new pad circuit driver architecture is needed to improve the timing of the output signals transmitted by the pad circuits while maintaining the original pad circuit area.

Therefore, in one aspect of the present invention, a pad driving circuit is provided, and the timing of the output signal transmitted by the pad circuit can be improved without increasing the area of the pad circuit, so that the output signal can quickly complete the logic transition.

According to an embodiment of the invention, the pad driving circuit includes an output control circuit, a voltage pump circuit, a first buffer string, and a second buffer string. The output control circuit controls whether a pad circuit can deliver an input signal, wherein the output control circuit enables the pad circuit to output an input signal when the coincidence signal is asserted. The voltage boost circuit generates a negative supply voltage, wherein the negative supply voltage has a voltage value less than zero volts. The first buffer string is electrically connected between the output control circuit and the pad circuit to transmit an inverting input signal, and drives the pad circuit with a positive supply voltage and a negative supply voltage from one of the voltage pump circuits. The second buffer string drives the pad circuit with a ground voltage and a positive supply voltage.

Another aspect of the present invention is to provide an output pad system that can improve the timing of the output signal transmitted by the pad circuit without increasing the area of the pad circuit, so that the output signal can quickly complete the logic transition.

In accordance with another embodiment of the present invention, an output pad system includes a pad circuit, an output control circuit, a voltage pump circuit, a first buffer string, and a second buffer string. The output control circuit controls whether the pad circuit can transmit an input signal; when the coincidence signal is asserted, the output control circuit enables the pad circuit to output an input signal. The voltage boost circuit generates a negative supply voltage, wherein the negative supply voltage has a voltage value less than zero volts. The first buffer string is electrically connected between the output control circuit and the pad circuit to transmit an inverting input signal, wherein the first buffer string is connected with a positive supply voltage and a negative supply voltage from one of the voltage pump circuits Drive the pad circuit. The second buffer string drives the pad circuit with a ground voltage and a positive supply voltage.

According to the above embodiment, the pad driving circuit and the output pad system can shorten the rise time and the fall time occupied by the output signal transition state, improve the timing of the output signal transmitted by the pad circuit, and enable the output signal to quickly complete the logic transfer. state.

In the following embodiment, the output pad is driven by the negative supply voltage generated by the voltage boost circuit, thereby reducing the reaction time or the transition time of the signal outputted by the pad, thereby increasing the operating speed of the whole bulk circuit.

Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a waveform diagram of a mobile phone signal according to an embodiment of the present invention, and FIG. 1B is a timing chart of a mobile phone signal according to an embodiment of the present invention. In the first picture 1A, 1B, the signal 1 will display the message carried by the bus DB as instruction or data. When the signal 3 is asserted in the index period (low logic level), the signal 1 will be Sampling, followed by a Dummy read cycle. After the index period and the imitation read cycle, the output pad circuit should be ready for the external read at the leading edge or the falling edge of the signal 2 during the access cycle. For example, if the index period and the imitation read period occupy 66 ns and 160 ns, respectively, the negative supply voltage VBBS should be ready after 226 ns (66 ns + 160 ns).

In the interval B of Figure 1B and when signal 4 is asserted (low logic level), the external logic circuit will start the operation of the logic function. When the operation results, the result will be busbar in interval C. The output pad circuit is output. If the pad circuit can quickly increase the bus signal to V _OH , the operating time of the mobile phone will be shortened.

Please refer to FIG. 2A, which is a circuit diagram of an output pad system according to an embodiment of the invention. The output pad system 229 includes a pad driving circuit 219 and a pad circuit 221, wherein the pad circuit 221 includes a P-channel MOS half-effect transistor (PMOS) M1 driven by the first buffer string 209, and The N-channel MOS half-effect transistor (NMOS) M2 driven by the second buffer string 211.

The output control circuit 213 is responsible for controlling whether the pad circuit 221 can deliver an input signal, wherein when the enable signal is asserted (eg, a high logic level), the output control circuit 213 enables the pad circuit 221 to output an input signal. For example, when the enable signal Enable is at a low logic level, such as 0 volts, the output control circuit 213 turns off the PMOS M1 and the NMOS M2 to cause the pad output 埠 to float (Float); when the enable signal Enable is A high logic level turns on PMOS M1 and NMOS M2 to pass the input signal.

The second buffer string 211 includes an odd number of second inverters 217 that receive the positive supply voltage IOVCC from the external system and the ground voltage VSSD from the ground terminal, thus the second The buffer string 211 drives the pad circuit with the positive supply voltage IOVCC and the ground voltage VSSD. Since the voltage of the control output 2 received by the PMOS and the NMOS of the second inverter 217 is substantially equal to the positive supply voltage IOVCC or the ground voltage VSSD, the second inverter 217 of the second buffer string 211 The PMOS and NMOS (not shown) are not turned on at the same time, so the short-circuit current is reduced.

The first buffer string 209 is electrically connected between the output control circuit 213 and the pad circuit 221 to transmit the inverted input signal. The first buffer string 209 includes an even number of first inverters 215. This first buffer string 209 drives the pad circuit 221 with the positive supply voltage IOVCC and the negative supply voltage VBBS from the voltage pump circuit 223. Since the voltage of the control output 1 received by the NMOS in the first first inverter 215 is greater than the negative supply voltage VBBS, the PMOS and NMOS in the first inverter 215 of the first buffer string 209 (not Shown in the figure) will be turned on at the same time to induce short-circuit current. Therefore, it is necessary to reduce the area of the first inverter 215 adjacent to the output control circuit 213 to reduce the short-circuit current.

Voltage boost circuit 223 produces a supply voltage of less than 0 volts, such as -1 volts. The voltage pump circuit 223 includes an oscillator 201 and a charge pump group 225. The oscillator 201 is a multi-stage oscillator, such as the three-stage oscillator shown in FIG. 2C. The multi-stage oscillator 201 includes a first inverter 301, a second inverter 303, and a third inverter 305. . The first inverter 301 outputs a first phase signal P1, and the second inverter 303 is electrically connected to the first inverter 301 and outputs a second phase signal P2. The third inverter 305 is electrically connected between the second inverter 303 and the first inverter 301 to output a third phase signal P3. The phases of the three phase signals (P1, P2, P3) are different. More specifically, the second phase signal P2 lags behind the first phase signal P1, and the third phase signal P3 lags behind the second phase signal P2.

In FIG. 2B, the charge pump group 225 converts the positive supply voltage IOVCC into the negative supply voltage VBBS according to the voltage levels of the first phase signal P1, the second phase signal P2, and the third phase signal P3. The charge pump group 225 includes a first charge pump 203, a second charge pump 205, and a third charge pump 207. The pump circuits receive the first phase signal P1, the second phase signal P2, and the third phase, respectively. Signal P3.

More specifically, the first charge pump 203 illustrated in FIG. 2C includes a first storage capacitor CP1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.

The first switch S1 is electrically connected between the first end A1 of the first storage capacitor CP1 and the ground terminal that supplies the ground voltage VSSD. The first switch S1 determines whether to conduct according to the first phase inversion signal P1'. The first phase inversion signal P1' is an inverse of the first phase signal P1. The third switch S3 is electrically connected between the second end B1 of the first storage capacitor CP1 and the power supply end that supplies the positive supply voltage IOVCC. The third switch S3 is also determined according to the first phase inversion signal P1'. Turn on. When the first phase inversion signal P1' turns on the first switch S1 and the third switch S3, the positive supply voltage IOVCC charges the first storage capacitor CP1, and the voltage IOVCC can be stored in the first storage capacitor CP1 at this stage. .

The second switch S2 is electrically connected between the second end B1 of the first storage capacitor CP1 and the ground terminal that supplies the ground voltage VSSD. The second switch S2 determines whether to conduct according to the first phase signal P1. The fourth switch S4 is electrically connected between the first end A1 of the first storage capacitor CP1 and the load CL. The fourth switch S4 also determines whether to conduct according to the first phase signal P1.

When the second switch S2 and the fourth switch S4 are turned on, the second end B1 of the first storage capacitor CP1 is connected to the ground, and the voltage stored on the first storage capacitor CP1 converts the voltage on the first end A1 into a negative voltage. (-IOVCC). Therefore, the first terminal A1 will be able to provide a negative supply voltage VBBS. In fact, the voltage value at the first terminal A1 is related to the ratio of the capacitance of the first storage capacitor CP1 to the load capacitor CL; when the ratio of the two capacitors is larger, the closer the voltage of the first terminal A1 after conversion is closer to -IOVCC .

The second charge pump 205 includes a second storage capacitor CP2, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The second charge pump 205 is controlled by the second phase signal P2 and the second phase inverted signal P2'. The phase of the second phase signal P2 is different from the phase of the first phase signal P1, and the second phase inverted signal P2 'There is an inverse of the second phase signal P2, which operates similarly to the first charge pump 203. Since the node providing the negative supply voltage VBBS can be charged by the first charge pump 203 and the second charge pump 205 at different times, the negative supply voltage VBBS can be constantly updated to maintain its voltage value.

According to the above embodiment, the pad driving circuit and the output pad system use a negative supply voltage to drive the P-channel MOS field-effect transistor (PMOS) of the output pad circuit, thereby increasing the current of the output pad circuit PMOS. The charging time is reduced, so the transition time and driving capability of the output pad are also increased, thereby increasing the operating speed of the entire bulk circuit.

The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

201. . . Oscillator

203. . . First charge pump

205. . . Second charge pump

207. . . Third charge pump

209. . . First buffer string

211. . . Second buffer string

213. . . Output control circuit

215. . . First inverter

217. . . Second inverter

219. . . Pad drive circuit

221. . . Pad circuit

223. . . Voltage boost circuit

225. . . Charge pump group

229. . . Output pad system

301. . . First inverter

303. . . Second inverter

305. . . Third inverter

A1. . . First end

A2. . . First end

B1. . . Second end

B2. . . Second end

CP1. . . First storage capacitor

M1. . . Transistor

M2. . . Transistor

P1. . . First phase signal

P1’. . . First phase inverted signal

P2. . . Second phase signal

P2’. . . Second phase inverted signal

P3. . . Third phase signal

P3’. . . Third phase inverted signal

S1. . . First switch

S2. . . Second switch

S3. . . Third switch

S4. . . Fourth switch

S5. . . Fifth switch

S6. . . Sixth switch

S7. . . Seventh switch

S8. . . Eighth switch

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

Fig. 1A is a waveform diagram showing a mobile phone signal according to an embodiment of the present invention.

FIG. 1B is a timing diagram showing a mobile phone signal according to an embodiment of the present invention.

2A is a circuit diagram showing an output pad system in accordance with an embodiment of the present invention.

2B is a block diagram showing an output pad system in accordance with an embodiment of the present invention.

2C is a circuit diagram showing a charge pump circuit according to an embodiment of the present invention.

201. . . Oscillator

209. . . First buffer string

211. . . Second buffer string

213. . . Output control circuit

215. . . First inverter

217. . . Second inverter

219. . . Pad drive circuit

221. . . Pad circuit

223. . . Voltage boost circuit

225. . . Charge pump group

229. . . Output pad system

Claims (14)

A pad driving circuit includes: an output control circuit for controlling whether a pad circuit can transmit an input signal, wherein the output control circuit enables the pad circuit to output the input signal when the coincidence signal is asserted a voltage pump circuit for generating a negative supply voltage, wherein the voltage of the negative supply voltage is less than zero volts, wherein the voltage pump circuit comprises: an oscillator to generate a first phase signal; and a charge a group of pulses to generate the negative supply voltage, wherein the charge pump group converts a positive supply voltage to the negative supply voltage according to one of the voltage levels of the first phase signal; a first buffer string Electrically coupled between the output control circuit and the pad circuit for transmitting an inverting input signal, wherein the first buffer string is the positive supply voltage and the negative supply voltage from the voltage pump circuit Driving the pad circuit; and a second buffer string driving the pad circuit with a ground voltage and the positive supply voltage. The pad driving circuit of claim 1, wherein the oscillator is a multi-stage oscillator, the multi-stage oscillator comprising: a first inverter to output the first phase signal; and a second counter a phase detector electrically connected to the first inverter to output the second phase signal; and a third inverter electrically connected to the second inverter and the first reverse Between the phase converters, a third phase signal is output, wherein phases of the first phase signal, the second phase signal, and the third phase signal are different. The pad driving circuit of claim 2, wherein the charge pump group comprises a first charge pump, the first charge pump comprising: a first storage capacitor; a first switch electrically connected to Between a first end of the first storage capacitor and a ground terminal for providing the ground voltage, the first open relationship determines whether to conduct according to a first phase inversion signal; and a second switch electrically connected to the Between the second end of the first storage capacitor and the ground terminal that provides the ground voltage, wherein the second open relationship determines whether to conduct according to the first phase signal; a third switch is electrically connected to the first Between the second end of the storage capacitor and a power supply terminal that provides the positive supply voltage, wherein the third open relationship determines whether to conduct according to the first phase inverted signal; and a fourth switch electrically connected to The first end of the first storage capacitor is coupled to a load, wherein the fourth open relationship determines whether to be turned on according to the first phase signal. The pad driving circuit of claim 3, wherein the charge pump group further comprises a second charge pump, the second charge pump comprising: a fifth switch electrically connected to the second storage capacitor Between the first end and the ground, wherein the fifth open relationship determines whether to conduct according to the second second phase inversion signal; a sixth switch electrically connected between the second end of the second storage capacitor and the ground, wherein the sixth open relationship determines whether to conduct according to the second phase signal; a seventh switch, electrical Connected between the second end of the second storage capacitor and a power supply terminal that provides the positive supply voltage, wherein the seventh open relationship determines whether to conduct according to the second phase inversion signal; and an eighth switch And electrically connected between the load and the first end of the second storage capacitor, wherein the eighth open relationship determines whether to be turned on according to the second phase signal. The pad driving circuit of claim 1, wherein the first buffer string drives one of the pad circuits, a P-channel MOS field effect transistor. The pad drive circuit of claim 5, wherein the first buffer string comprises an even number of first inverters to receive the positive supply voltage and the negative supply voltage to drive the pad circuit. The pad drive circuit of claim 6, wherein the second buffer string comprises an odd number of second inverters to receive the positive supply voltage and the negative supply voltage to drive the pad circuit. An output pad system comprising: a pad circuit; An output control circuit for controlling whether the pad circuit can transmit an input signal, wherein the output control circuit enables the pad circuit to output the input signal when the coincidence signal is asserted; a voltage pump circuit to Generating a negative supply voltage, wherein the negative supply voltage has a voltage value less than zero volts, wherein the voltage pump circuit includes: an oscillator to generate at least one first phase signal; and a charge pump group to generate the a negative supply voltage, wherein the charge pump group converts a positive supply voltage to the negative supply voltage according to a voltage level of the first phase signal; a first buffer string electrically connected to the output An inverting input signal is transmitted between the control circuit and the pad circuit, wherein the first buffer string drives the pad circuit with the positive supply voltage from the voltage pump circuit and the negative supply voltage; A second buffer string drives the pad circuit with a ground voltage and the positive supply voltage. The output pad system of claim 8, wherein the oscillator is a multi-stage oscillator, the multi-stage oscillator comprising: a first inverter to output the first phase signal; and a second counter a phaser electrically connected to the first inverter to output the second phase signal; and a third inverter electrically connected between the second inverter and the first inverter to A third phase signal is output, wherein phases of the first phase signal, the second phase signal, and the third phase signal are different. The output pad system of claim 9, wherein the charge pump group comprises a first charge pump, the first charge pump comprising: a first storage capacitor; a first switch electrically connected to Between the first end of the first storage capacitor and one of the ground terminals for providing the ground voltage, wherein the first open relationship determines whether to conduct according to a first phase inversion signal; and a second switch is electrically connected to Between the second end of the first storage capacitor and the ground terminal that provides the ground voltage, wherein the second open relationship determines whether to conduct according to the first phase signal; a third switch is electrically connected to the first Between the second end of a storage capacitor and a power supply end that provides the positive supply voltage, wherein the third open relationship determines whether to conduct according to the first phase inverted signal; and a fourth switch that is electrically connected And between the first end of the first storage capacitor and a load, wherein the fourth open relationship determines whether to be turned on according to the first phase signal. The output pad system of claim 10, wherein the charge pump group further comprises a second charge pump, the second charge pump comprising: a fifth switch electrically connected to the second storage capacitor Between the first end and the ground, wherein the fifth open relationship determines whether to conduct according to a second phase inversion signal; a sixth switch electrically connected to the second end of the second storage capacitor And the grounding end, wherein the sixth open relationship determines whether to be turned on according to the second phase signal; a seventh switch electrically connected between the second end of the second storage capacitor and a power supply end that provides the positive supply voltage, wherein the seventh open relationship is based on the inverted second phase signal Determining whether to conduct; and an eighth switch electrically connected between the load and the first end of the second storage capacitor, wherein the eighth open relationship determines whether to be turned on according to the second phase signal. The output pad system of claim 8, wherein the pad circuit comprises: a P-channel metal oxide half field effect transistor driven by the first buffer string; and an N-channel MOS half field effect transistor And electrically connected to the P-channel MOS field-effect transistor, wherein the N-channel MOSFET is driven by the second buffer string. The output pad system of claim 12, wherein the first buffer string comprises an even number of first inverters to receive the positive supply voltage and the negative supply voltage to drive the pad circuit. The output pad system of claim 12, wherein the second buffer string comprises an odd number of second inverters to receive the positive supply voltage and the negative supply voltage to drive the pad circuit.